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11. 发明授权

US4045692A Solid state binary logic signal source for electronic timepiece or the like 失效
标题翻译：用于电子定时或类似的固态二进制逻辑信号源
公开(公告)号：US4045692A
公开(公告)日：1977-08-30
申请号：US615850
申请日：1975-09-23
申请人： Shigeru Morokawa , Fukuo Sekiya
发明人： Shigeru Morokawa , Fukuo Sekiya
IPC分类号： G04F5/00 , G04G5/02 , G04G21/00 , G04G99/00 , H03K5/02 , H03K17/00 , H03K19/0944 , H03K3/353 , G04C3/00 , H03K3/286 , H03K17/04
CPC分类号： G04F5/00 , G04G5/02 , H03K5/023
摘要： An inverting amplifier is provided with a high impedance input resistor connected at one end to an input terminal of the amplifier and connected at the other end to a first voltage source constituting a first binary logic level. The input terminal is also connected through a switch to a second voltage source constituting a second and opposite binary level. An MOS-FET has source and drain electrodes connected to the input terminal and the first voltage source respectively and a gate electrode connected to an output terminal of the amplifier. When the switch is closed, the second voltage is applied to the input terminal and the inverted output of the amplifier turns off the MOS-FET. When the switch is open, the first voltage is applied to the input terminal through the resistor and the inverted output of the amplifier turns on the MOS-FET. The low impedance of the MOS-FET in the turned on condition increases the stability of the amplifier under high humidity conditions.

12. 发明授权

US4016476A Booster circuits 失效
标题翻译：加速电路
公开(公告)号：US4016476A
公开(公告)日：1977-04-05
申请号：US630811
申请日：1975-11-11
申请人： Shigeru Morokawa , Fukuo Sekiya
发明人： Shigeru Morokawa , Fukuo Sekiya
IPC分类号： G04G19/04 , G04G19/08 , H02M3/07 , H03K5/003 , H03K5/02 , H03K19/0185 , H03K19/094 , H02M7/00
CPC分类号： H03K19/018507 , G04G19/04 , G04G19/08 , H02M3/07 , H03K19/094 , H03K5/003 , H03K5/023
摘要： An input line carrying a square-wave voltage is connected through a capacitor to the drain and via an inverter to the gate of a MOSFET acting as a diode, the relative magnitudes of the drain and gate pulses being so chosen that the FET conducts during alternate half-cycles of the square wave whereby the capacitor is charged during nonconductive half-cycles and is fully discharged to the potential of the source of the FET during conductive half-cycles. If the source is biased by a constant voltage, a square wave in a higher voltage range is available at the drain. If the source is connected to potential through another capacitance, a d-c voltage is available at that electrode. Complementary MOSFET/diodes can be connected in push-pull or in cascade to amplify the input voltage; they may also be combined with supplementary voltage boosters including cascaded stages composed of ordinary diodes and capacitors. The MOSFET/diode may be part of an electronic clock drive.
摘要翻译：承载方波电压的输入线通过电容器连接到漏极，并且通过反相器连接到用作二极管的MOSFET的栅极，所以选择漏极和栅极脉冲的相对幅度，使得FET在交替期间导通方波的半周期，由此电容器在非导通半周期期间被充电，并且在导电半周期期间完全放电到FET源极的电位。如果源被恒定电压偏置，则在漏极处可获得较高电压范围内的方波。如果源极通过另一个电容连接到电位，那么在该电极处可以获得d-c电压。互补MOSFET /二极管可以以推挽或级联方式连接，以放大输入电压; 它们还可以与包括由普通二极管和电容器组成的级联级的辅助升压器组合。 MOSFET /二极管可能是电子时钟驱动器的一部分。

13. 发明授权

US4015419A Electronic timepiece 失效
标题翻译：电子钟表
公开(公告)号：US4015419A
公开(公告)日：1977-04-05
申请号：US658037
申请日：1976-02-13
申请人： Shigeru Morokawa , Yukio Hashimoto
发明人： Shigeru Morokawa , Yukio Hashimoto
IPC分类号： G04F5/06 , G04G3/02 , G06F7/68 , G04C3/00
CPC分类号： G04F5/06 , G04G3/022 , G06F7/68
摘要： To facilitate acceleration or deceleration of the stepping rate of a time-keeping counter responding to driving pulses from a frequency divider connected to a crystal-controlled oscillator, a succession of such driving pulses is taken from an OR gate with inputs receiving a basic pulse train .phi..sub..gamma. a normally present first ancillary pulse train .phi..sub..beta. spacedly interleaved with pulse train .phi..sub..gamma. and a normally absent second ancillary pulse train .phi..sub..alpha. with pulse positions offset from those of the other two pulse trains. To retard the timepiece, the pulses of train .phi..sub..beta. are blocked for a desired period; to advance it, pulses of train .phi..sub..alpha. are interpolated at a rate depending on the cadence of a series of control pulses selectively synthesized from a combination of low-frequency stage outputs of the frequency divider. Externally set selection signals are temporarily stored in a memory circuit including NOR gates with positive-feedback connections to inverting inputs thereof, the memory circuit being periodically tested by a resetting pulse recurring at a frequency lower than that of the driving pulses.
摘要翻译：为了便于对来自连接到晶体振荡器的分频器的驱动脉冲响应的计时器的步进速度的加速或减速，从OR门获取一系列这样的驱动脉冲，其中输入接收基本脉冲串 phiγ是与脉冲串phiγ间隔地交错的正常存在的第一辅助脉冲串phiβ和具有与其他两个脉冲序列的脉冲位置偏移的脉冲位置的正常缺少的第二辅助脉冲串phiα。为了延迟时计，火车phi beta的脉冲被阻挡一段期望的时间; 为了使其前进，列车速率α的脉冲以取决于从分频器的低频级输出的组合选择合成的一系列控制脉冲的频率的速率内插。外部选择信号被临时存储在包括具有与其反相输入端的正反馈连接的NOR门的存储器电路中，存储器电路通过以低于驱动脉冲的频率重复的复位脉冲周期性地测试。

14. 发明授权

US5101116A Multi-level voltage generator to drive LCD 失效
标题翻译：多级电压发电机驱动LCD
公开(公告)号：US5101116A
公开(公告)日：1992-03-31
申请号：US513276
申请日：1990-04-24
申请人： Shigeru Morokawa
发明人： Shigeru Morokawa
IPC分类号： G02F1/133 , G09G3/04 , G09G3/18 , G09G3/30 , G09G3/36 , H03K5/15
CPC分类号： G09G3/3696 , G09G3/30 , G09G3/3674 , G09G2310/0289 , G09G2330/12
摘要： A display drive circuit including a pulse generator means; a variable voltage source circuit including a first voltage source line (VD.sub.t) with a variable potential, a second voltage source line (VS.sub.t) with a potential different from the first voltage source line by a constant value, having a voltage waveform, a variation period and a variation component the same as the first voltage source line, and varying in potential with a potential level not more than the lowest potential level of the first voltage source line, and other voltage source lines with constant potential levels between the potentials of the first and second voltage source lines; and an integrated circuit having an electronic switch which switches at a constant period the connection of the voltage source lines so as to make a plurality of constant waveform voltages, outputting these to a plurality of output terminals at constant phase difference.

15. 发明授权

US4679043A Method of driving liquid crystal matrix display 失效
标题翻译：驱动液晶矩阵显示的方法
公开(公告)号：US4679043A
公开(公告)日：1987-07-07
申请号：US566075
申请日：1983-12-27
申请人： Shigeru Morokawa
发明人： Shigeru Morokawa
IPC分类号： G02F1/133 , G02F1/1343 , G09F9/30 , G09G3/36
CPC分类号： G09G3/3644
摘要： A drive method for a liquid crystal matrix display panel whereby the display is driven as two or more separate regions, with each region being successively driven by row and column drive signals to display video data in a row-by-row manner during a drive phase while the remaining regions operate in a rest phase in which a potential substantially equal to zero is applied across the display elements of these other regions. The effective number of row electrodes to which sequential scanning signal pulses are applied, which determines the level of contrast obtainable with such a display panel when the number of display elements is large, is made equal to the number of row electrodes of each of these regions, so that a sufficiently high number of elements for high-resolution television display is attainable with a simple display panel and peripheral circuit configuration.
摘要翻译：一种用于液晶矩阵显示面板的驱动方法，由此显示器被驱动为两个或更多个分开的区域，每个区域由行和列驱动信号连续地驱动，以在驱动阶段以逐行的方式显示视频数据而其余区域在休止阶段中工作，其中在这些其他区域的显示元件上施加基本上等于零的电位。当施加顺序扫描信号脉冲的行电极的有效行数确定当显示元件数量大时可以用这种显示面板获得的对比度的水平等于这些区域中的每一个的行电极数，因此通过简单的显示面板和外围电路结构，可以获得足够高数量的用于高分辨率电视显示的元件。

16. 发明授权

US4630122A Television receiver with liquid crystal matrix display panel 失效
标题翻译：电视接收机配有液晶矩阵显示面板
公开(公告)号：US4630122A
公开(公告)日：1986-12-16
申请号：US592172
申请日：1984-03-22
申请人： Shigeru Morokawa
发明人： Shigeru Morokawa
IPC分类号： H04N5/66 , G02F1/133 , G09G3/20 , G09G3/36 , H04N3/12 , H04N5/44 , H04N5/70 , H04N3/14
CPC分类号： H04N3/127 , G09G3/3644 , G09G2320/0209 , G09G2320/041 , G09G2360/18 , G09G3/2014 , G09G3/3614
摘要： A television receiver is equipped with a liquid crystal matrix display panel having the drive electrodes arranged such as to form a plurality of regions, with the regions each successively entering a drive phase of operation in which selection and bias drive signals are applied to the display element electrodes and a rest phase of operation in which a voltage level substantially equal to zero is applied between the display element electrodes, with only one region operating in the drive phase at a time and the remaining regions operating in the rest phase. The display contrast attainable with a given number of rows of picture elements in the display can thereby be substantially increased, e.g. can be effectively doubled for the case of a display divided into two regions, without the need to utilize large-capacity video memory circuits.
摘要翻译：电视接收机配有液晶矩阵显示面板，其具有布置成形成多个区域的驱动电极，各区域各自依次进入操作的驱动阶段，其中选择和偏置驱动信号被施加到显示元件电极和其中在显示元件电极之间施加基本上等于零的电压等级的操作的休止阶段，一次只有一个区域在驱动阶段中操作，并且其余区域在休止阶段中操作。因此显示器中的给定数量的像素行可以实现的显示对比度可以大大增加，例如，对于分为两个区域的显示器的情况，可以有效地加倍，而不需要利用大容量视频存储器电路。

17. 发明授权

US4581649A Image pickup system 失效
标题翻译：摄像系统
公开(公告)号：US4581649A
公开(公告)日：1986-04-08
申请号：US593831
申请日：1984-03-27
申请人： Shigeru Morokawa
发明人： Shigeru Morokawa
IPC分类号： H04N1/409 , H04N5/225 , H04N5/335 , H04N5/372 , H04N5/374 , H04N5/378 , H04N3/14
CPC分类号： H04N5/2176 , H04N1/409 , H04N3/1587 , H04N5/2259
摘要： An image pickup system has an image sensor including a plurality of photodetectors arranged in two dimensions and an optical system having a lens for forming an image on the image sensor so that the image sensor produces picture data. A vibrator is provided for vibrating the image on the image sensor so as to oscillate the picture data, and a scanner is provided to be operative in synchronism with the vibration of the image for changing the oscillated picture data to data for a fixed image. A memory is provided for storing the data for a fixed image and a majority logic circuit is provided for selecting the most reliable data from the data stored in the memory and for producing a picture data for the image on the image sensor.
摘要翻译：图像拾取系统具有图像传感器，其包括以二维布置的多个光电检测器，以及具有用于在图像传感器上形成图像的透镜的光学系统，使得图像传感器产生图像数据。提供振动器用于使图像传感器上的图像振动以便振荡图像数据，并且提供扫描器以与用于将振荡的图像数据改变为固定图像的数据的图像的振动同步地操作。提供存储用于固定图像的数据的存储器，并且提供多数逻辑电路用于从存储在存储器中的数据中选择最可靠的数据，并且用于在图像传感器上产生图像的图像数据。

18. 发明授权

US4465999A Matrix driving method for electro-optical display device 失效
公开(公告)号：US4465999A
公开(公告)日：1984-08-14
申请号：US99805
申请日：1979-12-03
申请人： Akira Tsuzuki , Hiro Fujita , Shigeru Morokawa
发明人： Akira Tsuzuki , Hiro Fujita , Shigeru Morokawa
IPC分类号： G02F1/1345 , G09F9/302 , G09G3/18 , G09G3/36
CPC分类号： G02F1/1345 , G09F9/302 , G09G3/18 , G09G3/3622 , G09G3/3681 , G09G3/3692
摘要： A method of cyclically driving an electro-optical display device having a matrix array of a plurality of row electrodes and a plurality of column electrodes, wherein said column electrodes intersect with said row electrodes to provide a plurality of display elements at intersections between said row and column electrodes, comprising the steps of: applying row drive signals to said row electrodes, respectively; and applying one of first, second and third column drive signals to each of said column electrodes, with said first column drive signal inducing a non-display state at all of the display elements along each column electrode, said second column drive signal inducing a non-display state at a single display element along said each column electrode and inducing a display state at the other two display elements along said each column electrode, and said third column drive signal inducing a display state at all of the display elements along said each column electrode; wherein each of said row drive signals takes a plurality of voltage potentials during a half cycle period divided into prescribed time intervals and one of said row drive signals takes one of said voltage potentials different from those of the other of said row drive signals during each of said prescribed time intervals; and wherein said first column drive signal takes a reference voltage potential equal to the mean value of said voltage potentials of said row drive signals during said prescribed time intervals of said half cycle period, said second column drive signal takes a first voltage potential different from those of said row drive signals during one of said prescribed time interval, said reference voltage potential during another one of said prescribed time intervals, and a second voltage potential different from those of said row drive signals during another one of said prescribed time intervals, and said third column drive signal takes the first and second voltage potentials during each of said prescribed time intervals.

19. 发明授权

US4441826A Electronic timepiece 失效
标题翻译：电子钟表
公开(公告)号：US4441826A
公开(公告)日：1984-04-10
申请号：US430569
申请日：1982-09-30
申请人： Shigeru Morokawa , Keiichiro Koga
发明人： Shigeru Morokawa , Keiichiro Koga
IPC分类号： G04C10/04 , G04G3/02 , G04G9/00 , G05F3/24 , H03B5/32 , G04B1/00 , G05F1/56 , H03K3/01
CPC分类号： G04C10/04 , G04G3/022 , G04G9/0047 , G05F3/245 , G05F3/247 , Y10S331/03
摘要： An electronic timepiece having voltage regulation, temperature detection and battery voltage detection means provided on the same integrated circuit as is used for timekeeping circuitry, and having external terminals for stepwise weighted adjustment of timekeeping gain/loss.
摘要翻译：具有电压调节，温度检测和电池电压检测装置的电子钟表，设置在与计时电路相同的集成电路上，并具有用于逐步加权调整计时增益/损耗的外部端子。

20. 发明授权

US4441825A Low-power integrated circuit for an electronic timepiece 失效
标题翻译：用于电子表的低功率集成电路
公开(公告)号：US4441825A
公开(公告)日：1984-04-10
申请号：US931277
申请日：1978-08-04
申请人： Shigeru Morokawa
发明人： Shigeru Morokawa
IPC分类号： G04G3/00 , G04C3/14 , G04C10/00 , G04G3/02 , G04G5/02 , G04G19/00 , G04G19/02 , G04G99/00 , G04B1/00
CPC分类号： G04G99/00 , G04C3/14 , G04G19/00 , G04G3/022 , G04G5/02
摘要： An electronic timepiece comprising a threshold voltage based constant voltage regulator circuit, which provides the regulated voltage to a first part of the timepiece system including an oscillator and a divider. The signal from the first part is transferred to a second part of the timepiece which is provided with a voltage from a power supply source directly. The regulator circuit improves the voltage dependence of the timepiece system such as current consumption, frequency stability, etc.
摘要翻译：一种包括基于阈值电压的恒压调节器电路的电子钟表，其将调节电压提供给包括振荡器和分频器的钟表系统的第一部分。来自第一部分的信号被传送到从电源直接提供电压的钟表的第二部分。调节器电路提高了钟表系统的电压依赖性，如电流消耗，频率稳定性等。

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