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11. 发明专利

JPH0817948A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH0817948A
公开(公告)日：1996-01-19
申请号：JP15024194
申请日：1994-06-30
申请人： TOSHIBA CORP
发明人： SATO SHINJI , ARITOME SEIICHI , SHUDO SUSUMU , MARUYAMA TORU , WATABE HIROSHI , HEMINKU GERUTOYAN
IPC分类号： H01L21/8247 , H01L21/76 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PURPOSE:To provide a manufacturing method of an MOS transistor which has a gate insulating film of high breakdown voltage and can realize high level of integration and high reliability. CONSTITUTION:In the manufacturing method of an MOS transistor, a first layer polycrystalline silicon film 15 is formed on a silicon substrate 10 via a gate oxide film, and then selectively etched by using an island pattern as a mask, and a trench 11 for element isolation is formed by selectively etching the substrate 10. A CVD oxide film 12 is buried and formed in the trench 11, a second layer polycrystalline silicon film 20 is formed on the whole surface, and the second layer polycrystalline silicon film 20 and the first layer polycrystalline silicon film 15 are selectively etched by using a line type pattern formed on the first layer polycrystalline silicon film 15 as a mask.

12. 发明专利

JP2013236014A Multivalued non-volatile semiconductor memory 审中-公开
标题翻译：多变量非易失性半导体存储器
公开(公告)号：JP2013236014A
公开(公告)日：2013-11-21
申请号：JP2012108634
申请日：2012-05-10
申请人： Toshiba Corp , 株式会社東芝
发明人： KOYAMA YUKINORI , SHUDO SUSUMU
IPC分类号： H01L21/8246 , G11C11/15 , H01L27/105 , H01L29/82 , H01L43/08
CPC分类号： G11C11/16
摘要： PROBLEM TO BE SOLVED: To propose a new memory excellent in writing stability and reduction in bit cost, and using a multiferroic material.SOLUTION: A multivalued non-volatile semiconductor memory includes a memory cell M having a structure in which a first ferromagnetic layer FM1, a first multiferroic layer MF1, a second ferromagnetic layer FM2 and a second multiferroic layer MF2 are arranged in this order; and a control circuit 20 for controlling writing of 8-value data into the memory cell M. The first multiferroic layer MF1 stores 4 states according to 2 magnetization directions and 2 electric polarization directions. The second multiferroic layer MF2 stores 2 states according to 2 magnetization directions. The second ferromagnetic layer FM2 stores 2 states according to 2 magnetization directions depending on the two states of the second multiferroic layer MF2.
摘要翻译：要解决的问题：提出一种写入稳定性和降低成本的新型存储器，以及使用多铁性材料。解决方案：多值非易失性半导体存储器包括具有以下结构的存储单元M：第一铁磁层FM1 第一多铁层MF1，第二铁磁层FM2和第二多铁层MF2依次排列; 以及用于控制将8值数据写入存储单元M的控制电路20.第一多层层MF1根据2个磁化方向和2个电极化方向存储4个状态。第二多层层MF2根据2个磁化方向存储2个状态。第二铁磁层FM2根据第二多铁层MF2的两种状态，根据2个磁化方向存储2种状态。

13. 发明专利

JP2012129470A Semiconductor storage apparatus 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2012129470A
公开(公告)日：2012-07-05
申请号：JP2010281947
申请日：2010-12-17
申请人： Toshiba Corp , 株式会社東芝
发明人： SHUDO SUSUMU
IPC分类号： H01L27/105 , H01L21/8246 , H01L43/08
CPC分类号： H01L27/228
摘要： PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor storage apparatus which inhibits deterioration in a via contact between an upper electrode and a second bit line.SOLUTION: A semiconductor storage apparatus comprises a plurality of magnetic tunnel junction elements disposed on a semiconductor substrate and a plurality of selection transistors electrically connected to one ends of the plurality of magnetic tunnel junction elements, respectively. A first bit line is connected to one end of each magnetic tunnel junction element via one or a plurality of selection transistors. A plurality of upper electrodes are connected to other ends of the plurality of magnetic tunnel junction elements. A second bit line is connected to the other end of each magnetic tunnel junction element via the upper electrode. The upper electrodes stretch along the second bit line and are connected in common to the other end of each of the plurality of magnetic tunnel junction elements arranged in the stretching direction of the second bit line.
摘要翻译：要解决的问题：提供一种高可靠性的半导体存储装置，其抑制上部电极和第二位线之间的通孔接触的劣化。解决方案：一种半导体存储装置，包括设置在半导体衬底上的多个磁性隧道结元件和分别与多个磁性隧道结元件的一端电连接的多个选择晶体管。第一位线经由一个或多个选择晶体管连接到每个磁性隧道结元件的一端。多个上电极连接到多个磁隧道结元件的另一端。第二位线经由上电极连接到每个磁性隧道结元件的另一端。上部电极沿着第二位线延伸并且共同连接到沿第二位线的拉伸方向布置的多个磁性隧道结元件中的每一个的另一端。版权所有（C）2012，JPO＆INPIT

14. 发明专利

JP2010277653A Ferroelectric memory 审中-公开
标题翻译：电磁记忆
公开(公告)号：JP2010277653A
公开(公告)日：2010-12-09
申请号：JP2009130124
申请日：2009-05-29
申请人： Toshiba Corp , 株式会社東芝
发明人： KITAZAKI SOICHIRO , SHUDO SUSUMU
IPC分类号： G11C11/22 , H01L21/8246 , H01L27/10 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To provide a ferroelectric memory for effectively screening a failure caused by variation in threshold of a cell transistor.
SOLUTION: The ferroelectric memory includes: a memory cell array 111 having a plurality of memory cells in which ferroelectric capacitors and the cell transistors are connected in parallel, the memory cells being connected each other in series for each block; a plurality of word lines WL1-WL8; a plurality of bit lines BL1-BL4; a word line driver 201 which selects an operation voltage for memory cell, a ground voltage, or a third voltage having the voltage value different from the operation voltage and the ground voltage, to applies the selected voltage to the word lines; and a measurement circuit 202 connected to the bit lines to measure threshold voltages, output currents, or output voltages of the cell transistors and to output signals for showing measured results of the threshold voltages, output currents, or the output voltages.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供用于有效地屏蔽由单元晶体管的阈值变化引起的故障的铁电存储器。铁电存储器包括：具有多个存储单元的存储单元阵列111，其中强电介质电容器和单元晶体管并联连接，存储单元为每个块串联连接; 多个字线WL1〜WL8; 多个位线BL1〜BL4; 选择用于存储单元的操作电压，接地电压或具有与操作电压和接地电压不同的电压值的第三电压的字线驱动器201，以将所选择的电压施加到字线; 以及测量电路202，连接到位线以测量单元晶体管的阈值电压，输出电流或输出电压，并输出用于显示阈值电压，输出电流或输出电压的测量结果的信号。版权所有（C）2011，JPO＆INPIT

15. 发明专利

JP2010212426A Semiconductor memory device and method for manufacturing the same 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2010212426A
公开(公告)日：2010-09-24
申请号：JP2009056530
申请日：2009-03-10
申请人： Toshiba Corp , 株式会社東芝
发明人： SHUDO SUSUMU
IPC分类号： H01L21/8246 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which deterioration of ferroelectric capacitors due to hydrogen can be suppressed.
SOLUTION: The semiconductor memory device includes a first interlayer film which covers transistors, first plugs which are formed in the first interlayer film and are connected with one of a source and a drain of the transistors, the ferroelectric capacitors which are formed above the first plugs and the first interlayer film, a second plug which is formed in the first interlayer film under and between the adjacent ferroelectric capacitors and is connected with the other of the source and the drain of the transistors, a first insulating film which covers the side faces of the ferroelectric capacitors, a second insulating film which further covers the first insulating film on the side faces of the ferroelectric capacitors, a second interlayer film which covers the second insulating film, a third plug which passes through the second interlayer film between the adjacent ferroelectric capacitors and is connected with the second plug. The second insulating film is formed of a material which is harder to etch than the first insulating film.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决方案的问题：提供可抑制由于氢引起的铁电电容器劣化的半导体存储器件。解决方案：半导体存储器件包括覆盖晶体管的第一层间膜，形成在第一层间膜中并与晶体管的源极和漏极之一连接的第一插塞，形成在上面的铁电电容器第一插塞和第一夹层膜，第二插头，形成在相邻的强电介质电容器之下且位于相邻的强电介质电容器之间的第一层间膜中，并与晶体管的源极和漏极中的另一个连接，第一绝缘膜覆盖铁电电容器的侧面，进一步覆盖强电介质电容器的侧面上的第一绝缘膜的第二绝缘膜，覆盖第二绝缘膜的第二层间膜，在第二绝缘膜之间穿过第二中间膜的第三插塞相邻的铁电电容器并与第二插头连接。第二绝缘膜由比第一绝缘膜更难蚀刻的材料形成。版权所有（C）2010，JPO＆INPIT

16. 发明专利

JP2008059654A Ferroelectric semiconductor memory device 审中-公开
标题翻译：微电子半导体存储器件
公开(公告)号：JP2008059654A
公开(公告)日：2008-03-13
申请号：JP2006233273
申请日：2006-08-30
申请人： Toshiba Corp , 株式会社東芝
发明人： SHUDO SUSUMU
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： PROBLEM TO BE SOLVED: To achieve high-speed operation of a semiconductor memory device comprising a plurality of ferroelectric memory cells.
SOLUTION: A ferroelectric semiconductor memory device is provided with: a block with a plurality of serially connected ferroelectric memory cells constituted of a ferroelectric capacitor for holding charges and transistors connected in parallel to both ends of the ferroelectric capacitor; a word line connected to each transistor; a selection transistor connected to one end of the block; a bit line connected to the selection transistor; a plate line connected to the other end of the block; and a control circuit for changing potentials of the word line and the bit line. By changing the potential of the word line while the potential of the plate line is fixed, information is deleted from or written in the plurality of ferroelectric memory cells.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了实现包括多个铁电存储器单元的半导体存储器件的高速操作。解决方案：铁电半导体存储器件设置有：具有多个串联连接的铁电存储单元的块，该铁电体存储单元由用于保持电荷的铁电电容器和与所述铁电电容器的两端并联连接的晶体管构成; 连接到每个晶体管的字线; 连接到所述块的一端的选择晶体管; 连接到选择晶体管的位线; 连接到块的另一端的板线; 以及用于改变字线和位线的电位的控制电路。通过在板线的电位固定的同时改变字线的电位，从多个铁电存储单元中删除或写入信息。版权所有（C）2008，JPO＆INPIT

17. 发明专利

JP2007242120A Ferroelectric substance storage device 有权
标题翻译：微电子物质储存装置
公开(公告)号：JP2007242120A
公开(公告)日：2007-09-20
申请号：JP2006061445
申请日：2006-03-07
申请人： Toshiba Corp , 株式会社東芝
发明人： SHUDO SUSUMU
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C7/04 , G11C7/22
摘要： PROBLEM TO BE SOLVED: To provide a ferroelectric substance storage device including a read-out method highly reliable to data holding.
SOLUTION: The ferroelectric substance storage device is equipped with: a memory cell 12 with ferroelectric substance capacitors; a read-out circuit 14 configured so as to read out data from the memory cell 12; a temperature detection circuit 18 configured so as to detect an ambient temperature of the memory cell 12; and a read-out control circuit 16 configured so as to inhibit the read-out circuit 14 from reading the data when the circuit 16 is supplied with a temperature detection signal corresponding to the temperature detected by the temperature detection circuit 18 and receives an external read-out signal instructing to read out the data from the memory cell 12, and the temperature detected by the temperature detection circuit 18 is higher than a preset temperature.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种包括对数据保持高度可靠的读出方法的铁电物质存储装置。铁电体物质储存装置配备有：具有铁电体电容器的存储单元12; 被配置为从存储器单元12读出数据的读出电路14; 配置为检测存储单元12的环境温度的温度检测电路18; 以及读出控制电路16，被配置为当电路16被提供与温度检测电路18检测到的温度相对应的温度检测信号时，禁止读出电路14读取数据，并接收外部读取 -out信号指示从存储单元12读出数据，并且由温度检测电路18检测的温度高于预设温度。版权所有（C）2007，JPO＆INPIT

18. 发明专利

JP2006269764A Ferroelectric storage device and manufacturing method therefor 审中-公开
标题翻译：电力储存装置及其制造方法
公开(公告)号：JP2006269764A
公开(公告)日：2006-10-05
申请号：JP2005085988
申请日：2005-03-24
申请人： Toshiba Corp , 株式会社東芝
发明人： SHUDO SUSUMU
IPC分类号： H01L27/105 , H01L21/8246
CPC分类号： H01L27/115 , H01L27/11521 , H01L29/513 , H01L29/7881
摘要： PROBLEM TO BE SOLVED: To solve the problems that an excessive space is required for preventing the deviation of wiring connecting the plug of a transistor on a substrate and an upper ferroelectric capacitor electrode, and the micronization of a cell size is limited.
SOLUTION: By providing the ferroelectric capacitor of a ferroelectric memory and a transistor 45 in a self-aligning manner, the electrode 90 of the capacitor and the diffusion layer 40 of the transistor 45 are connected by the same wiring 90. Thus, the problem of the deviation is evaded and the micronization of the cell size is achieved.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：为了解决为了防止在基板上和上部铁电电容器电极上连接晶体管的插线的布线的偏差而需要过多的空间的问题，并且单元尺寸的微细化受到限制。解决方案：通过以自对准方式提供铁电存储器和晶体管45的铁电电容器，电容器的电极90和晶体管45的扩散层40通过相同的布线90连接。因此，避免了偏差的问题，并实现了电池尺寸的微细化。版权所有（C）2007，JPO＆INPIT

19. 发明专利

JP2005166836A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2005166836A
公开(公告)日：2005-06-23
申请号：JP2003402087
申请日：2003-12-01
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIMOJO YOSHIRO , SHUDO SUSUMU
IPC分类号： H01L27/105 , H01G4/005 , H01G4/20 , H01L21/02 , H01L21/8242 , H01L21/8246 , H01L27/108 , H01L27/115
CPC分类号： H01L27/11507 , H01L27/1085 , H01L27/10852 , H01L27/11502 , H01L28/55 , H01L28/57 , H01L28/65
摘要： PROBLEM TO BE SOLVED: To prevent static electricity energy loss due to the leakage of line of electric force to the external side of electrode plate.
SOLUTION: Each capacitor is formed, for example, of a lower electrode BE, an dielectric material D provided between the electrodes, and an upper electrode TE. Just under the lower electrode BE, a silicon oxide (SiO
2 ), for example, is disposed and a silicon oxide is also disposed, for example, just over the upper electrode TE. In the space between a couple of capacitors, an insulating layer Low-k having a lower specific dielectric constant is disposed. The insulating layer Low-k is formed of a material having the specific dielectric constant as lower as possible in order to lower parasitic capacitance of wiring. On the side wall of the electrode-to-electrode dielectric material D, a high dielectric material High-k is disposed to control the swell of the line of electric force. The specific dielectric constant of the high dielectric material High-k is larger than at least that of a insulating layer Low-k.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了防止由于电力线泄漏到电极板的外侧而导致的静电能量损失。解决方案：每个电容器例如由下电极BE，设置在电极之间的电介质材料D和上电极TE形成。在下电极BE的正下方，设置例如氧化硅（SiO 2 ），并且例如刚好在上电极TE上方设置氧化硅。在一对电容器之间的空间中，设置具有较低比介电常数的绝缘层Low-k。绝缘层Low-k由比介电常数尽可能低的材料形成，以便降低布线的寄生电容。在电极对电极介电材料D的侧壁上设置有高介电材料High-k以控制电力线的膨胀。高介电材料的比介电常数高k至少大于绝缘层Low-k的介电常数。版权所有（C）2005，JPO＆NCIPI

20. 发明专利

JP2005141835A Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路设备
公开(公告)号：JP2005141835A
公开(公告)日：2005-06-02
申请号：JP2003377155
申请日：2003-11-06
申请人： Toshiba Corp , 株式会社東芝
发明人： SHUDO SUSUMU
IPC分类号： G11C11/22 , H01L21/8246 , H01L27/105
CPC分类号： G11C11/22
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device in which signal margin can be improved.
SOLUTION: The semiconductor integrated circuit device is provided with a plurality of memory cells 10 divided into a plurality of groups, and a reference potential selecting circuit 14 setting reference potentials Vref1, Vref2 being different for each group.
COPYRIGHT: (C)2005,JPO&NCIPI

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