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11. 发明授权

US07289126B1 Gamma-corrected texel storage in a graphics memory 有权
标题翻译： Gamma校正的纹理存储器存储在图形存储器中
公开(公告)号：US07289126B1
公开(公告)日：2007-10-30
申请号：US10445144
申请日：2003-05-23
申请人： Alexander L. Minkin , Harold Robert Feldman Zable , Matthew N. Papakipos
发明人： Alexander L. Minkin , Harold Robert Feldman Zable , Matthew N. Papakipos
IPC分类号： G09G5/00 , G06T15/50 , G06T15/00
CPC分类号： G09G5/363 , G06T11/001 , G06T15/005 , G09G2320/0276
摘要： Methods, circuits, and apparatus for handling gamma-corrected texels stored in a graphics memory. On-the-fly gamma-to-linear and linear-to-gamma conversions are performed such that gamma-corrected texels are provided to circuits that are able to process them, while linear valued texels are supplied where needed. In various embodiments, these conversions are done by lookup tables, software instructions, or dedicated hardware. Gamma-corrected texels may be tracked by a shader program, pipeline states, or driver instructions, and may be identified by header or flag information, or by part of a texture descriptor.
摘要翻译：用于处理存储在图形存储器中的伽马校正的纹素的方法，电路和装置。执行即时伽马对线性和线性到伽马转换，使得伽马校正的纹素提供给能够处理它们的电路，而在需要时提供线性值纹理。在各种实施例中，这些转换通过查找表，软件指令或专用硬件完成。伽马校正的纹素可以由着色器程序，流水线状态或驱动器指令来跟踪，并且可以由标题或标志信息或纹理描述符的一部分来标识。

12. 发明申请

US20110292065A1 RECONFIGURABLE DUAL TEXTURE PIPELINE WITH SHARED TEXTURE CACHE 有权
标题翻译：具有共享纹理高速缓存的可重构双纹道管道
公开(公告)号：US20110292065A1
公开(公告)日：2011-12-01
申请号：US13209444
申请日：2011-08-15
申请人： Alexander L. Minkin
发明人： Alexander L. Minkin
IPC分类号： G09G5/00
CPC分类号： G06T15/04 , G06T2200/28 , G06T2210/36
摘要： Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in an efficient manner. One such texture circuit can provide a configurable number of texel quads for a configurable number of pixels. For bilinear filtering, texels for a comparatively greater number of pixels can be retrieved. For trilinear filtering, texels in a first LOD are retrieved for a number of pixels during a first clock cycle, during a second clock cycle, texels in a second LOD are retrieved. When aniso filtering is needed, a greater number of texels can be retrieved for a comparatively lower number of pixels.
摘要翻译：提供纹理缓存和相关电路的电路，方法和装置，以有效的方式存储和检索纹素。一个这样的纹理电路可以为可配置数量的像素提供可配置数量的纹素四边形。对于双线性滤波，可以检索相对较大数量的像素的纹素。对于三线性滤波，在第一时钟周期期间，在第一时钟周期期间，针对多个像素检索第一LOD中的纹理，在第二个LOD中的纹理片段被检索。当需要进行aniso过滤时，可以为相对较少数量的像素检索更多数量的纹素。

13. 发明授权

US07999821B1 Reconfigurable dual texture pipeline with shared texture cache 有权
标题翻译：可重构双纹理管道与共享纹理缓存
公开(公告)号：US07999821B1
公开(公告)日：2011-08-16
申请号：US11960645
申请日：2007-12-19
申请人： Alexander L. Minkin
发明人： Alexander L. Minkin
IPC分类号： G09G5/00
CPC分类号： G06T15/04 , G06T2200/28 , G06T2210/36
摘要： Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in an efficient manner. One such texture circuit can provide a configurable number of texel quads for a configurable number of pixels. For bilinear filtering, texels for a comparatively greater number of pixels can be retrieved. For trilinear filtering, texels in a first LOD are retrieved for a number of pixels during a first clock cycle, during a second clock cycle, texels in a second LOD are retrieved. When aniso filtering is needed, a greater number of texels can be retrieved for a comparatively lower number of pixels.
摘要翻译：提供纹理缓存和相关电路的电路，方法和装置，以有效的方式存储和检索纹素。一个这样的纹理电路可以为可配置数量的像素提供可配置数量的纹素四边形。对于双线性滤波，可以检索相对较大数量的像素的纹素。对于三线性滤波，在第一时钟周期期间，在第一时钟周期期间，针对多个像素检索第一LOD中的纹理，在第二个LOD中的纹理片段被检索。当需要进行aniso过滤时，可以为相对较少数量的像素检索更多数量的纹素。

14. 发明授权

US08217954B2 Reconfigurable dual texture pipeline with shared texture cache 有权
标题翻译：可重构双纹理管道与共享纹理缓存
公开(公告)号：US08217954B2
公开(公告)日：2012-07-10
申请号：US13209444
申请日：2011-08-15
申请人： Alexander L. Minkin
发明人： Alexander L. Minkin
IPC分类号： G09G5/00
CPC分类号： G06T15/04 , G06T2200/28 , G06T2210/36
摘要： Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in an efficient manner. One such texture circuit can provide a configurable number of texel quads for a configurable number of pixels. For bilinear filtering, texels for a comparatively greater number of pixels can be retrieved. For trilinear filtering, texels in a first LOD are retrieved for a number of pixels during a first clock cycle, during a second clock cycle, texels in a second LOD are retrieved. When aniso filtering is needed, a greater number of texels can be retrieved for a comparatively lower number of pixels.
摘要翻译：提供纹理缓存和相关电路的电路，方法和装置，以有效的方式存储和检索纹素。一个这样的纹理电路可以为可配置数量的像素提供可配置数量的纹素四边形。对于双线性滤波，可以检索相对较大数量的像素的纹素。对于三线性滤波，在第一时钟周期期间，在第一时钟周期期间，针对多个像素检索第一LOD中的纹理，在第二个LOD中的纹理片段被检索。当需要进行aniso过滤时，可以为相对较少数量的像素检索更多数量的纹素。

15. 发明授权

US07948498B1 Efficient texture state cache 有权
标题翻译：高效的纹理状态缓存
公开(公告)号：US07948498B1
公开(公告)日：2011-05-24
申请号：US11549566
申请日：2006-10-13
申请人： Alexander L. Minkin
发明人： Alexander L. Minkin
IPC分类号： G06T11/40
CPC分类号： G06T11/40 , G06T1/60 , G06T15/04
摘要： Circuits, methods, and apparatus that store a large number of texture states in an efficient manner. A level-one texture cache includes cache lines that are distributed throughout a texture pipeline, where each cache line stores a texture state. The cache lines can be updated by retrieving data from a second-level texture state cache, which in turn is updated from a frame buffer or graphics memory. The second-level texture state cache can prefetch texture states using a list of textures that are needed for a shader program or program portion.
摘要翻译：以有效的方式存储大量纹理状态的电路，方法和装置。一级纹理缓存包括分布在纹理流水线中的高速缓存行，其中每个高速缓存行存储纹理状态。可以通过从第二级纹理状态高速缓存中检索数据来更新高速缓存行，该缓存行又从帧缓冲器或图形存储器更新。第二级纹理状态缓存可以使用着色器程序或程序部分所需的纹理列表来预取纹理状态。

16. 发明授权

US07948495B1 Linking texture headers and texture samplers 有权
标题翻译：链接纹理标题和纹理采样器
公开(公告)号：US07948495B1
公开(公告)日：2011-05-24
申请号：US11345740
申请日：2006-02-02
申请人： Bryon S. Nordquist , Alexander L. Minkin
发明人： Bryon S. Nordquist , Alexander L. Minkin
IPC分类号： G06T1/00
CPC分类号： G06T1/00
摘要： Systems and methods used for binding texture state stored in independent structures may be used by more than one graphics applications programming interface (API). A texture header portion of the texture state defines texture data characteristics and is stored in a first structure. A texture sampler portion of the texture state specifies texture processing attributes and is stored in a second structure. A single unified structure is emulated for use by APIs that store the texture state in a single structure. Therefore, a graphics processor may support more than one graphics API for processing texture data.
摘要翻译：用于绑定存储在独立结构中的纹理状态的系统和方法可能由多个图形应用编程接口（API）使用。纹理状态的纹理标题部分定义纹理数据特征，并存储在第一结构中。纹理状态的纹理采样器部分指定纹理处理属性并存储在第二结构中。单一的统一结构被仿真以供在单一结构中存储纹理状态的API使用。因此，图形处理器可以支持多于一个图形API来处理纹理数据。

17. 发明授权

US07924290B2 Method and system for processing texture samples with programmable offset positions 有权
标题翻译：用可编程偏移位置处理纹理样本的方法和系统
公开(公告)号：US07924290B2
公开(公告)日：2011-04-12
申请号：US11755531
申请日：2007-05-30
申请人： Anders M. Kugler , Alexander L. Minkin , William P. Newhall, Jr. , Christopher J. Migdal , Pemith R. Fernando , Lup-Yen Peter Young , Mehmet Cem Cebenoyan , Yury Y. Uralsky
发明人： Anders M. Kugler , Alexander L. Minkin , William P. Newhall, Jr. , Christopher J. Migdal , Pemith R. Fernando , Lup-Yen Peter Young , Mehmet Cem Cebenoyan , Yury Y. Uralsky
IPC分类号： G06T17/00 , G06T11/40 , G09G5/00 , G09G5/02 , G06K9/40 , G06K9/36 , G06K9/32
CPC分类号： G06T15/04
摘要： A method and system for performing a texture operation with user-specified offset positions are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of deriving a first destined texel position based on an original sample position associated with a pixel projected in a texture map and a first offset position specified by a user and fetching texel attributes at the first destined texel position for the texture operation.
摘要翻译：公开了一种用于执行用户指定的偏移位置的纹理操作的方法和系统。具体地，本发明的一个实施例提出了一种方法，其包括以下步骤：基于与投影在纹理图中的像素和由用户指定的第一偏移位置相关联的原始样本位置导出第一目标纹理位置，并且获取纹理操作的第一个目标纹素像素位置的纹素属性。

18. 发明申请

US20100118043A1 RECONFIGURABLE HIGH-PERFORMANCE TEXTURE PIPELINE WITH ADVANCED FILTERING 有权
标题翻译：可重复使用的高性能纹路管道，具有先进的过滤功能
公开(公告)号：US20100118043A1
公开(公告)日：2010-05-13
申请号：US12689939
申请日：2010-01-19
申请人： Alexander L. Minkin , Joel J. McCormack , Paul S. Heckbert , Michael J.M. Toksvig , Luke Y. Chang , Karim Abdalla , Bo Hong , John W. Berendsen , Walter Donavan , Emmett M. Kilgariff
发明人： Alexander L. Minkin , Joel J. McCormack , Paul S. Heckbert , Michael J.M. Toksvig , Luke Y. Chang , Karim Abdalla , Bo Hong , John W. Berendsen , Walter Donavan , Emmett M. Kilgariff
IPC分类号： G09G5/00
CPC分类号： G06T1/60 , G06F3/14 , G06T15/04 , G06T2200/28 , G09G5/026 , G09G5/22 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2360/06 , G09G2360/121 , G09G2360/18
摘要： Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.
摘要翻译：提供纹理缓存和相关电路的电路，方法和装置，以快速和有效的方式存储和检索纹素。一个这样的纹理电路为一组像素中的每个像素提供了更多数量的iler骨，特别是当需要三线性或茴香过滤时。对于三线性滤波，在一个时钟周期内针对多个像素检索第一和第二细节级别的纹素。当执行了茴香过滤时，可以在一个时钟周期内为多个像素中的每一个检索多个b骨。

19. 发明授权

US07659893B1 Method and apparatus to ensure consistency of depth values computed in different sections of a graphics processor 失效
标题翻译：确保在图形处理器的不同部分计算的深度值的一致性的方法和装置
公开(公告)号：US07659893B1
公开(公告)日：2010-02-09
申请号：US11538002
申请日：2006-10-02
申请人： Stuart F. Oberman , Steven E. Molnar , Alexander L. Minkin , Peter B. Holmqvist
发明人： Stuart F. Oberman , Steven E. Molnar , Alexander L. Minkin , Peter B. Holmqvist
IPC分类号： G06T15/40
CPC分类号： G06T15/405 , G06T15/005 , G06T2200/28
摘要： At least two different processing sections in a graphics processors compute Z coordinates for a sample location from a compressed Z representation. The processors are designed to ensure that Z coordinates computed in any unit in the processor are identical. In one embodiment, the respective arithmetic circuits included in each processing section that computes Z coordinates are “bit-identical,” meaning that, for any input planar Z representation and coordinates, the output Z coordinates produced by the circuits are identical to each other.
摘要翻译：图形处理器中的至少两个不同的处理部分从压缩的Z表示中计算样本位置的Z坐标。处理器被设计为确保在处理器中的任何单元中计算的Z坐标是相同的。在一个实施例中，计算Z坐标的每个处理部分中包括的相应运算电路是“位相同”，这意味着对于任何输入的平面Z表示和坐标，由电路产生的输出Z坐标彼此相同。

20. 发明授权

US09013498B1 Determining a working set of texture maps 有权
标题翻译：确定纹理贴图的工作集
公开(公告)号：US09013498B1
公开(公告)日：2015-04-21
申请号：US12340499
申请日：2008-12-19
申请人： John S. Montrym , Andrew J. Tao , Henry P. Moreton , Emmett M. Kilgariff , Cass W. Everitt , Alexander L. Minkin , Eric Anderson , Yan Yan Tang , Jerome F. Duluk, Jr.
发明人： John S. Montrym , Andrew J. Tao , Henry P. Moreton , Emmett M. Kilgariff , Cass W. Everitt , Alexander L. Minkin , Eric Anderson , Yan Yan Tang , Jerome F. Duluk, Jr.
IPC分类号： G09G5/00 , G09G5/37
CPC分类号： G09G5/37 , G06T15/005 , G06T15/04 , G06T2210/36
摘要： A system and method for tracking and reporting texture map levels of detail that are computed during graphics processing allows for efficient management of texture map storage. Minimum and/or maximum pre-clamped texture map levels of detail values are tracked by a graphics processor and an array stored in memory is updated to report the minimum and/or maximum values for use by an application program. The minimum and/or maximum values may be used to determine the active set of texture map levels of detail that is loaded into graphics memory.
摘要翻译：用于跟踪和报告在图形处理期间计算的细节纹理图层级的系统和方法允许纹理图存储的有效管理。图形处理器跟踪细节值的最小和/或最大预夹紧纹理映射级别，更新存储在存储器中的阵列以报告应用程序使用的最小值和/或最大值。最小值和/或最大值可用于确定加载到图形存储器中的细节的纹理映射级别的活动集合。

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