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11. 发明授权

US08912626B2 eFuse and method of fabrication 有权
标题翻译： eFuse和制造方法
公开(公告)号：US08912626B2
公开(公告)日：2014-12-16
申请号：US13013055
申请日：2011-01-25
申请人： Edward P. Maciejewski , Dustin Kenneth Slisher , Stefan Zollner
发明人： Edward P. Maciejewski , Dustin Kenneth Slisher , Stefan Zollner
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L21/3065 , H01L21/31116 , H01L21/32053 , H01L2924/0002 , H01L2924/00
摘要： An improved eFuse and method of fabrication is disclosed. A cavity is formed in a substrate, which results in a polysilicon line having an increased depth in the area of the fuse, while having a reduced depth in areas outside of the fuse. The increased depth reduces the chance of the polysilicon line entering the fully silicided state. The cavity may be formed with a wet or dry etch.
摘要翻译：公开了改进的eFuse和制造方法。在衬底中形成腔，这导致多晶硅线在熔丝的面积上具有增加的深度，同时在熔丝外部的区域具有减小的深度。增加的深度降低了多晶硅线路进入完全硅化状态的机会。空腔可以用湿或干蚀刻形成。

12. 发明授权

US08398889B2 Electroluminescent adhesive masses 有权
标题翻译：电致发光胶
公开(公告)号：US08398889B2
公开(公告)日：2013-03-19
申请号：US12293482
申请日：2007-03-21
申请人： Marco Kupsky , Stefan Zollner
发明人： Marco Kupsky , Stefan Zollner
IPC分类号： C09J7/02 , C09J11/02 , C09J9/00
CPC分类号： C09J11/02 , C09J7/381 , C09J9/00 , C09J133/02 , C09J183/04 , C09J2205/102 , C09J2433/00 , C09J2483/00
摘要： The invention relates to adhesive masses containing at least one electroluminescent additive, single and double-sided adhesive strips which are provided with adhesive masses of said type, and to the use of said adhesive masses for sticking together electronic components.
摘要翻译：本发明涉及包含至少一种电致发光添加剂，单面和双面粘合带的粘合剂块，其具有所述类型的粘合剂块，以及使用所述粘合剂块将电子部件粘合在一起。

13. 发明申请

US20120028430A1 METHOD AND STRUCTURE TO IMPROVE FORMATION OF SILICIDE 审中-公开
标题翻译：改善硅酸盐形成的方法与结构
公开(公告)号：US20120028430A1
公开(公告)日：2012-02-02
申请号：US12843998
申请日：2010-07-27
申请人： Ming Cai , Ahmet S. Ozcan , Stefan Zollner
发明人： Ming Cai , Ahmet S. Ozcan , Stefan Zollner
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L29/6656 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： A method begins with a structure having: a gate insulator on a silicon substrate between a gate conductor and a channel region within the substrate; insulating sidewall spacers on sidewalls of the gate conductor; and source and drain regions within the substrate adjacent the channel region. To silicide the gate and source and drain regions, the method deposits a metallic material over the substrate, the gate conductor, and the sidewalls, and performs a first heating process to change the metallic material into a metal-rich silicide at locations where the metallic material contacts silicon. The method removes the sidewall spacers, and performs a second heating process to change the metal-rich silicide into silicide having a lower metallic concentration than the metal-rich silicide. The silicide thus formed avoids being damaged by the spacer removal process.
摘要翻译：一种方法开始于具有以下结构：在硅衬底之间的栅极导体和衬底内的沟道区之间的栅极绝缘体; 在栅极导体的侧壁上的绝缘侧壁间隔物; 衬底内的源极和漏极区域相邻于沟道区域。为了硅化栅极和源极和漏极区域，该方法将金属材料沉积在衬底，栅极导体和侧壁上，并且执行第一加热过程，以将金属材料改变为富金属硅化物，其中金属材料接触硅。该方法除去侧壁间隔物，并且进行第二加热处理以将富金属硅化物改变为具有比富金属硅化物更低的金属浓度的硅化物。这样形成的硅化物避免了被间隔物去除过程损坏。

14. 发明申请

US20110241213A1 Silicide Contact Formation 失效
标题翻译：硅胶接触层
公开(公告)号：US20110241213A1
公开(公告)日：2011-10-06
申请号：US12754912
申请日：2010-04-06
申请人： Andrew J. Kellock , Christian Lavoie , Ahmet Ozcan , Stephen Rossnagel , Bin Yang , Zhen Zhang , Yu Zhu , Stefan Zollner
发明人： Andrew J. Kellock , Christian Lavoie , Ahmet Ozcan , Stephen Rossnagel , Bin Yang , Zhen Zhang , Yu Zhu , Stefan Zollner
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L21/28518 , H01L29/66795 , H01L29/785 , H01L2029/7858 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a silicide contact includes depositing a metal layer on silicon such that the metal layer intermixes with the silicon to form an intermixed region on the silicon; removing an unintermixed portion of the metal layer from the intermixed region; and annealing the intermixed region to form a silicide contact on the silicon. A semiconductor device comprising a silicide contact located over a silicon layer of the semiconductor device, the silicide contact comprising nickel (Ni) and silicon (Si) and having Ni amount equivalent to a thickness of about 21 angstroms or less.
摘要翻译：形成硅化物接触的方法包括在硅上沉积金属层，使得金属层与硅混合以在硅上形成混合区; 从所述混合区域去除所述金属层的未混合部分; 并且对所述混合区进行退火以在所述硅上形成硅化物接触。一种半导体器件，包括位于所述半导体器件的硅层上方的硅化物触点，所述硅化物触点包括镍（Ni）和硅（Si），并且具有相当于约21埃或更小的厚度的Ni量。

15. 发明授权

US08404589B2 Silicide contact formation 失效
标题翻译：硅化物接触形成
公开(公告)号：US08404589B2
公开(公告)日：2013-03-26
申请号：US12754912
申请日：2010-04-06
申请人： Andrew J. Kellock , Christian Lavoie , Ahmet Ozcan , Stephen Rossnagel , Bin Yang , Zhen Zhang , Yu Zhu , Stefan Zollner
发明人： Andrew J. Kellock , Christian Lavoie , Ahmet Ozcan , Stephen Rossnagel , Bin Yang , Zhen Zhang , Yu Zhu , Stefan Zollner
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L29/66795 , H01L29/785 , H01L2029/7858 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a silicide contact includes depositing a metal layer on silicon such that the metal layer intermixes with the silicon to form an intermixed region on the silicon; removing an unintermixed portion of the metal layer from the intermixed region; and annealing the intermixed region to form a silicide contact on the silicon. A semiconductor device comprising a silicide contact located over a silicon layer of the semiconductor device, the silicide contact comprising nickel (Ni) and silicon (Si) and having Ni amount equivalent to a thickness of about 21 angstroms or less.
摘要翻译：形成硅化物接触的方法包括在硅上沉积金属层，使得金属层与硅混合以在硅上形成混合区; 从所述混合区域去除所述金属层的未混合部分; 并且对所述混合区进行退火以在所述硅上形成硅化物接触。一种半导体器件，包括位于所述半导体器件的硅层上方的硅化物触点，所述硅化物触点包含镍（Ni）和硅（Si），并且具有相当于约21埃或更小的厚度的Ni量。

16. 发明申请

US20120187529A1 eFUSE AND METHOD OF FABRICATION 有权
标题翻译： eFUSE和制造方法
公开(公告)号：US20120187529A1
公开(公告)日：2012-07-26
申请号：US13013055
申请日：2011-01-25
申请人： Edward P. Maciejewski , Dustin Kenneth Slisher , Stefan Zollner
发明人： Edward P. Maciejewski , Dustin Kenneth Slisher , Stefan Zollner
IPC分类号： H01L23/525 , H01L21/02
CPC分类号： H01L23/5256 , H01L21/3065 , H01L21/31116 , H01L21/32053 , H01L2924/0002 , H01L2924/00
摘要： An improved eFuse and method of fabrication is disclosed. A cavity is formed in a substrate, which results in a polysilicon line having an increased depth in the area of the fuse, while having a reduced depth in areas outside of the fuse. The increased depth reduces the chance of the polysilicon line entering the fully silicided state. The cavity may be formed with a wet or dry etch.
摘要翻译：公开了改进的eFuse和制造方法。在衬底中形成腔，这导致多晶硅线在熔丝的面积上具有增加的深度，同时在熔丝外部的区域具有减小的深度。增加的深度降低了多晶硅线路进入完全硅化状态的机会。空腔可以用湿或干蚀刻形成。

17. 发明申请

US20090042373A1 PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A DOPED SEMICONDUCTOR LAYER 有权
标题翻译：形成包含掺杂半导体层的电子器件的工艺
公开(公告)号：US20090042373A1
公开(公告)日：2009-02-12
申请号：US11835643
申请日：2007-08-08
申请人： Stefan Zollner , Bich-Yen Nguyen
发明人： Stefan Zollner , Bich-Yen Nguyen
IPC分类号： H01L21/20 , H01L21/02
CPC分类号： H01L21/28035 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/2807 , H01L29/4916 , H01L29/66636 , H01L29/7833
摘要： A process can include forming a doped semiconductor layer over a substrate. The process can also include performing an action that reduces a dopant content along an exposed surface of a workpiece that includes the substrate and the doped semiconductor layer. The action is performed after forming the doped semiconductor layer and before the doped semiconductor layer is exposed to a room ambient. In particular embodiments, the doped semiconductor layer includes a semiconductor material that includes a combination of at least two elements selected from the group consisting of C, Si, and Ge, and the doped semiconductor layer also includes a dopant, such as phosphorus, arsenic, boron, or the like. The action can include forming an encapsulating layer, exposing the doped semiconductor layer to radiation, annealing the doped semiconductor layer, or any combination thereof.
摘要翻译：工艺可以包括在衬底上形成掺杂半导体层。该方法还可以包括执行减少沿着包括衬底和掺杂半导体层的工件的暴露表面的掺杂剂含量的动作。在形成掺杂半导体层之后并且在掺杂半导体层暴露于室内环境之前执行该动作。在特定实施例中，掺杂半导体层包括半导体材料，其包括选自由C，Si和Ge组成的组中的至少两种元素的组合，并且掺杂半导体层还包括掺杂剂，例如磷，砷，硼等。该作用可以包括形成封装层，将掺杂半导体层暴露于辐射，退火掺杂半导体层，或其任何组合。

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