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11. 发明授权

US06657422B2 Current mirror circuit 有权
公开(公告)号：US06657422B2
公开(公告)日：2003-12-02
申请号：US10033877
申请日：2001-12-27
申请人： Patrick Heyne , Thilo Marx , Thomas Hein , Torsten Partsch
发明人： Patrick Heyne , Thilo Marx , Thomas Hein , Torsten Partsch
IPC分类号： G05F320
CPC分类号： G05F3/262
摘要： A current mirror circuit has an input path, which has a current source and, connected in series therewith, a first transistor circuit with at least two transistors, wherein one of the transistors can be connected in parallel with the other of the transistors. In an output path, which has a second transistor circuit with at least two transistors, one of the transistors can be connected in parallel with the other of the transistors. The control terminals of the transistors of the first and second transistor circuits can be connected to the input path. As a result, the current mirror circuit can be changed over between two operating modes with a different current requirement with comparatively short changeover times.

12. 发明授权

US06928025B1 Synchronous integrated memory 失效
标题翻译：同步集成存储器
公开(公告)号：US06928025B1
公开(公告)日：2005-08-09
申请号：US09621905
申请日：2000-07-24
申请人： Thomas Hein , Thilo Marx , Patrick Heyne , Torsten Partsch
发明人： Thomas Hein , Thilo Marx , Patrick Heyne , Torsten Partsch
IPC分类号： G11C7/10 , G11C7/22 , G11C11/4076 , G11C8/00
CPC分类号： G11C7/222 , G11C7/1072 , G11C7/22 , G11C11/4076
摘要： An output circuit (OUT) can be activated via an activation input (AKT), in the activated state starts an output process for data (D) to be read out, in synchronism with the first internal clock (CLKI1), and outputs the data (D) with a specific phase shift (ΔTOUT) with respect to the first internal clock (CLKI1), in synchronism with the external clock (CLKE), at a data connection (P). A counting unit (CT) starts a counting process for recording the number of successively following first levels of the first internal clock (CLKI1) as soon as a second internal clock (CLKI2), which is synchronized to the external clock (CLKE), for the first time assumes a first level while an output control signal (PAR) is at first level. It activates the output circuit (OUT) as soon as the number of successively following first levels of the first internal clock (CLKI1) has reached a predetermined value.
摘要翻译：可以通过激活输入（AKT）激活输出电路（OUT），在激活状态下，与第一内部时钟（CLKI 1）同步地开始读出数据（D）的输出处理，并输出在数据连接（P）下与外部时钟（CLKE）同步地具有相对于第一内部时钟（CLKI 1）的特定相移（DeltaTOUT）的数据（D）。一旦与外部时钟（CLKE）同步的第二内部时钟（CLKI 2），计数单元（CT）开始计数，用于记录连续追随的第一内部时钟（CLKI 1）的第一电平的数量，，当输出控制信号（PAR）处于第一电平时，第一次采用第一电平。一旦第一内部时钟（CLKI 1）的连续跟随的第一电平的数量达到预定值，它就激活输出电路（OUT）。

13. 发明授权

US06784650B2 Circuit configuration for generating a controllable output voltage 有权
标题翻译：用于产生可控输出电压的电路配置
公开(公告)号：US06784650B2
公开(公告)日：2004-08-31
申请号：US10438362
申请日：2003-05-14
申请人： Thomas Hein , Patrick Heyne , Thilo Marx , Torsten Partsch
发明人： Thomas Hein , Patrick Heyne , Thilo Marx , Torsten Partsch
IPC分类号： G05F140
CPC分类号： G05F1/465
摘要： A switching network with trimmable resistors lies in a control loop of a voltage generator that can be switched off from the supply voltage by a logic device. The logic device and also the switching network are driven by the same signals. The circuit configuration can be used for trimming or switching off the output voltage generated by the voltage generator during the functional test. As many settings as possible for the output voltage can be tested by a small number of control signals.
摘要翻译：具有可调电阻的开关网络位于电压发生器的控制回路中，该控制回路可通过逻辑器件从电源电压切断。逻辑器件以及开关网络由相同的信号驱动。电路配置可用于在功能测试期间修整或关闭由电压发生器产生的输出电压。输出电压尽可能多的设置可以通过少量控制信号进行测试。

14. 发明授权

US06366527B2 Circuit configuration for generating an output clock signal with optimized signal generation time 有权
标题翻译：用于产生具有优化的信号产生时间的输出时钟信号的电路配置
公开(公告)号：US06366527B2
公开(公告)日：2002-04-02
申请号：US09773220
申请日：2001-01-31
申请人： Thomas Hein , Thilo Marx , Patrick Heyne , Torsten Partsch
发明人： Thomas Hein , Thilo Marx , Patrick Heyne , Torsten Partsch
IPC分类号： G11C800
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/22
摘要： DDR SDRAM memory chips require a highly precise output clock signal in order to pass the stored data onto a data highway at the correct instant. This signal is generated by a symmetrical circuit configuration that, by virtue of the integration of a multiplexer in a clock ratio compensator, additionally generates the output clock signal in a minimal time.
摘要翻译： DDR SDRAM存储器芯片需要高精度的输出时钟信号，以便在正确的时刻将存储的数据传送到数据高速公路上。该信号由对称电路配置产生，由于多路复用器在时钟比率补偿器中的积分，在最小时间内另外产生输出时钟信号。

15. 发明授权

US06351167B1 Integrated circuit with a phase locked loop 有权
标题翻译：具有锁相环的集成电路
公开(公告)号：US06351167B1
公开(公告)日：2002-02-26
申请号：US09608563
申请日：2000-06-30
申请人： Thomas Hein , Thilo Marx , Patrick Heyne , Torsten Partsch
发明人： Thomas Hein , Thilo Marx , Patrick Heyne , Torsten Partsch
IPC分类号： H03L700
CPC分类号： H03L7/0805 , H03K5/13 , H03L7/0814
摘要： A phase regulator is connected, on the input side, to the output of a phase comparator and generates a control signal in a manner dependent on the phase difference ascertained by said comparator. Updating of the control signal fed to a control input of a first delay unit is triggered by an edge of the first output clock signal occurring at the clock output of the first delay unit.
摘要翻译：相位调节器在输入侧连接到相位检测器的输出，并以取决于由所述检测器确定的相位差的方式产生控制信号。馈送到第一延迟单元的控制输入的控制信号的更新由在第一延迟单元的时钟输出处发生的第一输出时钟信号的边沿触发。

16. 发明授权

US07363561B2 Method and circuit arrangement for resetting an integrated circuit 有权
标题翻译：用于复位集成电路的方法和电路装置
公开(公告)号：US07363561B2
公开(公告)日：2008-04-22
申请号：US11117736
申请日：2005-04-29
申请人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schrögmeier
发明人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schrögmeier
IPC分类号： G01R31/28
CPC分类号： G06F1/24 , H03K5/1534
摘要： The invention relates to a method for resetting at least one circuit part of an integrated circuit, in particular a synchronous semiconductor memory, in which a clock signal and a clock signal that is inverted with respect to the latter are provided in order to clock the integrated circuit, and in which, when a reset condition is present, an item of reset information is coded onto the clock signal or onto the inverted clock signal. The invention also relates to a circuit arrangement for carrying out the method according to the invention, having a clock suppression device and a decoder circuit, which is intended to extract the reset information from the clock signal or from the inverted clock signal.
摘要翻译：本发明涉及一种用于复位集成电路，特别是同步半导体存储器的至少一个电路部分的方法，其中提供时钟信号和相对于后者反相的时钟信号，以便对集成电路电路，并且当存在复位条件时，将复位信息的项目编码到时钟信号或反相时钟信号上。本发明还涉及用于执行根据本发明的方法的电路装置，其具有时钟抑制装置和解码器电路，其用于从时钟信号或反相时钟信号中提取复位信息。

17. 发明授权

US06584021B2 Semiconductor memory having a delay locked loop 有权
公开(公告)号：US06584021B2
公开(公告)日：2003-06-24
申请号：US10047824
申请日：2002-01-15
申请人： Patrick Heyne , Thomas Hein , Torsten Partsch , Marx Thilo
发明人： Patrick Heyne , Thomas Hein , Torsten Partsch , Marx Thilo
IPC分类号： G11C700
CPC分类号： G11C7/222 , G11C7/1051 , G11C7/22
摘要： A synchronous semiconductor memory containing dynamic memory cells has a delay locked loop in order to synchronize a clock signal which actuates data output drivers with an externally supplied clock signal. An updating of the delay locked loop is suppressed during a Read state of the semiconductor memory. An appropriate control signal is produced by a state machine and is supplied to the delay locked loop. The synchronization of the data output with the supplied clock signal can be achieved in a precise manner and requires only simple circuitry.

18. 发明申请

US20050270852A1 Read latency control circuit 有权
标题翻译：读延迟控制电路
公开(公告)号：US20050270852A1
公开(公告)日：2005-12-08
申请号：US11136712
申请日：2005-05-25
申请人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schroegmeier
发明人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schroegmeier
IPC分类号： G06F3/06 , G11C7/22 , G11C11/4076
CPC分类号： G11C11/4076 , G11C7/1066 , G11C7/20 , G11C7/22 , G11C7/222 , G11C11/4072 , G11C2207/2272
摘要： The invention provides a method for setting and controlling a read latency (L) by means of a FIFO-based read latency control circuit for a read access to a semiconductor memory, having the method steps of providing a common internal clock signal; generating an internal first clock signal and an internal second clock signal, which is different from the first clock signal, from the common clock signal; generating an output pointer for reading out the read data from the first clock signal; generating an input pointer for reading in the read data from the second clock signal; initializing the input and output pointers by allocating a defined, fixedly predetermined time offset between output pointer and input pointer. The invention furthermore provides a corresponding circuit arrangement for carrying out the method.
摘要翻译：本发明提供了一种用于通过用于对半导体存储器的读取访问的基于FIFO的读延迟控制电路来设置和控制读延迟（L）的方法，具有提供公共内部时钟信号的方法步骤; 从公共时钟信号产生与第一时钟信号不同的内部第一时钟信号和内部第二时钟信号; 产生用于从所述第一时钟信号读出读取数据的输出指针; 生成用于从所述第二时钟信号读取所述读取数据的输入指针; 通过在输出指针和输入指针之间分配定义的，固定地预定的时间偏移来初始化输入和输出指针。本发明还提供了一种用于执行该方法的相应电路装置。

19. 发明申请

US20050253638A1 Method and circuit arrangement for resetting an integrated circuit 有权
标题翻译：用于复位集成电路的方法和电路装置
公开(公告)号：US20050253638A1
公开(公告)日：2005-11-17
申请号：US11117736
申请日：2005-04-29
申请人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schrogmeier
发明人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schrogmeier
IPC分类号： G06F1/24 , G11C5/14 , G11C11/4072 , H01L21/82 , H03K5/1534 , H03L7/00
CPC分类号： G06F1/24 , H03K5/1534
摘要： The invention relates to a method for resetting at least one circuit part of an integrated circuit, in particular a synchronous semiconductor memory, in which a clock signal and a clock signal that is inverted with respect to the latter are provided in order to clock the integrated circuit, and in which, when a reset condition is present, an item of reset information is coded onto the clock signal or onto the inverted clock signal. The invention also relates to a circuit arrangement for carrying out the method according to the invention, having a clock suppression device and a decoder circuit, which is intended to extract the reset information from the clock signal or from the inverted clock signal.
摘要翻译：本发明涉及一种用于复位集成电路，特别是同步半导体存储器的至少一个电路部分的方法，其中提供时钟信号和相对于后者反相的时钟信号，以便对集成电路电路，并且当存在复位条件时，将复位信息的项目编码到时钟信号或反相时钟信号上。本发明还涉及用于执行根据本发明的方法的电路装置，其具有时钟抑制装置和解码器电路，其用于从时钟信号或反相时钟信号中提取复位信息。

20. 发明授权

US07404018B2 Read latency control circuit 有权
标题翻译：读延迟控制电路
公开(公告)号：US07404018B2
公开(公告)日：2008-07-22
申请号：US11136712
申请日：2005-05-25
申请人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schroegmeier
发明人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schroegmeier
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G11C11/4076 , G11C7/1066 , G11C7/20 , G11C7/22 , G11C7/222 , G11C11/4072 , G11C2207/2272
摘要： The invention provides a method for setting and controlling a read latency (L) by means of a FIFO-based read latency control circuit for a read access to a semiconductor memory, having the method steps of providing a common internal clock signal; generating an internal first clock signal and an internal second clock signal, which is different from the first clock signal, from the common clock signal; generating an output pointer for reading out the read data from the first clock signal; generating an input pointer for reading in the read data from the second clock signal; initializing the input and output pointers by allocating a defined, fixedly predetermined time offset between output pointer and input pointer. The invention furthermore provides a corresponding circuit arrangement for carrying out the method.
摘要翻译：本发明提供了一种用于通过用于对半导体存储器的读取访问的基于FIFO的读延迟控制电路来设置和控制读延迟（L）的方法，具有提供公共内部时钟信号的方法步骤; 从公共时钟信号产生与第一时钟信号不同的内部第一时钟信号和内部第二时钟信号; 产生用于从所述第一时钟信号读出读取数据的输出指针; 生成用于从所述第二时钟信号读取所述读取数据的输入指针; 通过在输出指针和输入指针之间分配定义的，固定地预定的时间偏移来初始化输入和输出指针。本发明还提供了一种用于执行该方法的相应电路装置。

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