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11. 发明授权

US08236578B2 Electronic device including a magneto-resistive memory device and a process for forming the electronic device 有权
公开(公告)号：US08236578B2
公开(公告)日：2012-08-07
申请号：US13358231
申请日：2012-01-25
申请人： Phillip G. Mather , Sanjeev Aggarwal , Brian R. Butcher , Renu W. Dave , Frederick B. Mancoff , Nicholas D. Rizzo
发明人： Phillip G. Mather , Sanjeev Aggarwal , Brian R. Butcher , Renu W. Dave , Frederick B. Mancoff , Nicholas D. Rizzo
IPC分类号： H01L21/00
CPC分类号： H01L43/08 , B82Y10/00 , B82Y25/00 , G11C11/161 , H01L43/12
摘要： A process of forming an electronic device can include forming a stack including a tunnel barrier layer. The tunnel barrier layer can have a ratio of the metal atoms to oxygen atoms of greater than a stoichiometric ratio, wherein the ratio has a particular value. The process can also include forming a gettering layer having a composition capable of gettering oxygen, and depositing an insulating layer over the gettering layer. The process can further include exposing the insulating layer to a temperature of at least approximately 60° C. In one embodiment, after such exposure, a portion of the gettering layer is converted to an insulating material. In another embodiment, an electronic device can include a magnetic tunnel junction and an adjacent insulating layer lying within an opening in another insulating layer.

12. 发明授权

US06956763B2 MRAM element and methods for writing the MRAM element 失效
标题翻译： MRAM元素和写入MRAM元素的方法
公开(公告)号：US06956763B2
公开(公告)日：2005-10-18
申请号：US10609288
申请日：2003-06-27
申请人： Bengt J. Akerman , Mark F. Deherrera , Bradley N. Engel , Nicholas D. Rizzo
发明人： Bengt J. Akerman , Mark F. Deherrera , Bradley N. Engel , Nicholas D. Rizzo
IPC分类号： G11C11/155 , G11C11/00
CPC分类号： G11C11/155
摘要： A direct write is provided for a magnetoelectronics information device that includes producing a first magnetic field with a first field magnitude in proximity to the magnetoelectronics information device at a first time (t1). Once this first magnetic field with the first magnitude is produced, a second magnetic field with a second field magnitude is produced in proximity to the magnetoelectronics information device at a second time (t2). The first magnetic field is adjusted to provide a third magnitude at a third time (t3) that is less than the first field magnitude and greater than zero, and the second magnetic field is adjusted to provide a fourth field magnitude at a fourth time (t4) that is less than the second field magnitude. This direct write is used in conjunction with other direct writes and also in combination with toggle writes to write the MRAM element without an initial read.
摘要翻译：提供了一种用于磁电子信息设备的直接写入，其包括在第一时间（t 1> 1）处产生具有接近磁电子信息器件的第一场强的第一磁场。一旦产生具有第一幅度的第一磁场，则在第二时间（t 2> 2）处产生具有第二磁场强度的第二磁场，靠近磁电子信息装置。第一磁场被调整以在小于第一场幅度并大于零的第三时间（t 3/3）处提供第三幅度，并且调整第二磁场以提供第四磁场小于第二场强的第四时间（t> 4 ）的场强。这种直接写入与其他直接写入一起使用，并且与切换写入组合使用以写入MRAM元素而不进行初始读取。

13. 发明申请

US20090085058A1 ELECTRONIC DEVICE INCLUDING A MAGNETO-RESISTIVE MEMORY DEVICE AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE 有权
标题翻译：包括磁电阻记忆体装置的电子装置和形成电子装置的方法
公开(公告)号：US20090085058A1
公开(公告)日：2009-04-02
申请号：US11864409
申请日：2007-09-28
申请人： Phillip G. Mather , Sanjeev Aggarwal , Brian R. Butcher , Renu W. Dave , Frederick B. Mancoff , Nicholas D. Rizzo
发明人： Phillip G. Mather , Sanjeev Aggarwal , Brian R. Butcher , Renu W. Dave , Frederick B. Mancoff , Nicholas D. Rizzo
IPC分类号： H01L29/82 , H01L21/46
CPC分类号： H01L43/08 , B82Y10/00 , B82Y25/00 , G11C11/161 , H01L43/12
摘要： A process of forming an electronic device can include forming a stack including a tunnel barrier layer. The tunnel barrier layer can have a ratio of the metal atoms to oxygen atoms of greater than a stoichiometric ratio, wherein the ratio has a particular value. The process can also include forming a gettering layer having a composition capable of gettering oxygen, and depositing an insulating layer over the gettering layer. The process can further include exposing the insulating layer to a temperature of at least approximately 60° C. In one embodiment, after such exposure, a portion of the gettering layer is converted to an insulating material. In another embodiment, an electronic device can include a magnetic tunnel junction and an adjacent insulating layer lying within an opening in another insulating layer.
摘要翻译：形成电子器件的工艺可以包括形成包括隧道势垒层的堆叠。隧道阻挡层可以具有大于化学计量比的金属原子与氧原子的比例，其中该比率具有特定值。该方法还可以包括形成具有能够吸收氧的组成的吸气层，以及在吸气层上沉积绝缘层。该方法还可以包括将绝缘层暴露于至少约60℃的温度。在一个实施方案中，在这种曝光之后，将一部分吸气层转化为绝缘材料。在另一个实施例中，电子设备可以包括磁性隧道结和位于另一绝缘层的开口内的相邻绝缘层。

14. 发明申请

US20120122247A1 ELECTRONIC DEVICE INCLUDING A MAGNETO-RESISTIVE MEMORY DEVICE AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE 有权
标题翻译：包括磁电阻记忆体装置的电子装置和形成电子装置的方法
公开(公告)号：US20120122247A1
公开(公告)日：2012-05-17
申请号：US13358231
申请日：2012-01-25
申请人： Phillip G. Mather , Sanjeev Aggarwal , Brian R. Butcher , Renu W. Dave , Frederick B. Mancoff , Nicholas D. Rizzo
发明人： Phillip G. Mather , Sanjeev Aggarwal , Brian R. Butcher , Renu W. Dave , Frederick B. Mancoff , Nicholas D. Rizzo
IPC分类号： H01L21/20
CPC分类号： H01L43/08 , B82Y10/00 , B82Y25/00 , G11C11/161 , H01L43/12
摘要： A process of forming an electronic device can include forming a stack including a tunnel barrier layer. The tunnel barrier layer can have a ratio of the metal atoms to oxygen atoms of greater than a stoichiometric ratio, wherein the ratio has a particular value. The process can also include forming a gettering layer having a composition capable of gettering oxygen, and depositing an insulating layer over the gettering layer. The process can further include exposing the insulating layer to a temperature of at least approximately 60° C. In one embodiment, after such exposure, a portion of the gettering layer is converted to an insulating material. In another embodiment, an electronic device can include a magnetic tunnel junction and an adjacent insulating layer lying within an opening in another insulating layer.
摘要翻译：形成电子器件的工艺可以包括形成包括隧道势垒层的堆叠。隧道阻挡层可以具有大于化学计量比的金属原子与氧原子的比例，其中该比率具有特定值。该方法还可以包括形成具有能够吸收氧的组成的吸气层，以及在吸气层上沉积绝缘层。该方法还可以包括将绝缘层暴露于至少约60℃的温度。在一个实施方案中，在这种曝光之后，将一部分吸气层转化为绝缘材料。在另一个实施例中，电子设备可以包括磁性隧道结和位于另一绝缘层的开口内的相邻绝缘层。

15. 发明授权

US08119424B2 Electronic device including a magneto-resistive memory device and a process for forming the electronic device 有权
标题翻译：包括磁阻存储器件的电子器件和用于形成电子器件的工艺
公开(公告)号：US08119424B2
公开(公告)日：2012-02-21
申请号：US11864409
申请日：2007-09-28
申请人： Phillip G. Mather , Sanjeev Aggarwal , Brian R. Butcher , Renu W. Dave , Frederick B. Mancoff , Nicholas D. Rizzo
发明人： Phillip G. Mather , Sanjeev Aggarwal , Brian R. Butcher , Renu W. Dave , Frederick B. Mancoff , Nicholas D. Rizzo
IPC分类号： H01L21/00
CPC分类号： H01L43/08 , B82Y10/00 , B82Y25/00 , G11C11/161 , H01L43/12
摘要： A process of forming an electronic device can include forming a stack including a tunnel barrier layer. The tunnel barrier layer can have a ratio of the metal atoms to oxygen atoms of greater than a stoichiometric ratio, wherein the ratio has a particular value. The process can also include forming a gettering layer having a composition capable of gettering oxygen, and depositing an insulating layer over the gettering layer. The process can further include exposing the insulating layer to a temperature of at least approximately 60° C. In one embodiment, after such exposure, a portion of the gettering layer is converted to an insulating material. In another embodiment, an electronic device can include a magnetic tunnel junction and an adjacent insulating layer lying within an opening in another insulating layer.
摘要翻译：形成电子器件的工艺可以包括形成包括隧道势垒层的堆叠。隧道阻挡层可以具有大于化学计量比的金属原子与氧原子的比例，其中该比率具有特定值。该方法还可以包括形成具有能够吸收氧的组成的吸气层，以及在吸气层上沉积绝缘层。该方法还可以包括将绝缘层暴露于至少约60℃的温度。在一个实施方案中，在这种曝光之后，将一部分吸气层转化为绝缘材料。在另一个实施例中，电子设备可以包括磁性隧道结和位于另一绝缘层的开口内的相邻绝缘层。

16. 发明授权

US06579625B1 Magnetoelectronics element having a magnetic layer formed of multiple sub-element layers 失效
标题翻译：具有由多个子元件层形成的磁性层的磁电元件
公开(公告)号：US06579625B1
公开(公告)日：2003-06-17
申请号：US09695467
申请日：2000-10-24
申请人： Bradley N. Engel , Nicholas D. Rizzo , Jason A. Janesky , Saied Tehrani
发明人： Bradley N. Engel , Nicholas D. Rizzo , Jason A. Janesky , Saied Tehrani
IPC分类号： G11B5127
CPC分类号： H01F10/3254 , B82Y10/00 , B82Y25/00 , G11C11/16 , H01F10/32 , H01L27/222 , H01L43/08 , Y10T428/1171 , Y10T428/12465 , Y10T428/12639 , Y10T428/24942 , Y10T428/31
摘要： A magnetic layer (46) of a magnetoelectronics element (40) is provided that has a first sub-element layer (48) and a second sub-element layer (50). The first sub-element layer (48) is configured to have a first area and the second sub-element layer (50) is configured to have a second area that is less than the first area.
摘要翻译：提供了具有第一子元件层（48）和第二子元件层（50）的磁电元件（40）的磁性层（46）。第一子元件层（48）被配置为具有第一区域，并且第二子元件层（50）被配置为具有小于第一区域的第二区域。

17. 发明授权

US07235408B2 Synthetic antiferromagnetic structure for magnetoelectronic devices 失效
标题翻译：用于磁电子器件的合成反铁磁结构
公开(公告)号：US07235408B2
公开(公告)日：2007-06-26
申请号：US11075587
申请日：2005-03-09
申请人： Jason Allen Janesky , Bradley N. Engel , Nicholas D. Rizzo , Jon M Slaughter
发明人： Jason Allen Janesky , Bradley N. Engel , Nicholas D. Rizzo , Jon M Slaughter
IPC分类号： H01L21/00
CPC分类号： H01L43/08 , B82Y10/00 , B82Y25/00 , B82Y40/00 , G01R33/093 , G11C11/16 , H01F10/3254 , H01F10/3272 , H01F41/302 , H01L43/12
摘要： A nearly balanced synthetic antiferromagnetic (SAF) structure that can be advantageously used in magnetoelectronic devices such as a magnetoresistive memory cell includes two ferromagnetic layers and an antiferromagnetic coupling layer separating the two ferromagnetic layers. The SAF free layer has weakly coupled regions formed in the antiferromagnetic coupling layer by a treatment such as annealing, layering of the antiferromagnetic coupling layer, or forming the antiferromagnetic coupling layer over a roughened surface of a ferromagnetic layer. The weakly coupled regions lower the flop field of the SAF free layer in comparison to untreated SAF free layers. The SAF flop is used during the write operation of such a structure and its reduction results in lower power consumption during write operations and correspondingly increased device performance.
摘要翻译：可以有利地用于诸如磁阻存储器单元的磁电子器件中的几乎平衡的合成反铁磁（SAF）结构包括两个铁磁层和分离两个铁磁层的反铁磁耦合层。 SAF自由层通过诸如退火，反铁磁耦合层的分层或在铁磁层的粗糙表面上形成反铁磁耦合层的处理，在反铁磁耦合层中形成弱耦合区域。与未处理的SAF自由层相比，弱耦合区域降低了SAF自由层的触发场。在这种结构的写入操作期间使用SAF触发器，并且其减少导致在写入操作期间较低的功耗并且相应地增加器件性能。

18. 发明授权

US07158407B2 Triple pulse method for MRAM toggle bit characterization 失效
标题翻译：用于MRAM切换位特性的三脉冲方法
公开(公告)号：US07158407B2
公开(公告)日：2007-01-02
申请号：US11118145
申请日：2005-04-29
申请人： Nicholas D. Rizzo , Mark F. Deherrera , Jason A. Janesky
发明人： Nicholas D. Rizzo , Mark F. Deherrera , Jason A. Janesky
IPC分类号： G11C11/15
CPC分类号： G11C11/16 , G11C29/50
摘要： A method is provided for testing magnetic bits (3, 104, 514) of an array. A train of first (702), second (704), and third (706) pulses is provided to a desired bit, the first and second pulses beginning at a substantially similar low field and increasing in similar amounts with respect to successive trains of the first, second, and third pulses, the third pulse having a current amplitude sufficient to toggle the magnetic bit. A representative count is recorded in response to switching of the bit. The above steps are repeated and a determination is made of the current amplitude required to write and toggle the bit.
摘要翻译：提供了一种用于测试阵列的磁头（3,104,514）的方法。将第一（702），第二（704）和第三（706）脉冲串提供给期望的位，第一和第二脉冲以基本相似的低场开始，并且相对于第一，第二和第三脉冲，第三脉冲具有足以切换磁头的电流幅度。响应于位的切换记录代表计数。重复上述步骤，并确定写入和切换位所需的当前幅度。

19. 发明授权

US07965543B2 Method for reducing current density in a magnetoelectronic device 有权
标题翻译：一种用于降低磁电子器件中的电流密度的方法
公开(公告)号：US07965543B2
公开(公告)日：2011-06-21
申请号：US12433670
申请日：2009-04-30
申请人： Jon M. Slaughter , Nicholas D. Rizzo
发明人： Jon M. Slaughter , Nicholas D. Rizzo
IPC分类号： G11C11/00
CPC分类号： G11C11/1693 , G11C11/161 , G11C11/1675
摘要： A method for reducing spin-torque current density needed to switch a magnetoelectronic device (200, 300, 400), includes applying (602) a voltage bias having a predetermined polarity to the magnetoelectronic device (200, 300, 400) that creates a spin-polarized current with spin torque transfer to a synthetic antiferromagnet free layer (206), applying (604) a magnetic field having a predetermined direction to the magnetoelectronic device (200, 300, 400), removing (606) the applied magnetic field; and removing (608) the voltage bias subsequent to removing (606) the applied magnetic field, wherein the polarity of the voltage bias and the direction of the magnetic field leave the synthetic antiferromagnet free layer (206) in a predetermined magnetic state after the voltage bias is removed.
摘要翻译：一种用于减小切换磁电子器件（200,300,400）所需的自旋转矩电流密度的方法包括将具有预定极性的电压偏置（602）施加到产生旋转的磁电子器件（200,300,400）上具有自旋转矩传递到合成反铁磁自由层（206）的偏振电流，向磁电子器件（200,300,400）施加（604）具有预定方向的磁场，去除（606）所施加的磁场; 以及在去除（606）所施加的磁场之后去除（608）所述电压偏置，其中所述电压偏置的极性和所述磁场的方向在所述电压之后离开所述合成的反铁磁自由层（206）处于预定的磁状态偏移被去除。

20. 发明申请

US20080205130A1 MRAM FREE LAYER SYNTHETIC ANTIFERROMAGNET STRUCTURE AND METHODS 审中-公开
标题翻译： MRAM自由层合成抗体网络结构与方法
公开(公告)号：US20080205130A1
公开(公告)日：2008-08-28
申请号：US11679982
申请日：2007-02-28
申请人： Jijun Sun , Nicholas D. Rizzo , Jon M. Slaughter
发明人： Jijun Sun , Nicholas D. Rizzo , Jon M. Slaughter
IPC分类号： G11C11/15 , H01L21/00 , H01L29/82
CPC分类号： G11C11/16 , B82Y25/00 , B82Y40/00 , H01F10/3254 , H01F10/3272 , H01F41/302 , H01L43/08
摘要： A magnetic tunnel junction (MTJ) structure for use with toggle MRAM devices and the like includes a tunnel barrier layer and a synthetic antiferromagnet (SAF) structure formed on the tunnel barrier layer, wherein the SAF includes a plurality (e.g., three or more) ferromagnetic layers antiferromagnetically or ferromagnetically coupled by a plurality of respective coupling layers. The bottom ferromagnetic layer adjacent the tunnel barrier layer has a high spin polarization and a high intrinsic anisotropy field (Hki) while one or more of the remaining ferromagnetic layers has a low intrinsic anisotropy field Hki.
摘要翻译：与切换MRAM器件等一起使用的磁隧道结（MTJ）结构包括形成在隧道势垒层上的隧道势垒层和合成反铁磁体（SAF）结构，其中SAF包括多个（例如三个或更多个）铁磁层通过多个相应的耦合层反铁磁或铁磁耦合。与隧道势垒层相邻的底部铁磁层具有高的自旋极化和高的本征各向异性场（H >Ki），而一个或多个剩余的铁磁层具有低的固有各向异性场H ki 。

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