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11. 发明授权

US06964875B1 Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitance 失效
标题翻译：用于测量栅介质厚度和寄生电容的栅介质结构阵列
公开(公告)号：US06964875B1
公开(公告)日：2005-11-15
申请号：US10962582
申请日：2004-10-13
申请人： William G. En , Mark W. Michael , Hai Hong Wang , Simon Siu-Sing Chan
发明人： William G. En , Mark W. Michael , Hai Hong Wang , Simon Siu-Sing Chan
IPC分类号： H01L21/66 , H01L21/8234 , H01L23/544 , H01L27/08 , H01L29/76 , H01L31/119
CPC分类号： H01L22/34 , H01L21/823437 , H01L27/0811 , H01L2924/0002 , H01L2924/00
摘要： Accurate determination of gate dielectric thickness is required to produce high-reliability and high-performance ultra-thin gate dielectric semiconductor devices. Large area gate dielectric capacitors with ultra-thin gate dielectric layers suffer from high gate leakage, which prevents the accurate measurement of gate dielectric thickness. Accurate measurement of gate dielectric thickness of smaller area gate dielectric capacitors is hindered by the relatively large parasitic capacitance of the smaller area capacitors. The formation of first and second dummy structures on a wafer allow the accurate determination of gate dielectric thickness. First and second dummy structures are formed that are substantially similar to the gate dielectric capacitors except that the first dummy structures are formed without the second electrode of the capacitor and the second dummy structures are formed without the first electrode of the capacitor structure. The capacitance, and therefore thickness, of the gate dielectric capacitor is determined by subtracting the parasitic capacitances measured at the first and second dummy structures.
摘要翻译：制造高可靠性和高性能超薄栅极电介质半导体器件需要精确确定栅极电介质厚度。具有超薄栅极介电层的大面积栅极介质电容器具有高栅极泄漏，这阻止了栅极电介质厚度的精确测量。较小面积的电介质电容器的栅极电介质厚度的精确测量受到较小面积电容器的相对大的寄生电容的阻碍。在晶片上形成第一和第二虚拟结构允许准确地确定栅极电介质厚度。形成基本上类似于栅极介电电容器的第一和第二虚拟结构，除了第一虚拟结构形成而没有电容器的第二电极，并且第二虚拟结构形成而没有电容器结构的第一电极。通过减去在第一和第二虚拟结构处测量的寄生电容来确定栅极介电电容器的电容，并因此确定厚度。

12. 发明授权

US08102009B2 Integrated circuit eliminating source/drain junction spiking 有权
标题翻译：集成电路消除源极/漏极结尖峰
公开(公告)号：US08102009B2
公开(公告)日：2012-01-24
申请号：US11538156
申请日：2006-10-03
申请人： Simon Siu-Sing Chan , Paul R. Besser , Jeffrey P. Patton
发明人： Simon Siu-Sing Chan , Paul R. Besser , Jeffrey P. Patton
IPC分类号： H01L29/76
CPC分类号： H01L21/324 , H01L21/26506 , H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A metallic layer is on the semiconductor substrate, and the metallic layer is reacted with the semiconductor substrate to form an early phase of silicide. Implanted shallow source/drain junctions are immediately beneath the silicide. A final phase of the silicide is formed. An interlayer dielectric is above the semiconductor substrate, and contacts are formed to the silicide.
摘要翻译：提供了具有半导体衬底的集成电路。栅极电介质位于半导体衬底上，栅极位于栅极电介质上。金属层在半导体衬底上，金属层与半导体衬底反应形成硅化物的早期阶段。在硅化物的正下方，注入浅的源极/漏极结。形成硅化物的最终相。层间电介质在半导体衬底上方，并且与硅化物形成接触。

13. 发明申请

US20080153224A1 INTEGRATED CIRCUIT SYSTEM WITH MEMORY SYSTEM 审中-公开
标题翻译：具有存储器系统的集成电路系统
公开(公告)号：US20080153224A1
公开(公告)日：2008-06-26
申请号：US11735229
申请日：2007-04-13
申请人： Connie Pin Chin Wang , Simon Siu-Sing Chan , Angela T. Hui , Paul R. Besser , Shenqing Fang
发明人： Connie Pin Chin Wang , Simon Siu-Sing Chan , Angela T. Hui , Paul R. Besser , Shenqing Fang
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： An integrated circuit system is provided including forming a memory section having a spacer with a substrate, forming an outer doped region of the memory section in the substrate, forming a contact on the outer doped region, thinning the contact for forming a thinned contact, and forming a metal plug on the thinned contact.
摘要翻译：提供了一种集成电路系统，包括形成具有衬底的间隔物的存储部分，在衬底中形成存储部分的外部掺杂区域，在外部掺杂区域上形成接触，减少接触以形成变薄的接触，以及在变薄的触点上形成金属插头。

14. 发明授权

US06969678B1 Multi-silicide in integrated circuit technology 失效
标题翻译：集成电路技术中的多硅化物
公开(公告)号：US06969678B1
公开(公告)日：2005-11-29
申请号：US10700711
申请日：2003-11-03
申请人： Robert J. Chiu , Paul R. Besser , Simon Siu-Sing Chan , Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Errol Todd Ryan
发明人： Robert J. Chiu , Paul R. Besser , Simon Siu-Sing Chan , Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Errol Todd Ryan
IPC分类号： H01L21/285 , H01L21/336 , H01L21/44 , H01L29/78
CPC分类号： H01L29/7833 , H01L21/28518 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： A method of forming an integrated circuit, and an integrated circuit, are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.
摘要翻译：提供一种形成集成电路的方法和集成电路。在半导体衬底上形成栅极电介质，并且在栅极电介质上形成栅极。在栅极周围形成侧壁间隔物，并且使用侧壁间隔物在半导体衬底中形成源极/漏极结。底部硅化物金属沉积在源极/漏极结上，然后顶部硅化物金属沉积在底部的硅化物金属上。底部和顶部硅化物金属形成其硅化物。介电层沉积在半导体衬底的上方，并且在电介质层中形成与顶部硅化物的接触。

15. 发明授权

US06737337B1 Method of preventing dopant depletion in surface semiconductor layer of semiconductor-on-insulator (SOI) device 有权
标题翻译：防止绝缘体上半导体（SOI）器件的表面半导体层中的掺杂剂消耗的方法
公开(公告)号：US06737337B1
公开(公告)日：2004-05-18
申请号：US10134972
申请日：2002-04-29
申请人： Simon Siu-Sing Chan , Qi Xiang
发明人： Simon Siu-Sing Chan , Qi Xiang
IPC分类号： H01L2130
CPC分类号： H01L21/76254
摘要： A method of manufacturing a semiconductor device includes forming a buried insulator layer of a semiconductor-on-insulator (SOI) wafer with a dopant material, such as boron, therein. The insulator material with the dopant material may be formed by a number of methods, for example by thermal oxidation of a semiconductor wafer in the presence of an atmosphere containing the dopant material, by co-deposition of the insulator material and the dopant material, or by co-implantation of an insulator material and the dopant material. The dopant material may be the same as a dopant material in at least a region (e.g., a source, drain, or channel region) of a semiconductor material layer which overlies the insulator layer. The dopant material in the buried insulator layer may advantageously reduce the tendency of dopant material to migrate from the overlying material to the insulator layer, such as during manufacturing operations involving heating.
摘要翻译：一种制造半导体器件的方法包括在其中用诸如硼的掺杂剂材料形成绝缘体上半导体（SOI）晶片的掩埋绝缘体层。具有掺杂剂材料的绝缘体材料可以通过多种方法形成，例如通过在包含掺杂剂材料的气氛存在的情况下通过半导体晶片的热氧化，通过绝缘体材料和掺杂剂材料的共沉积，或通过共注入绝缘体材料和掺杂剂材料。掺杂剂材料可以与至少覆盖绝缘体层的半导体材料层的区域（例如，源极，漏极或沟道区）中的掺杂剂材料相同。掩埋绝缘体层中的掺杂剂材料可以有利地降低掺杂剂材料从覆盖材料迁移到绝缘体层的趋势，例如在涉及加热的制造操作期间。

16. 发明授权

US07843015B2 Multi-silicide system in integrated circuit technology 有权
标题翻译：集成电路技术中的多硅化物系统
公开(公告)号：US07843015B2
公开(公告)日：2010-11-30
申请号：US11229188
申请日：2005-09-15
申请人： Robert J. Chiu , Paul R. Besser , Simon Siu-Sing Chan , Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Errol Todd Ryan
发明人： Robert J. Chiu , Paul R. Besser , Simon Siu-Sing Chan , Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Errol Todd Ryan
IPC分类号： H01L21/02
CPC分类号： H01L29/7833 , H01L21/28518 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： An integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.
摘要翻译：提供集成电路。在半导体衬底上形成栅极电介质，并且在栅极电介质上形成栅极。在栅极周围形成侧壁间隔物，并且使用侧壁间隔物在半导体衬底中形成源极/漏极结。底部硅化物金属沉积在源极/漏极结上，然后顶部硅化物金属沉积在底部的硅化物金属上。底部和顶部硅化物金属形成其硅化物。介电层沉积在半导体衬底的上方，并且在电介质层中形成与顶部硅化物的接触。

17. 发明授权

US07250667B2 Selectable open circuit and anti-fuse element 有权
标题翻译：可选开路和反熔丝元件
公开(公告)号：US07250667B2
公开(公告)日：2007-07-31
申请号：US11306663
申请日：2006-01-05
申请人： Darin A. Chan , Simon Siu-Sing Chan , Paul L. King
发明人： Darin A. Chan , Simon Siu-Sing Chan , Paul L. King
IPC分类号： H01L29/00
CPC分类号： H01L27/112 , H01L23/5252 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is provided with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. Source/drain junctions are in the semiconductor substrate. A silicide is on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is above the semiconductor substrate. Contacts and connection points are in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.
摘要翻译：集成电路设置有半导体衬底，当半导体衬底反应以形成这种硅化物时，半导体衬底被掺杂为具有与硅化物的顶表面分离的类型的可氧化掺杂剂的设定浓度。栅极电介质位于半导体衬底上，栅极位于栅极电介质上。源极/漏极结在半导体衬底中。硅化物在源极/漏极结上，掺杂剂分离到硅化物的顶表面。分离的掺杂剂的顶表面上的掺杂剂被氧化以在硅化物之上形成氧化掺杂剂的绝缘层。层间电介质在半导体衬底之上。触点和连接点位于硅化物之上的氧化掺杂剂的绝缘层的层间电介质中。

18. 发明授权

US07015076B1 Selectable open circuit and anti-fuse element, and fabrication method therefor 失效
标题翻译：可选开路和反熔丝元件及其制造方法
公开(公告)号：US07015076B1
公开(公告)日：2006-03-21
申请号：US10791098
申请日：2004-03-01
申请人： Darin A. Chan , Simon Siu-Sing Chan , Paul L. King
发明人： Darin A. Chan , Simon Siu-Sing Chan , Paul L. King
IPC分类号： H01L21/82
CPC分类号： H01L27/112 , H01L23/5252 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A method is provided of forming an integrated circuit with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is deposited above the semiconductor substrate. Contacts and connection points are then formed in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.
摘要翻译：提供了一种形成集成电路的方法，该半导体衬底在半导体衬底反应形成这种硅化物时，掺杂有一定类型的可氧化掺杂剂的分解与硅化物顶表面的浓度。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。在半导体衬底中形成源极/漏极结。在源极/漏极结上形成硅化物，掺杂剂分离到硅化物的顶表面。分离的掺杂剂的顶表面上的掺杂剂被氧化以在硅化物之上形成氧化掺杂剂的绝缘层。在半导体衬底上沉积层间电介质。接触点和连接点然后在层间电介质中形成到硅化物之上的氧化掺杂剂的绝缘层。

19. 发明授权

US06841832B1 Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitance 失效
公开(公告)号：US06841832B1
公开(公告)日：2005-01-11
申请号：US10021497
申请日：2001-12-19
申请人： William G. En , Mark W. Michael , Hai Hong Wang , Simon Siu-Sing Chan
发明人： William G. En , Mark W. Michael , Hai Hong Wang , Simon Siu-Sing Chan
IPC分类号： H01L21/66 , H01L21/8234 , H01L23/544 , H01L27/08 , H01L29/76 , H01L31/119
CPC分类号： H01L22/34 , H01L21/823437 , H01L27/0811 , H01L2924/0002 , H01L2924/00
摘要： Accurate determination of gate dielectric thickness is required to produce high-reliability and high-performance ultra-thin gate dielectric semiconductor devices. Large area gate dielectric capacitors with ultra-thin gate dielectric layers suffer from high gate leakage, which prevents the accurate measurement of gate dielectric thickness. Accurate measurement of gate dielectric thickness of smaller area gate dielectric capacitors is hindered by the relatively large parasitic capacitance of the smaller area capacitors. The formation of first and second dummy structures on a wafer allow the accurate determination of gate dielectric thickness. First and second dummy structures are formed that are substantially similar to the gate dielectric capacitors except that the first dummy structures are formed without the second electrode of the capacitor and the second dummy structures are formed without the first electrode of the capacitor structure. The capacitance, and therefore thickness, of the gate dielectric capacitor is determined by subtracting the parasitic capacitances measured at the first and second dummy structures.

20. 发明授权

US06670259B1 Inert atom implantation method for SOI gettering 有权
标题翻译：用于SOI吸杂的惰性原子注入方法
公开(公告)号：US06670259B1
公开(公告)日：2003-12-30
申请号：US10068396
申请日：2002-02-05
申请人： Simon Siu-Sing Chan
发明人： Simon Siu-Sing Chan
IPC分类号： H01L21322
CPC分类号： H01L21/26506 , H01L21/2658 , H01L21/3226 , H01L21/76251
摘要： The present invention relates to a method of manufacturing a silicon-on-insulator substrate, comprising the steps of (1) providing a silicon-on-insulator semiconductor wafer having at least one surface of a silicon film; (2) implanting an inert atom into the at least one surface to form a damaged surface layer including a gettering site on the silicon film and to leave an undamaged region of the silicon film; (3) subjecting the wafer to conditions to getter at least one impurity from the silicon film into the gettering site; and (4) removing the damaged surface layer.
摘要翻译：本发明涉及一种制造绝缘体上硅衬底的方法，包括以下步骤：（1）提供具有至少一个硅膜表面的绝缘体上硅半导体晶片; （2）将惰性原子注入所述至少一个表面以形成包含硅膜上的吸杂位点并且留下未损坏的硅膜区域的受损表面层; （3）使晶片经受从硅膜吸收至少一种杂质到吸杂位置的条件; 和（4）去除损坏的表面层。

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