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11. 发明授权

US06678840B1 Fault containment and error recovery in a scalable multiprocessor 有权
标题翻译：可扩展多处理器中的故障控制和错误恢复
公开(公告)号：US06678840B1
公开(公告)日：2004-01-13
申请号：US09651949
申请日：2000-08-31
申请人： Richard E. Kessler , Peter J. Bannon , Kourosh Gharachorloo , Thukalan V. Verghese
发明人： Richard E. Kessler , Peter J. Bannon , Kourosh Gharachorloo , Thukalan V. Verghese
IPC分类号： G06F1100
CPC分类号： G06F11/0793 , G06F11/0724 , G06F15/17
摘要： A multi-processor computer system permits various types of partitions to be implemented to contain and isolate hardware failures. The various types of partitions include hard, semi-hard, firm, and soft partitions. Each partition can include one or more processors. Upon detecting a failure associated with a processor, the connection to adjacent processors in the system can be severed, thereby precluding corrupted data from contaminating the rest of the system. If an inter-processor connection is severed, message traffic in the system can become congested as messages become backed up in other processors. Accordingly, each processor includes various timers to monitor for traffic congestion that may be due to a severed connection. Rather than letting the processor continue to wait to be able to transmit its messages, the timers will expire at preprogrammed time periods and the processor will take appropriate action, such as simply dropping queued messages, to keep the system from locking up.
摘要翻译：多处理器计算机系统允许实现各种类型的分区以包含和隔离硬件故障。各种类型的分区包括硬，半硬，坚固和软分区。每个分区可以包括一个或多个处理器。当检测到与处理器相关联的故障时，可以切断与系统中的相邻处理器的连接，从而防止损坏的数据污染系统的其余部分。如果处理器间连接被切断，则在其他处理器中的消息备份时，系统中的消息流量可能会变得拥塞。因此，每个处理器包括各种定时器，以监视可能由于切断的连接造成的交通拥堵。而不是让处理器继续等待能够发送其消息，定时器将在预编程的时间段过期，并且处理器将采取适当的动作，例如简单地删除排队的消息，以防止系统锁定。

12. 发明授权

US06622217B2 Cache coherence protocol engine system and method for processing memory transaction in distinct address subsets during interleaved time periods in a multiprocessor system 失效
标题翻译：缓存一致性协议引擎系统和方法，用于在多处理器系统中的交织时间段期间处理不同地址子集中的存储器事务
公开(公告)号：US06622217B2
公开(公告)日：2003-09-16
申请号：US09878983
申请日：2001-06-11
申请人： Kourosh Gharachorloo , Luiz A. Barroso , Mosur K. Ravishankar , Robert J Stets, Jr. , Andreas Nowatzyk
发明人： Kourosh Gharachorloo , Luiz A. Barroso , Mosur K. Ravishankar , Robert J Stets, Jr. , Andreas Nowatzyk
IPC分类号： G06F1200
CPC分类号： G06F12/0828 , G06F2212/621
摘要： The present invention relates generally to a protocol engine for use in a multiprocessor computer system. The protocol engine, which implements a cache coherence protocol, includes a clock signal generator for generating signals denoting interleaved even clock periods and odd clock periods, a memory transaction state array for storing entries, each denoting the state of a respective memory transaction, and processing logic. The memory transactions are divided into even and odd transactions whose states are stored in distinct sets of entries in the memory transaction state array. The processing logic has interleaving circuitry for processing during even clock periods the even memory transactions and for processing during odd clock periods the odd memory transactions.
摘要翻译：本发明一般涉及在多处理器计算机系统中使用的协议引擎。实现高速缓存一致性协议的协议引擎包括时钟信号发生器，用于产生表示交织的偶数时钟周期和奇数时钟周期的信号，存储事务状态阵列，用于存储条目，每个表示各自的存储器事务的状态，以及处理逻辑。存储器事务被分为偶数和奇数事务，其状态存储在存储器事务状态数组中的不同的条目集合中。处理逻辑具有交织电路，用于在甚至时钟周期期间处理偶数存储器事务并且用于在奇数时钟周期期间处理奇数存储器事务。

13. 发明授权

US5933598A Method for sharing variable-grained memory of workstations by sending particular block including line and size of the block to exchange shared data structures 失效
标题翻译：通过发送包括块的行和大小的特定块来交换共享数据结构来共享工作站的可变粒度存储器的方法
公开(公告)号：US5933598A
公开(公告)日：1999-08-03
申请号：US682348
申请日：1996-07-17
申请人： Daniel J. Scales , Kourosh Gharachorloo
发明人： Daniel J. Scales , Kourosh Gharachorloo
IPC分类号： G06F9/50 , G06F13/00
CPC分类号： G06F9/5016
摘要： In a distributed shared memory system, workstations are connected to each other by a network. Each workstation includes a processor, a memory having addresses, and an input/output interface to interconnect the workstations. A software implemented method enables data sharing between the workstations using variable sized quantities of data. A set of the addresses of the memories are designated as virtual shared addresses to store shared data. A portion of the virtual shared addresses are allocated to store a shared data structure as one or more blocks. The shared data structure is accessible by programs executing in any of the processors. The size of a particular allocated block can vary for different shared data structures. Each block includes an integer number of lines, and each line includes a predetermined number of bytes of shared data. Access information of a particular block is stored in the memory of a home one of the workstations. The access information includes the size of the particular block and an identity of workstations having a copy of the block.
摘要翻译：在分布式共享存储器系统中，工作站通过网络彼此连接。每个工作站包括处理器，具有地址的存储器以及用于互连工作站的输入/输出接口。软件实现的方法使得可以使用可变大小数据的数据在工作站之间进行数据共享。一组存储器的地址被指定为虚拟共享地址以存储共享数据。虚拟共享地址的一部分被分配以将共享数据结构存储为一个或多个块。共享数据结构可由在任何处理器中执行的程序访问。特定分配的块的大小可以针对不同的共享数据结构而变化。每个块包括整数行，并且每行包括预定数量的共享数据字节。特定块的访问信息被存储在家庭工作站的存储器中。访问信息包括特定块的大小和具有该块的副本的工作站的标识。

14. 发明授权

US07523016B1 Detecting anomalies 有权
标题翻译：检测异常
公开(公告)号：US07523016B1
公开(公告)日：2009-04-21
申请号：US11618607
申请日：2006-12-29
申请人： Razvan Surdulescu , Kourosh Gharachorloo
发明人： Razvan Surdulescu , Kourosh Gharachorloo
IPC分类号： G06F11/30 , G21C17/00
CPC分类号： H04L63/1416 , G06F21/316 , G06F21/552 , G06Q30/00 , H04L63/1425
摘要： In general, systems and methods for identifying anomalous activity are described. For example, systems and methods are described, in which patterns of unusual behavior can be identified by aggregating logged, or sampled, data into cells and annotating each cell with statistically derived measures of how extreme the cell is relative to, for example, historical behavior of corresponding characteristics or relative to, for example, behavior of characteristics from a general population. Cells that have more than a predefined number of such annotations can be identified as anomalous and can be investigated by a user or outright acted upon in an automatic, pre-defined way.
摘要翻译：一般来说，描述用于识别异常活动的系统和方法。例如，描述了系统和方法，其中可以通过将记录的或采样的数据聚合到单元中并且通过统计学上导出的测量来注释每个单元来识别该异常行为的模式，该度量对于诸如历史行为或相对于例如来自普通人群的特征的行为。具有超过预定数量的这种注释的单元可以被识别为异常的，并且可以由用户进行调查或直接以自动的，预定义的方式进行操作。

15. 发明授权

US07502895B2 Techniques for reducing castouts in a snoop filter 有权
标题翻译：用于减少窥探过滤器中的铸件的技术
公开(公告)号：US07502895B2
公开(公告)日：2009-03-10
申请号：US11225937
申请日：2005-09-13
申请人： Phillip Matthew Jones , Kourosh Gharachorloo
发明人： Phillip Matthew Jones , Kourosh Gharachorloo
IPC分类号： G06F12/08
CPC分类号： G06F12/082 , G06F12/0831
摘要： Method and apparatus for reducing castouts in a snoop filter. More specifically, there is provided a system comprising a plurality of buses, one or more processors coupled to each of the plurality of buses and a snoop filter. The snoop filter configured to eliminate unnecessary snoops of the plurality of buses, and further configured to track requests from the one or more processors only if tracking the request does not result in a castout penalty.
摘要翻译：用于减少窥探过滤器中的铸件的方法和装置。更具体地，提供了一种包括多个总线，耦合到多个总线中的每一个的一个或多个处理器和窥探滤波器的系统。所述窥探过滤器被配置为消除所述多个总线中的不必要的窥探，并且还被配置为仅在跟踪所述请求不导致停顿罚分时才跟踪来自所述一个或多个处理器的请求。

16. 发明申请

US20070061520A1 Techniques for reducing castouts in a snoop filter 有权
标题翻译：用于减少窥探过滤器中的铸件的技术
公开(公告)号：US20070061520A1
公开(公告)日：2007-03-15
申请号：US11225937
申请日：2005-09-13
申请人： Phillip Jones , Kourosh Gharachorloo
发明人： Phillip Jones , Kourosh Gharachorloo
IPC分类号： G06F13/28
CPC分类号： G06F12/082 , G06F12/0831
摘要： Method and apparatus for reducing castouts in a snoop filter. More specifically, there is provided a system comprising a plurality of buses, one or more processors coupled to each of the plurality of buses and a snoop filter. The snoop filter configured to eliminate unnecessary snoops of the plurality of buses, and further configured to track requests from the one or more processors only if tracking the request does not result in a castout penalty
摘要翻译：用于减少窥探过滤器中的铸件的方法和装置。更具体地，提供了一种包括多个总线，耦合到多个总线中的每一个的一个或多个处理器和窥探滤波器的系统。所述窥探过滤器被配置为消除所述多个总线中的不必要的窥探，并且还被配置为仅在跟踪所述请求不导致停顿罚分时跟踪来自所述一个或多个处理器的请求

17. 发明授权

US06748498B2 Scalable multiprocessor system and cache coherence method implementing store-conditional memory transactions while an associated directory entry is encoded as a coarse bit vector 失效
标题翻译：可扩展的多处理器系统和缓存一致性方法实现存储条件存储器事务，而相关联的目录条目被编码为粗位向量
公开(公告)号：US06748498B2
公开(公告)日：2004-06-08
申请号：US10042053
申请日：2002-01-07
申请人： Kourosh Gharachorloo , Luiz Andre Barroso , Mosur K. Ravishankar , Robert J. Stets , Daniel J. Scales
发明人： Kourosh Gharachorloo , Luiz Andre Barroso , Mosur K. Ravishankar , Robert J. Stets , Daniel J. Scales
IPC分类号： G06F1200
CPC分类号： G06F12/0826 , G06F12/0828 , G06F2212/621 , Y10S707/99952
摘要： A system including a plurality of processor nodes is configured to execute a cache coherence protocol that avoids the use of negative acknowledgments and ordering requirements on the underlying transaction-message interconnect/network, and implements store-conditional memory transactions. A store-conditional memory transaction succeeds if a directory tracking the state of a memory line of information unambiguously indicates that the requesting node is the exclusive owner of the memory line, if the directory ambiguously indicates that the requesting node is sharing the memory line and the requesting node is in fact sharing the memory line, or if the directory unambiguously indicates that the requesting node is sharing the memory line. The store-conditional memory transaction fails if the directory unambiguously indicates that the requesting node is not sharing the memory line, or if the directory ambiguously indicates that the requesting node may be sharing the memory line and the requesting node is in fact not sharing the memory line.
摘要翻译：包括多个处理器节点的系统被配置为执行高速缓存一致性协议，其避免对底层事务消息互连/网络使用否定确认和排序要求，并且实现存储条件存储器事务。如果跟踪存储器线的状态的目录明确地指示请求节点是存储器线的专有所有者，则存储条件存储器事务成功，如果目录模糊地指示请求节点正在共享存储器线，并且请求节点实际上共享内存线，或者如果目录明确地指示请求节点正在共享存储器线。如果目录明确地指示请求节点不共享存储器线路，或者如果目录模糊地指示请求节点可能共享存储器线且请求节点实际上不共享存储器，则存储条件存储器事务将失败线。

18. 发明授权

US06738868B2 System for minimizing directory information in scalable multiprocessor systems with logically independent input/output nodes 失效
标题翻译：用于在具有逻辑独立的输入/输出节点的可扩展多处理器系统中最小化目录信息的系统
公开(公告)号：US06738868B2
公开(公告)日：2004-05-18
申请号：US10042035
申请日：2002-01-07
申请人： Kourosh Gharachorloo , Luiz Andre Barroso , Daniel J. Scales
发明人： Kourosh Gharachorloo , Luiz Andre Barroso , Daniel J. Scales
IPC分类号： G06F1200
CPC分类号： G06F12/0826 , G06F12/0828 , G06F2212/621
摘要： A system of scalable shared-memory multiprocessors includes processor nodes and I/O nodes. The I/O nodes connect I/O devices directly to an interconnection network of a system of scalable shared-memory multiprocessors. Each node of the system includes an interface to a local memory subsystem, a memory cache and a protocol engine. The local memory subsystem stores memory lines of information and a directory. Each entry in the directory stores sharing information concerning a memory line of information stored in the local memory subsystem. The protocol engine in each I/O node is configured to limit to a predefined period of time any sharing of a memory line of information from the memory subsystem of any other node. The protocol engine in the home node of the memory line is configured to identify only nodes other than I/O nodes that are sharing the memory line of information. In one embodiment, I/O nodes that share the memory line of information are not identified in the directory entry of the memory line, and instead are represented by a count field, which indicates how many I/O nodes share the memory line of information.
摘要翻译：可扩展共享存储器多处理器的系统包括处理器节点和I / O节点。 I / O节点将I / O设备直接连接到可扩展共享存储器多处理器系统的互连网络。系统的每个节点包括到本地存储器子系统的接口，存储器高速缓存和协议引擎。本地存储器子系统存储信息的存储线和目录。目录中的每个条目存储关于存储在本地存储器子系统中的信息的存储器线的共享信息。每个I / O节点中的协议引擎被配置为限制来自任何其他节点的存储器子系统的信息的存储器线的任何共享的预定时间段。存储器线路的家庭节点中的协议引擎被配置为仅识别正在共享信息的存储器线的I / O节点之外的节点。在一个实施例中，共享存储器信息线的I / O节点不在存储器线的目录条目中标识，而是由计数字段表示，计数字段指示有多少个I / O节点共享信息的存储器线。

19. 发明授权

US06640287B2 Scalable multiprocessor system and cache coherence method incorporating invalid-to-dirty requests 失效
公开(公告)号：US06640287B2
公开(公告)日：2003-10-28
申请号：US10042009
申请日：2002-01-07
申请人： Kourosh Gharachorloo , Luiz Andre Barroso , Mosur Kumaraswamy Ravishankar , Robert J. Stets , Daniel J. Scales
发明人： Kourosh Gharachorloo , Luiz Andre Barroso , Mosur Kumaraswamy Ravishankar , Robert J. Stets , Daniel J. Scales
IPC分类号： G06F1200
CPC分类号： G06F12/0826 , G06F12/0828 , G06F2212/621
摘要： An invalid-to-dirty request permits a transition from an invalid memory state to a dirty state without requiring an up-to-date copy of the memory. The present invention is a system for supporting invalid-to-dirty memory transactions in an aggressive cache coherence protocol that minimizes directory entry locking. The nodes of a multiprocessor system each include a protocol engine that is configured to implement a distinct invalidation request that corresponds to an invalid-to-dirty memory transaction. If node O receives this distinct invalidation request while waiting for a response to an outstanding request for exclusive ownership, the protocol engine of node O is configured to treat the distinct invalidation request as applying to the memory line of information that is the subject of the outstanding request for exclusive ownership. Furthermore, if the node O receives a normal invalidation request, while it has an outstanding exclusive request, the invalidation request applies to a previous copy of the memory line of information held by the node N and therefore the protocol engine of node O is configured to ignore the normal invalidation request in this circumstance.

20. 发明授权

US07389389B2 System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system 有权
标题翻译：用于在共享内存多处理器系统中缓存无效请求的有限扇出菊花链的系统和方法
公开(公告)号：US07389389B2
公开(公告)日：2008-06-17
申请号：US10672960
申请日：2003-09-26
申请人： Kourosh Gharachorloo , Luiz A. Barroso , Robert J. Stets, Jr. , Mosur K. Ravishankar , Andreas Nowatzyk
发明人： Kourosh Gharachorloo , Luiz A. Barroso , Robert J. Stets, Jr. , Mosur K. Ravishankar , Andreas Nowatzyk
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F7/00 , G06F15/16
CPC分类号： G06F12/0826 , G06F2212/621 , Y10S707/99952
摘要： A protocol engine is for use in each node of a computer system having a plurality of nodes. Each node includes an interface to a local memory subsystem that stores memory lines of information, a directory, and a memory cache. The directory includes an entry associated with a memory line of information stored in the local memory subsystem. The directory entry includes an identification field for identifying sharer nodes that potentially cache the memory line of information. The identification field has a plurality of bits at associated positions within the identification field. Each respective bit of the identification field is associated with one or more nodes. The protocol engine furthermore sets each bit in the identification field for which the memory line is cached in at least one of the associated nodes. In response to a request for exclusive ownership of a memory line, the protocol engine sends an initial invalidation request to no more than a first predefined number of the nodes associated with set bits in the identification field of the directory entry associated with the memory line.
摘要翻译：协议引擎用于具有多个节点的计算机系统的每个节点。每个节点包括存储信息存储线，目录和存储器高速缓存的本地存储器子系统的接口。目录包括与存储在本地存储器子系统中的信息的存储器线相关联的条目。目录条目包括用于识别可能缓存信息的存储器线的共享者节点的标识字段。识别字段在识别字段内的关联位置具有多个位。识别字段的每个相应位与一个或多个节点相关联。协议引擎还将存储线被高速缓存的标识字段中的每一位设置在相关联的节点中的至少一个中。响应于对存储器线路的独占所有权的请求，协议引擎将初始无效请求发送到与存储器线相关联的目录条目的标识字段中与设置位相关联的不超过第一预定数量的节点。

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