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11. 发明申请

US20070013008A1 Power LDMOS transistor 有权
公开(公告)号：US20070013008A1
公开(公告)日：2007-01-18
申请号：US11180155
申请日：2005-07-13
申请人： Shuming Xu , Jacek Korec
发明人： Shuming Xu , Jacek Korec
IPC分类号： H01L21/337
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/4933 , H01L29/7802 , H01L29/7811 , H01L29/7823
摘要： An LDMOS device comprises a substrate having a first conductivity type and a lightly doped epitaxial layer thereon having an upper surface. Source and drain regions of the first conductivity type are formed in the epitaxial layer along with a channel region of a second conductivity type formed therebetween. A conductive gate is formed over a gate dielectric layer. A drain contact electrically connects the drain region to the substrate, comprising a first trench formed from the upper surface of the epitaxial layer to the substrate and having a side wall along the epitaxial layer, a highly doped region of the first conductivity type formed along the side wall of the first trench, and a drain plug in the first trench adjacent the highly doped region. A source contact is provided and an insulating layer is formed between the conductive gate and the source contact.

12. 发明申请

US20060071270A1 Metal-oxide-semiconductor device having trenched diffusion region and method of forming same 审中-公开
标题翻译：具有沟槽扩散区域的金属氧化物半导体器件及其形成方法
公开(公告)号：US20060071270A1
公开(公告)日：2006-04-06
申请号：US10953018
申请日：2004-09-29
申请人： Muhammed Shibib , Shuming Xu
发明人： Muhammed Shibib , Shuming Xu
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L21/223 , H01L21/2253 , H01L21/266 , H01L29/0653 , H01L29/0657 , H01L29/0886 , H01L29/1037 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.
摘要翻译： MOS器件包括第一导电类型的半导体层和形成在半导体层中的靠近半导体层的上表面的第二导电类型的第一和第二源极/漏极区域。第一和第二源极/漏极区域相对于彼此间隔开。至少部分地在第一和第二源极/漏极区之间形成栅极，并与半导体层电隔离。第一和第二源极/漏极区域中的至少一个被配置为具有基本上大于半导体层和给定源极/漏极区域之间的结的宽度的有效宽度。

13. 发明申请

US20050285189A1 Graded conductive structure for use in a metal-oxide-semiconductor device 有权
标题翻译：用于金属氧化物半导体器件的分级导电结构
公开(公告)号：US20050285189A1
公开(公告)日：2005-12-29
申请号：US10878857
申请日：2004-06-28
申请人： Muhammed Shibib , Shuming Xu
发明人： Muhammed Shibib , Shuming Xu
IPC分类号： H01L21/336 , H01L29/08 , H01L29/40 , H01L29/417 , H01L29/76 , H01L29/78
CPC分类号： H01L29/7816 , H01L29/0847 , H01L29/402 , H01L29/404 , H01L29/4175 , H01L29/41758 , H01L29/41775 , H01L29/66659 , H01L29/7802 , H01L29/7835
摘要： An MOS device comprises a semiconductor layer of a first conductivity type and source and drain regions of a second conductivity type formed in the semiconductor layer, the source and drain regions being spaced apart from one another. A drift region is formed in the semiconductor layer proximate an upper surface of the semiconductor layer and between the source and drain regions, and a insulating layer is formed on the semiconductor layer above at least a portion of the drift region. A gate is formed on the insulating layer and at least partially between the source and drift regions. The MOS device further includes a conductive structure comprising a first end formed on the insulating layer and spaced apart from the gate, and a second end formed on the insulating layer and extending laterally toward the drain region above at least a portion of the drift region. The conductive structure is configured such that a thickness of the insulating layer under the second end of the conductive structure increases as the second end extends toward the drain region.
摘要翻译： MOS器件包括第一导电类型的半导体层和形成在半导体层中的第二导电类型的源区和漏区，源极和漏极彼此间隔开。在半导体层中，靠近半导体层的上表面并且在源极和漏极区之间形成漂移区，并且在漂移区的至少一部分上方的半导体层上形成绝缘层。栅极形成在绝缘层上并且至少部分地在源极和漂移区域之间。 MOS器件还包括导电结构，该导电结构包括形成在绝缘层上并与栅极隔开的第一端，以及形成在绝缘层上并在漂移区的至少一部分上方向漏极区横向延伸的第二端。导电结构被构造成使得当导电结构的第二端下方的绝缘层的厚度随着第二端向漏极区延伸而增加。

14. 发明授权

US08722503B2 Capacitors and methods of forming 有权
标题翻译：电容器和成型方法
公开(公告)号：US08722503B2
公开(公告)日：2014-05-13
申请号：US13184854
申请日：2011-07-18
申请人： Jacek Korec , Shuming Xu , Jun Wang , Boyi Yang
发明人： Jacek Korec , Shuming Xu , Jun Wang , Boyi Yang
IPC分类号： H01L21/20
CPC分类号： H01L29/945 , H01L29/66181
摘要： Capacitors and methods of forming semiconductor device capacitors are disclosed. Trenches are formed to define a capacitor bottom plate in a doped upper region of a semiconductor substrate, a dielectric layer is formed conformally over the substrate within the trenches, and a polysilicon layer is formed over the dielectric layer to define a capacitor top plate. A guard ring region of opposite conductivity and peripheral recessed areas may be added to avoid electric field crowding. A central substrate of lower doping concentration may be provided to provide a resistor in series below the capacitor bottom plate. A series resistor may also be provided in a resistivity region of the polysilicon layer laterally extending from the trenched area region. Contact for the capacitor bottom plate may be made through a contact layer formed on a bottom of the substrate. A top contact may be formed laterally spaced from the trenched area by patterning laterally extended portions of one or more of the dielectric, polysilicon and top metal contact layers.
摘要翻译：公开了形成半导体器件电容器的电容器和方法。形成沟槽以在半导体衬底的掺杂上部区域中限定电容器底板，电介质层在沟槽内的衬底上共形地形成，并且在电介质层上形成多晶硅层以限定电容器顶板。可以添加相反导电性和周边凹陷区域的保护环区域，以避免电场拥挤。可以提供较低掺杂浓度的中心衬底以在电容器底板下方串联提供串联的电阻器。也可以在从沟槽区域侧向延伸的多晶硅层的电阻率区域中提供串联电阻器。电容器底板的接触可以通过形成在基板的底部上的接触层制成。可以通过对电介质，多晶硅和顶部金属接触层中的一个或多个的横向延伸部分进行图案来形成顶部接触件与沟槽区域横向间隔开。

15. 发明授权

US08547162B2 Integration of MOSFETs in a source-down configuration 有权
标题翻译：将MOSFET集成在降压配置中
公开(公告)号：US08547162B2
公开(公告)日：2013-10-01
申请号：US12964527
申请日：2010-12-09
申请人： Jacek Korec , Christopher B. Kocon , Shuming Xu
发明人： Jacek Korec , Christopher B. Kocon , Shuming Xu
IPC分类号： H03K17/687
CPC分类号： H01L27/088 , H01L27/0629 , H03K17/04123 , H03K17/687
摘要： An output stage for a switched mode power supply has a high-side switch having a first power FET and a first speed-up FET monolithically integrated onto a first die. A low-side switch has a second power FET and a second speed-up FET monolithically integrated onto a second die. A semiconductor device has the power FET and the speed-up FET monolithically integrated in a “source-down” configuration. A method of operating an output stage of a switched mode power supply alternately turns on and off a high-side and a low-side switch and drives at least one of the switches with a speed-up FET monolithically integrated with the switch.
摘要翻译：用于开关模式电源的输出级具有高侧开关，其具有单片集成到第一管芯上的第一功率FET和第一加速FET。低侧开关具有单片集成到第二管芯上的第二功率FET和第二加速FET。半导体器件具有功率FET和加速FET，其以“下降”配置为单位集成。操作开关式电源的输出级的方法交替地接通和断开高侧和低侧开关，并且通过与开关单片集成的加速FET来驱动至少一个开关。

16. 发明申请

US20120175702A1 METAL-OXIDE-SEMICONDUCTOR DEVICE HAVING TRENCHED DIFFUSION REGION AND METHOD OF FORMING SAME 有权
标题翻译：具有扩张扩张区域的金属氧化物半导体器件及其形成方法
公开(公告)号：US20120175702A1
公开(公告)日：2012-07-12
申请号：US13428540
申请日：2012-03-23
申请人： Muhammed Ayman Shibib , Shuming Xu
发明人： Muhammed Ayman Shibib , Shuming Xu
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L21/223 , H01L21/2253 , H01L21/266 , H01L29/0653 , H01L29/0657 , H01L29/0886 , H01L29/1037 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.
摘要翻译： MOS器件包括第一导电类型的半导体层和形成在半导体层中的靠近半导体层的上表面的第二导电类型的第一和第二源极/漏极区域。第一和第二源极/漏极区域相对于彼此间隔开。至少部分地在第一和第二源极/漏极区之间形成栅极，并与半导体层电隔离。第一和第二源极/漏极区域中的至少一个被配置为具有基本上大于半导体层和给定源极/漏极区域之间的结的宽度的有效宽度。

17. 发明申请

US20110148506A1 INTEGRATION OF MOSFETS IN A SOURCE-DOWN CONFIGURATION 有权
标题翻译： MOSFET在SOURCE-DOWN配置中的集成
公开(公告)号：US20110148506A1
公开(公告)日：2011-06-23
申请号：US12964527
申请日：2010-12-09
申请人： Jacek Korec , Christopher B. Kocon , Shuming Xu
发明人： Jacek Korec , Christopher B. Kocon , Shuming Xu
IPC分类号： H03K17/687 , H01L29/66
CPC分类号： H01L27/088 , H01L27/0629 , H03K17/04123 , H03K17/687
摘要： An output stage for a switched mode power supply has a high-side switch having a first power FET and a first speed-up FET monolithically integrated onto a first die. A low-side switch has a second power FET and a second speed-up FET monolithically integrated onto a second die. A semiconductor device has the power FET and the speed-up FET monolithically integrated in a “source-down” configuration. A method of operating an output stage of a switched mode power supply alternately turns on and off a high-side and a low-side switch and drives at least one of the switches with a speed-up FET monolithically integrated with the switch.
摘要翻译：用于开关模式电源的输出级具有高侧开关，其具有单片集成到第一管芯上的第一功率FET和第一加速FET。低侧开关具有单片集成到第二管芯上的第二功率FET和第二加速FET。半导体器件具有功率FET和加速FET，其以“下降”配置为单位集成。操作开关式电源的输出级的方法交替地接通和断开高侧和低侧开关，并且通过与开关单片集成的加速FET来驱动至少一个开关。

18. 发明申请

US20110148376A1 MOSFET WITH GATE PULL-DOWN 审中-公开
标题翻译：具有门盖的MOSFET
公开(公告)号：US20110148376A1
公开(公告)日：2011-06-23
申请号：US12964484
申请日：2010-12-09
申请人： Shuming Xu , Jacek Korec , Osvaldo J. Lopez
发明人： Shuming Xu , Jacek Korec , Osvaldo J. Lopez
IPC分类号： G05F1/00 , H03K17/687
CPC分类号： H03K17/165 , H03K17/687
摘要： A MOSFET main switch transistor has a pull-down FET coupled between a drain thereof and the gate of the main switch transistor. A gate of the pull-down FET is coupled to the drain of the main switch transistor by a capacitor and is connected to a source thereof by a resistor. The pull-down FET is operated by capacitive coupling to the voltage drop across the main switch and can be used to hold the gate of the main switch transistor at or near its source potential to avoid or reduce unintentional turn-on of the main switch transistor by the Miller effect.
摘要翻译： MOSFET主开关晶体管具有耦合在其漏极和主开关晶体管的栅极之间的下拉FET。下拉式FET的栅极通过电容器耦合到主开关晶体管的漏极，并通过电阻器与源极连接。下拉式FET通过与主开关两端的电压耦合的电容耦合来操作，并可用于将主开关晶体管的栅极保持在其源极电位处或其附近，以避免或减少主开关晶体管的无意开启由米勒效应。

19. 发明授权

US07745846B2 LDMOS integrated Schottky diode 有权
标题翻译： LDMOS集成肖特基二极管
公开(公告)号：US07745846B2
公开(公告)日：2010-06-29
申请号：US12014581
申请日：2008-01-15
申请人： Jacek Korec , Shuming Xu , Christopher Boguslaw Kocon
发明人： Jacek Korec , Shuming Xu , Christopher Boguslaw Kocon
IPC分类号： H01L31/111 , H01L21/28
CPC分类号： H01L27/0727 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/40 , H01L29/41741 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/4933 , H01L29/7806 , H01L29/782 , H01L29/872
摘要： A semiconductor device includes a substrate having a first conductivity type and a semiconductor layer formed over the substrate and having lower and upper surfaces. A laterally diffused metal-oxide-semiconductor (LDMOS) transistor device is formed over the substrate and includes a source region of the first conductivity type and a drain extension region of the first conductivity type formed in the semiconductor layer proximate the upper surface of the semiconductor layer, and a drain contact electrically connecting the drain extension region to the substrate. A Schottky diode is formed over the substrate and includes at least one doped region of the first conductivity type formed in the semiconductor layer proximate to the upper surface, an anode contact forming a Schottky barrier with the at least one doped region, and a cathode contact laterally spaced from the anode contact and electrically connecting at least one doped region to the substrate.
摘要翻译：半导体器件包括具有第一导电类型的衬底和形成在衬底上并具有下表面和上表面的半导体层。横向扩散的金属氧化物半导体（LDMOS）晶体管器件形成在衬底上，并且包括第一导电类型的源极区域和形成在靠近半导体的上表面的半导体层中的第一导电类型的漏极延伸区域以及将漏极延伸区域与衬底电连接的漏极接触。肖特基二极管形成在衬底之上，并且包括形成在靠近上表面的半导体层中的至少一个第一导电类型的掺杂区域，形成具有至少一个掺杂区域的肖特基势垒的阳极接触器和阴极接触器与阳极接触件横向间隔开并将至少一个掺杂区域电连接到衬底。

20. 发明授权

US07560808B2 Chip scale power LDMOS device 有权
标题翻译：芯片级功率LDMOS器件
公开(公告)号：US07560808B2
公开(公告)日：2009-07-14
申请号：US11254482
申请日：2005-10-19
申请人： Jacek Korec , Shuming Xu , Wenhua Dai
发明人： Jacek Korec , Shuming Xu , Wenhua Dai
IPC分类号： H01L29/76
CPC分类号： H01L24/13 , H01L24/14 , H01L29/0653 , H01L29/0847 , H01L29/0873 , H01L29/0878 , H01L29/0882 , H01L29/4175 , H01L29/41766 , H01L29/4933 , H01L29/7816 , H01L29/7835 , H01L2224/05001 , H01L2224/13 , H01L2224/13028 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/014 , H01L2924/12036 , H01L2924/1306 , H01L2924/13091 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： A semiconductor device includes at least one macro-cell device, the macro-cell device comprising a plurality of LDMOS devices. A first conductive layer is formed over the substrate, the first conductive layer providing source and drain contacts for the macro-cell device. A first isolation layer is formed over the first conductive layer and a second conductive layer is formed over the first isolation layer, the second conductive layer forming a drain bus and a source bus, wherein the buses are electrically coupled to the contacts through the first isolation layer. A second isolation layer is formed over the second conductive layer and insulates the source bus from the drain bus. A plurality of conductive bumps are formed over the second isolation layer, at least one of the conductive bumps directly contacting the drain bus and at least one of the conductive bumps directly contacting the source bus through the second isolation layer.
摘要翻译：半导体器件包括至少一个宏小区设备，该宏小区设备包括多个LDMOS设备。第一导电层形成在衬底上，第一导电层提供用于宏电池器件的源极和漏极触点。在第一导电层上形成第一隔离层，在第一隔离层上形成第二导电层，第二导电层形成漏极总线和源极总线，其中总线通过第一隔离电耦合到触点层。在第二导电层上形成第二隔离层，并将源极总线与漏极母线绝缘。多个导电凸块形成在第二隔离层上方，至少一个导电凸块直接接触漏极母线和至少一个导电凸块直接通过第二隔离层与源极总线接触。

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