专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20070108554A1 De-coupling capacitors produced by utilizing dummy conductive structures integrated circuits 审中-公开
公开(公告)号：US20070108554A1
公开(公告)日：2007-05-17
申请号：US11650028
申请日：2007-01-05
申请人： Cliff Hou , Lee-Chung Lu , Chia-Lin Cheng
发明人： Cliff Hou , Lee-Chung Lu , Chia-Lin Cheng
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A de-coupling capacitor module using dummy conductive elements in an integrated circuit is disclosed. The de-coupling module comprises at least one circuit module having one or more active nodes, and at least one dummy conductive element unconnected to any active node, and separated from a high voltage conductor or a low voltage conductor by an insulation region to provide a de-coupling capacitance.

12. 发明申请

US20060238220A1 Method of using mixed multi-Vt devices in a cell-based design 有权
标题翻译：在基于单元的设计中使用混合多Vt设备的方法
公开(公告)号：US20060238220A1
公开(公告)日：2006-10-26
申请号：US11111281
申请日：2005-04-20
申请人： Shine Chung , Cliff Hou , Mark Chen , Lee-Chung Lu
发明人： Shine Chung , Cliff Hou , Mark Chen , Lee-Chung Lu
IPC分类号： H03K19/0175
CPC分类号： G06F17/505
摘要： A method is disclosed for utilizing mixed low threshold voltage (low-Vt) and high threshold voltage (high-Vt) devices in a cell-based design such that a tradeoff of both the circuit speed and power performance may be achieved. Using cells having non-uniform threshold devices for designing circuit, the speed or/and power optimization is comparable to fully custom designs.
摘要翻译：公开了一种在基于单元的设计中利用混合的低阈值电压（低Vt）和高阈值电压（高Vt）装置的方法，从而可以实现电路速度和功率性能的折衷。使用具有不均匀阈值器件的电池来设计电路，速度或/和功率优化与完全定制的设计相当。

13. 发明申请

US20060067032A1 De-coupling capacitors produced by utilizing dummy conductive structures integrated circuits 有权
标题翻译：通过利用虚拟导电结构集成电路产生的去耦电容器
公开(公告)号：US20060067032A1
公开(公告)日：2006-03-30
申请号：US10952259
申请日：2004-09-27
申请人： Cliff Hou , Lee-Chung Lu , Chia-Lin Cheng
发明人： Cliff Hou , Lee-Chung Lu , Chia-Lin Cheng
IPC分类号： H01G4/228
CPC分类号： H01L23/5223 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A de-coupling capacitor module using dummy conductive elements in an integrated circuit is disclosed. The de-coupling module comprises at least one circuit module having one or more active nodes, and at least one dummy conductive element unconnected to any active node, and separated from a high voltage conductor or a low voltage conductor by an insulation region to provide a de-coupling capacitance.
摘要翻译：公开了一种在集成电路中使用虚设导电元件的去耦合电容器模块。解耦模块包括具有一个或多个有源节点的至少一个电路模块和未连接到任何有源节点的至少一个虚拟导电元件，并且通过绝缘区域与高压导体或低压导体分离，以提供去耦合电容。

14. 发明申请

US20050242375A1 Very fine-grain voltage island integrated circuit 有权
标题翻译：非常细晶电压岛集成电路
公开(公告)号：US20050242375A1
公开(公告)日：2005-11-03
申请号：US11029267
申请日：2005-01-05
申请人： Cliff Hou , Li-Chun Tien , Ching-Hao Shaw , Wan-Pin Yu , Chia-Lin Cheng , Lee-Chung Lu
发明人： Cliff Hou , Li-Chun Tien , Ching-Hao Shaw , Wan-Pin Yu , Chia-Lin Cheng , Lee-Chung Lu
IPC分类号： H01L21/822 , G06F1/18 , G11C5/06 , G11C5/14 , H01L21/82 , H01L23/528 , H01L27/00 , H01L27/04 , H01L27/10 , H01L29/73 , H01L29/739
CPC分类号： G06F1/189 , G11C5/063 , G11C5/14 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： Methods of supplying voltages to integrated circuits are provided. A high voltage VddH and/or a low voltage VddL can be supplied to a filler cell and routed to other cells. Each of the VddH and VddL is carried by one of a first voltage supply wire and a second voltage supply wire. A voltage routing wire routes desired voltage(s) to a filler cell. The first and the second voltage supply wires are preferably formed parallel to the voltage routing wire with their edges substantially aligned to the edges of the voltage routing wire. Vias are made to route the desire voltage. Also preferably, the first voltage supply wire is an M1 wire formed outside the filler cell while the second voltage supply wire is an M2 wire formed inside the filler cell.
摘要翻译：提供向集成电路供电的方法。可以将高电压VddH和/或低电压VddL提供给填充电池并且路由到其它电池。 VddH和VddL中的每一个由第一电压供给线和第二电压供给线之一承载。电压布线将期望的电压传送到填充电池。第一和第二电压电源线优选地与电压布线相平行地形成，其边缘基本上对准电压布线的边缘。使通孔作为路由期望电压。还优选地，第一电压供给线是形成在填充单元外部的M 1线，而第二电压供给线是形成在填充单元内的M 2线。

15. 发明申请

US20050102643A1 Methodology to optimize hierarchical clock skew by clock delay compensation 失效
标题翻译：通过时钟延迟补偿优化分层时钟偏移的方法
公开(公告)号：US20050102643A1
公开(公告)日：2005-05-12
申请号：US10706380
申请日：2003-11-12
申请人： Cliff Hou , Chia-Lin Cheng , Lee-Chung Lu
发明人： Cliff Hou , Chia-Lin Cheng , Lee-Chung Lu
IPC分类号： G06F1/10 , G06F9/45 , G06F17/50
CPC分类号： G06F17/5045 , G06F1/10
摘要： A method for synthesizing a clock distribution system within an integrated circuit for compensating for clock skew within a global or top level clock distribution network begins with allocating at least one delaying circuit within each of functional circuits of the integrated circuit. An intra-functional clock distribution network is fabricated within each of the functional circuits. Once the intra-functional clock distribution network is fabricated, an inter-functional clock distribution network is constructed between each of the functional circuits. A clock skew for the inter-functional clock distribution network is determined. The clock skew is then compensated by inserting the delaying circuit at a terminal of the inter-function clock distribution network where each of the functional circuits is connected to the inter-functional clock distribution network.
摘要翻译：一种用于在集成电路内合成用于补偿全局或顶级时钟分配网络内的时钟偏差的时钟分配系统的方法是从在集成电路的每个功能电路中分配至少一个延迟电路开始。在每个功能电路内制造功能内的时钟分配网络。一旦制造了功能性时钟分配网络，则在每个功能电路之间构造一个功能间时钟分配网络。确定功能间时钟分配网络的时钟偏移。然后通过将延迟电路插入到功能间时钟分配网络的每个功能电路连接到功能间时钟分配网络的终端来补偿时钟偏移。

16. 发明授权

US06797999B2 Flexible routing channels among vias 有权
标题翻译：通孔之间灵活的路由通道
公开(公告)号：US06797999B2
公开(公告)日：2004-09-28
申请号：US10165336
申请日：2002-06-07
申请人： Cliff Hou , Lee-Chung Lu , Chia-Lin Cheng
发明人： Cliff Hou , Lee-Chung Lu , Chia-Lin Cheng
IPC分类号： H01L2710
CPC分类号： H01L23/525 , G06F17/5077 , H01L2924/0002 , H01L2924/00
摘要： Flexible routing channels among vias is disclosed. A semiconductor device of one embodiment includes a number of metal layers, a number of dielectric layers, a number of via holes, and a number of routing channels. The metal layers are organized along a vertical axis. The dielectric layers are alternatively positioned relative to the metal layers. The via holes are situated within the dielectric layers and electrically connect a lower layer of the metal layers to an upper layer of the metal layers. The routing channels are situated within the metal layers and provide for electrical routing through the device along at least one of two horizontal axes of a horizontal plane perpendicular to the vertical axis.
摘要翻译：公开了通孔之间的柔性路由通道。一个实施例的半导体器件包括多个金属层，多个电介质层，多个通孔和多个布线通道。金属层沿垂直轴组织。电介质层相对于金属层交替定位。通孔位于电介质层内，并将金属层的下层电连接到金属层的上层。路由通道位于金属层内，并且沿垂直于垂直轴线的水平面的两个水平轴线中的至少一个水平轴提供穿过该装置的电路。

17. 发明授权

US07793130B2 Mother/daughter switch design with self power-up control 有权
标题翻译：母/子开关设计具有自上电控制功能
公开(公告)号：US07793130B2
公开(公告)日：2010-09-07
申请号：US11789721
申请日：2007-04-24
申请人： Shih-Hsien Yang , Chung-Hsing Wang , Lee-Chung Lu , Chun-Hui Tai , Cliff Hou
发明人： Shih-Hsien Yang , Chung-Hsing Wang , Lee-Chung Lu , Chun-Hui Tai , Cliff Hou
IPC分类号： G06F1/26
CPC分类号： G06F1/3203
摘要： System and method for providing power to integrated circuitry with good power-on responsive time and reduced power-on transient glitches. A preferred embodiment comprises a daughter switch coupled to a circuit block, a first control circuit coupled to the daughter circuit, a second control circuit coupled to the first control circuit, and a mother circuit coupled to the circuit block and to the second control circuit. After the daughter switch is turned on by a control signal, the mother switch is not turned on until the daughter switch has discharged (charged) the voltage potential across power rails of the mother circuit to a point where glitches are minimized. The second control circuit turns on the mother circuit when the reduced voltage potential is reached, with a signal produced by the first control circuit reflects the voltage potential. Furthermore, a bypass circuit can be used to reduce leakage current.
摘要翻译：为集成电路提供电源的系统和方法具有良好的上电响应时间和减少的上电瞬态毛刺。优选实施例包括耦合到电路块的子开关，耦合到子电路的第一控制电路，耦合到第一控制电路的第二控制电路和耦合到电路块和第二控制电路的母电路。在通过控制信号接通子开关之后，母开关直到子开关已经将母电路的电源轨上的电压放电（充电）到毛刺最小化的位置为止。当达到降低的电压电位时，第二控制电路接通母电路，由第一控制电路产生的信号反映电压电位。此外，可以使用旁路电路来减少泄漏电流。

18. 发明申请

US20080229259A1 Design flow for shrinking circuits having non-shrinkable IP layout 有权
标题翻译：具有不可收缩IP布局的收缩电路的设计流程
公开(公告)号：US20080229259A1
公开(公告)日：2008-09-18
申请号：US11807640
申请日：2007-05-30
申请人： Chung-Hsing Wang , Lee-Chung Lu , Cliff Hou , Lie-Szu Juang
发明人： Chung-Hsing Wang , Lee-Chung Lu , Cliff Hou , Lie-Szu Juang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： A method for processing an integrated circuit is provided. The method includes providing a first integrated circuit having a first scale, wherein the first integrated circuit comprises a shrinkable circuit comprising a first intellectual property (IP) layout, and a non-shrinkable circuit comprising a second IP layout; and generating a second integrated circuit having a second scale smaller than the first scale. The step of generating the second integrated circuit includes shrinking the shrinkable integrated circuit to the second scale. The method further includes merging the second IP layout with the non-shrinkable circuit to generate a final integrated circuit.
摘要翻译：提供了一种用于处理集成电路的方法。该方法包括提供具有第一刻度的第一集成电路，其中第一集成电路包括包含第一知识产权（IP）布局的可收缩电路和包括第二IP布局的不可收缩电路; 以及生成具有小于所述第一刻度的第二刻度的第二集成电路。产生第二集成电路的步骤包括将可收缩集成电路收缩到第二刻度。该方法还包括将第二IP布局与不可收缩电路合并以产生最终集成电路。

19. 发明授权

US07017132B2 Methodology to optimize hierarchical clock skew by clock delay compensation 失效
标题翻译：通过时钟延迟补偿优化分层时钟偏移的方法
公开(公告)号：US07017132B2
公开(公告)日：2006-03-21
申请号：US10706380
申请日：2003-11-12
申请人： Cliff Hou , Chia-Lin Cheng , Lee-Chung Lu
发明人： Cliff Hou , Chia-Lin Cheng , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F1/10
摘要： A method for synthesizing a clock distribution system within an integrated circuit for compensating for clock skew within a global or top level clock distribution network begins with allocating at least one delaying circuit within each of functional circuits of the integrated circuit. An intra-functional clock distribution network is fabricated within each of the functional circuits. Once the intra-functional clock distribution network is fabricated, an inter-functional clock distribution network is constructed between each of the functional circuits. A clock skew for the inter-functional clock distribution network is determined. The clock skew is then compensated by inserting the delaying circuit at a terminal of the inter-function clock distribution network where each of the functional circuits is connected to the inter-functional clock distribution network.
摘要翻译：一种用于在集成电路内合成用于补偿全局或顶级时钟分配网络内的时钟偏差的时钟分配系统的方法是从在集成电路的每个功能电路中分配至少一个延迟电路开始。在每个功能电路内制造功能内的时钟分配网络。一旦制造了功能性时钟分配网络，则在每个功能电路之间构造一个功能间时钟分配网络。确定功能间时钟分配网络的时钟偏移。然后通过将延迟电路插入到功能间时钟分配网络的每个功能电路连接到功能间时钟分配网络的终端来补偿时钟偏移。

20. 发明授权

US08418111B2 Method and apparatus for achieving multiple patterning technology compliant design layout 有权
标题翻译：用于实现多种图案化技术兼容的设计布局的方法和装置
公开(公告)号：US08418111B2
公开(公告)日：2013-04-09
申请号：US12953661
申请日：2010-11-24
申请人： Huang-Yu Chen , Fang-Yu Fan , Yuan-Te Hou , Lee-Chung Lu , Ru-Gun Liu , Ken-Hsien Hsieh , Lee Fung Song , Wen-Chun Huang , Li-Chun Tien
发明人： Huang-Yu Chen , Fang-Yu Fan , Yuan-Te Hou , Lee-Chung Lu , Ru-Gun Liu , Ken-Hsien Hsieh , Lee Fung Song , Wen-Chun Huang , Li-Chun Tien
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G03F7/70433 , G03F7/70466
摘要： A method and apparatus for achieving multiple patterning compliant technology design layouts is provided. An exemplary method includes providing a routing grid having routing tracks; designating each of the routing tracks one of at least two colors; applying a pattern layout having a plurality of features to the routing grid, wherein each of the plurality of features corresponds with at least one routing track; and applying a feature splitting constraint to determine whether the pattern layout is a multiple patterning compliant layout. If the pattern layout is not a multiple patterning compliant layout, the pattern layout may be modified until a multiple patterning compliant layout is achieved. If the pattern layout is a multiple patterning compliant layout, the method includes coloring each of the plurality of features based on the color of each feature's corresponding at least one routing track, thereby forming a colored pattern layout, and generating at least two masks with the features of the colored pattern layout. Each mask includes features of a single color.
摘要翻译：提供了一种用于实现多个图案化兼容技术设计布局的方法和装置。示例性方法包括提供具有路由轨迹的路由网格; 指定每个路线轨道至少两种颜色之一; 将具有多个特征的图案布局应用于所述路由网格，其中所述多个特征中的每一个对应于至少一个路由轨道; 以及应用特征分解约束来确定所述图案布局是否是符合多重图案化的布局。如果图案布局不是符合多重图案化的布局，则可以修改图案布局，直到实现多重图案化兼容布局。如果图案布局是符合多重图案化的布局，则该方法包括基于每个特征对应的至少一个路线轨迹的颜色来着色多个特征中的每一个，从而形成彩色图案布局，并且生成至少两个具有彩色图案布局的特点。每个面具都包含单一颜色的特征。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式