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11. 发明申请

US20120064693A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20120064693A1
公开(公告)日：2012-03-15
申请号：US13277261
申请日：2011-10-20
申请人： Kenji Aoyama
发明人： Kenji Aoyama
IPC分类号： H01L45/00
CPC分类号： H01L27/1021 , H01L27/24
摘要： A semiconductor memory device includes a word line interconnect layer having a plurality of word lines extending in a word line direction and a bit line interconnect layer having a plurality of bit lines extending in a bit line direction alternately stacked on a silicon substrate. A variable resistance film is disposed between the word line and the bit line. A first pin diode extending in the word line direction is provided between the word line and the variable resistance film, and a second pin diode extending in the bit line direction is provided between the bit line and the variable resistance film. A region of an upper surface of the pin diode other than an immediately underlying region of the variable resistance film is located lower than the immediately underlying region.
摘要翻译：半导体存储器件包括具有在字线方向上延伸的多个字线的字线互连层和具有交替层叠在硅衬底上的位线方向延伸的多个位线的位线互连层。可变电阻膜设置在字线和位线之间。在字线方向和可变电阻膜之间设置有沿字线方向延伸的第一PIN二极管，并且在位线和可变电阻膜之间设置沿位线方向延伸的第二pin二极管。引脚二极管的上表面的区域不同于可变电阻膜的紧邻下方区域的位置低于紧邻的下方区域。

12. 发明授权

US08071969B2 Semiconductor memory device and method for manufacturing same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08071969B2
公开(公告)日：2011-12-06
申请号：US12491296
申请日：2009-06-25
申请人： Kenji Aoyama
发明人： Kenji Aoyama
IPC分类号： H01L45/00 , G11C11/00
CPC分类号： H01L27/1021 , H01L27/24
摘要： A semiconductor memory device includes a word line interconnect layer having a plurality of word lines extending in a word line direction and a bit line interconnect layer having a plurality of bit lines extending in a bit line direction alternately stacked on a silicon substrate. A variable resistance film is disposed between the word line and the bit line. A first pin diode extending in the word line direction is provided between the word line and the variable resistance film, and a second pin diode extending in the bit line direction is provided between the bit line and the variable resistance film. A region of an upper surface of the pin diode other than an immediately underlying region of the variable resistance film is located lower than the immediately underlying region.
摘要翻译：半导体存储器件包括具有在字线方向上延伸的多个字线的字线互连层和具有交替层叠在硅衬底上的位线方向延伸的多个位线的位线互连层。可变电阻膜设置在字线和位线之间。在字线方向和可变电阻膜之间设置有沿字线方向延伸的第一PIN二极管，并且在位线和可变电阻膜之间设置沿位线方向延伸的第二pin二极管。引脚二极管的上表面的区域不同于可变电阻膜的紧邻下方区域的位置低于紧邻的下方区域。

13. 发明申请

US20110147822A1 Semiconductor memory device and method for manufacturing the same 审中-公开
公开(公告)号：US20110147822A1
公开(公告)日：2011-06-23
申请号：US12929894
申请日：2011-02-23
申请人： Kenji Aoyama , Eiji Ito , Masahiro Kiyotoshi , Tadashi Iguchi , Moto Yabuki
发明人： Kenji Aoyama , Eiji Ito , Masahiro Kiyotoshi , Tadashi Iguchi , Moto Yabuki
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/764 , H01L29/40114 , H01L29/66825
摘要： A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity.

14. 发明授权

US07868376B2 Semiconductor storage device and method for manufacturing the same 失效
公开(公告)号：US07868376B2
公开(公告)日：2011-01-11
申请号：US12354271
申请日：2009-01-15
申请人： Kenji Aoyama , Hisataka Meguro , Satoshi Nagashima
发明人： Kenji Aoyama , Hisataka Meguro , Satoshi Nagashima
IPC分类号： H01L29/792
CPC分类号： H01L21/28247 , H01L21/76229 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side surface of the selection transistor, and a surface of the semiconductor substrate between the word lines, a high-permittivity film formed on the first insulation film, a second insulating film formed so as to cover the upper surface of the word lines and the selection transistor, a first air-gap portion located between the word lines and surrounded by the high-permittivity film and the second insulating film, and a second air-gap portion formed via the first insulating film and the high-permittivity film at a sidewall portion, which opposes the selection transistor, of the word line adjacent to the selection transistor, an upper portion of the second air-gap portion being covered by the second insulating film.

15. 发明申请

US20090206391A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20090206391A1
公开(公告)日：2009-08-20
申请号：US12350658
申请日：2009-01-08
申请人： Kyoko ANDO , Satoshi Nagashima , Kenji Aoyama
发明人： Kyoko ANDO , Satoshi Nagashima , Kenji Aoyama
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/42324 , H01L21/76229 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L29/66825 , H01L29/7883
摘要： A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed on the semiconductor substrate at predetermined intervals, a selecting transistor arranged on each of two sides of each of the plurality of word lines in which a spacing between the selecting transistor and an adjacent one of the word lines is not less than three times a width of each of the word lines, an interlayer insulating film formed to cover upper surfaces of the word lines and selecting transistors, a first cavity portion which is located between each pair of adjacent ones of the word lines and whose upper portion is covered with the interlayer insulating film, a second cavity portion which is formed at a side wall portion of the word line adjacent to each selecting transistor which faces the selecting transistor and whose upper portion is covered with the interlayer insulating film, and a third cavity portion which is formed at a side wall portion of each of the selecting transistors and whose upper portion is covered with the interlayer insulating film.
摘要翻译：半导体存储器件具有半导体衬底，以预定间隔形成在半导体衬底上的多条字线，选择晶体管布置在多个字线中的每一个的两侧中，其中选择晶体管和字线的相邻一方的字线宽度不小于每条字线的宽度的三倍，形成为覆盖字线的上表面并选择晶体管的层间绝缘膜，第一空腔部分位于每对相邻的所述字线中的一个并且其上部被所述层间绝缘膜覆盖;第二空腔部分，形成在所述字线的与所述选择晶体管相对并且其上部被覆盖的相邻的字线的侧壁部分处层间绝缘膜和形成在每个选择晶体管的侧壁部分的第三空腔部分并且其上部被层间绝缘膜覆盖。

16. 发明授权

US08551852B2 Semiconductor memory device and method for manufacturing same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08551852B2
公开(公告)日：2013-10-08
申请号：US13277261
申请日：2011-10-20
申请人： Kenji Aoyama
发明人： Kenji Aoyama
IPC分类号： H01L45/00
CPC分类号： H01L27/1021 , H01L27/24
摘要： A semiconductor memory device includes a word line interconnect layer having a plurality of word lines extending in a word line direction and a bit line interconnect layer having a plurality of bit lines extending in a bit line direction alternately stacked on a silicon substrate. A variable resistance film is disposed between the word line and the bit line. A first pin diode extending in the word line direction is provided between the word line and the variable resistance film, and a second pin diode extending in the bit line direction is provided between the bit line and the variable resistance film. A region of an upper surface of the pin diode other than an immediately underlying region of the variable resistance film is located lower than the immediately underlying region.
摘要翻译：半导体存储器件包括具有在字线方向上延伸的多个字线的字线互连层和具有交替层叠在硅衬底上的位线方向延伸的多个位线的位线互连层。可变电阻膜设置在字线和位线之间。在字线方向和可变电阻膜之间设置有沿字线方向延伸的第一PIN二极管，并且在位线和可变电阻膜之间设置沿位线方向延伸的第二pin二极管。引脚二极管的上表面的区域不同于可变电阻膜的紧邻下方区域的位置低于紧邻的下方区域。

17. 发明授权

US08253199B2 Semiconductor memory device having cavity portions 有权
标题翻译：具有空腔部分的半导体存储器件
公开(公告)号：US08253199B2
公开(公告)日：2012-08-28
申请号：US12350658
申请日：2009-01-08
申请人： Kyoko Ando , Satoshi Nagashima , Kenji Aoyama
发明人： Kyoko Ando , Satoshi Nagashima , Kenji Aoyama
IPC分类号： H01L27/12
CPC分类号： H01L29/42324 , H01L21/76229 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L29/66825 , H01L29/7883
摘要： A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed on the semiconductor substrate at predetermined intervals, a selecting transistor arranged on each of two sides of each of the plurality of word lines in which a spacing between the selecting transistor and an adjacent one of the word lines is not less than three times a width of each of the word lines, an interlayer insulating film formed to cover upper surfaces of the word lines and selecting transistors, a first cavity portion which is located between each pair of adjacent ones of the word lines and whose upper portion is covered with the interlayer insulating film, a second cavity portion which is formed at a side wall portion of the word line adjacent to each selecting transistor which faces the selecting transistor and whose upper portion is covered with the interlayer insulating film, and a third cavity portion which is formed at a side wall portion of each of the selecting transistors and whose upper portion is covered with the interlayer insulating film.
摘要翻译：半导体存储器件具有半导体衬底，以预定间隔形成在半导体衬底上的多条字线，选择晶体管布置在多个字线中的每一个的两侧中，其中选择晶体管和字线的相邻一方的字线宽度不小于每条字线的宽度的三倍，形成为覆盖字线的上表面并选择晶体管的层间绝缘膜，第一空腔部分位于每对相邻的所述字线中的一个并且其上部被所述层间绝缘膜覆盖;第二空腔部分，形成在所述字线的与所述选择晶体管相对并且其上部被覆盖的相邻的字线的侧壁部分处层间绝缘膜和形成在每个选择晶体管的侧壁部分的第三空腔部分并且其上部被层间绝缘膜覆盖。

18. 发明授权

US08053825B2 Stacked gate nonvolatile semiconductor memory and method for manufacturing the same 有权
标题翻译：堆叠式非易失性半导体存储器及其制造方法
公开(公告)号：US08053825B2
公开(公告)日：2011-11-08
申请号：US11927799
申请日：2007-10-30
申请人： Kenji Aoyama , Satoshi Nagashima
发明人： Kenji Aoyama , Satoshi Nagashima
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A stacked gate nonvolatile semiconductor memory includes at least a memory cell transistor and a selective gate transistor which are formed on a semiconductor substrate. The memory cell transistor includes a floating gate made of a semiconductor material below an interlayer insulating layer and a control gate made of a silicide above the interlayer insulating layer. The selective gate transistor includes a semiconductor layer made of the semiconductor material, a silicide layer made of the silicide and a conductive layer made of a conductive material not subject to silicide process which is formed through the interlayer insulating film so as to electrically connect the semiconductor layer and the silicide layer.
摘要翻译：层叠栅极非易失性半导体存储器至少包括形成在半导体衬底上的存储单元晶体管和选择栅极晶体管。存储单元晶体管包括由层间绝缘层下方的半导体材料制成的浮置栅极和由层间绝缘层上方的硅化物制成的控制栅极。选择栅极晶体管包括由半导体材料制成的半导体层，由硅化物制成的硅化物层和由不经过硅化处理的导电材料制成的导电层，该导电层通过层间绝缘膜形成，以将半导体层和硅化物层。

19. 发明授权

US08629528B2 Semiconductor memory device and method for manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08629528B2
公开(公告)日：2014-01-14
申请号：US13557295
申请日：2012-07-25
申请人： Kyoko Ando , Satoshi Nagashima , Kenji Aoyama
发明人： Kyoko Ando , Satoshi Nagashima , Kenji Aoyama
IPC分类号： H01L21/70
CPC分类号： H01L29/42324 , H01L21/76229 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L29/66825 , H01L29/7883
摘要： According to one embodiment, a semiconductor memory device includes a plurality of word lines formed on a semiconductor substrate at predetermined intervals, selecting transistors arranged on at least one side of the plurality of word lines, an interlayer insulating film formed to cover upper surfaces of the word lines and the selecting transistors, a first air gap located between each pair of adjacent ones of the word lines and covered by the interlayer insulating film, a second air gap located at a first side wall portion of a word line adjacent to the selecting transistors covered by the interlayer insulating film, the first side wall portion facing the selecting transistors, and a third air gap located at a second side wall portion of each of the selecting transistors and covered by the interlayer insulating film. The first, second, and third air gaps are filled with air.
摘要翻译：根据一个实施例，半导体存储器件包括以预定间隔形成在半导体衬底上的多个字线，选择排列在多个字线的至少一侧的晶体管，形成为覆盖所述多个字线的上表面的层间绝缘膜字线和选择晶体管，位于每对相邻字线之间并由层间绝缘膜覆盖的第一气隙，位于与选择晶体管相邻的字线的第一侧壁部分处的第二气隙被层间绝缘膜覆盖，面向选择晶体管的第一侧壁部分和位于每个选择晶体管的第二侧壁部分并被层间绝缘膜覆盖的第三气隙。第一，第二和第三气隙充满空气。

20. 发明授权

US08253188B2 Semiconductor storage device and method for manufacturing the same 失效
标题翻译：半导体存储装置及其制造方法
公开(公告)号：US08253188B2
公开(公告)日：2012-08-28
申请号：US12728788
申请日：2010-03-22
申请人： Takeshi Kamigaichi , Satoshi Nagashima , Kenji Aoyama
发明人： Takeshi Kamigaichi , Satoshi Nagashima , Kenji Aoyama
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L27/11529 , H01L27/11519 , H01L27/11526
摘要： A semiconductor storage device includes a semiconductor substrate, a first insulator, a laminated insulator including a second insulator having fixed charges more than those of the first insulator, a single-layer insulator, memory cells between the semiconductor substrate and the first insulator, each memory cells separated from an adjacent memory cell by a cavity portion and including a tunnel insulator, a charge accumulation layer, an insulator, and a control gate electrode, a first selection gate transistor between the semiconductor substrate and the first insulator, a second selection gate transistor between the semiconductor substrate and the first insulator, between one memory cell and the first selection gate transistor, and in contact with the laminated insulator on a first side face on a memory cell side thereof, and a high-voltage peripheral circuit transistor between the semiconductor substrate and the first insulator, and in contact with the single-layer insulator on a side face thereof.
摘要翻译：一种半导体存储装置，包括半导体衬底，第一绝缘体，层叠绝缘体，其包括具有比第一绝缘体的电荷多的固定电荷的第二绝缘体，单层绝缘体，半导体衬底和第一绝缘体之间的存储单元，通过空腔部分从相邻的存储单元分离的单元，包括隧道绝缘体，电荷累积层，绝缘体和控制栅电极，在半导体衬底和第一绝缘体之间的第一选择栅极晶体管，第二选择栅极晶体管在所述半导体衬底和所述第一绝缘体之间，在一个存储单元和所述第一选择栅极晶体管之间，并且与所述层叠绝缘体在其存储单元侧的第一侧面接触;以及所述半导体之间的高压外围电路晶体管基板和第一绝缘体，并与一侧的单层绝缘体接触面对。

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