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11. 发明授权

US07830703B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07830703B2
公开(公告)日：2010-11-09
申请号：US11570037
申请日：2005-05-25
申请人： Koichi Takeda , Masahiro Nomura , Kiyoshi Takeuchi , Hitoshi Wakabayashi , Shigeharu Yamagami , Risho Koh , Koichi Terashima , Katsuhiko Tanaka , Masayasu Tanaka
发明人： Koichi Takeda , Masahiro Nomura , Kiyoshi Takeuchi , Hitoshi Wakabayashi , Shigeharu Yamagami , Risho Koh , Koichi Terashima , Katsuhiko Tanaka , Masayasu Tanaka
IPC分类号： G11C11/00
CPC分类号： H01L27/11 , H01L27/1104 , H01L27/1108 , H01L29/785 , Y10S257/903
摘要： A semiconductor device having SRAM cell units each comprising a pair of a first driving transistor and a second driving transistor, a pair of a first load transistor and a second load transistor, and a pair of a first access transistor and a second access transistor, wherein each of the transistors comprises a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulating film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; and the first and second driving transistors each have a channel width larger than that of at least either each of the load transistors or each of the access transistors.
摘要翻译：一种具有SRAM单元单元的半导体器件，每个SRAM单元包括一对第一驱动晶体管和第二驱动晶体管，一对第一负载晶体管和第二负载晶体管，以及一对第一存取晶体管和第二存取晶体管，其中每个晶体管包括从衬底平面向上突出的半导体层，在半导体层的相对侧上延伸以跨越半导体层的顶部的栅极电极，插入在栅极电极和半导体之间的栅极绝缘膜层，以及形成在半导体层中的一对源极/漏极区域; 并且第一和第二驱动晶体管的沟道宽度均大于至少任一个负载晶体管或每个存取晶体管的沟道宽度。

12. 发明申请

US20080079077A1 Semiconductor Device And Manufacturing Method Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080079077A1
公开(公告)日：2008-04-03
申请号：US11570037
申请日：2005-05-25
申请人： Koichi Takeda , Masahiro Nomura , Kiyoshi Takeuchi , Hitoshi Wakabayashi , Shigeharu Yamagami , Risho Koh , Koichi Terashima , Katsuhiko Tanaka , Masayasu Tanaka
发明人： Koichi Takeda , Masahiro Nomura , Kiyoshi Takeuchi , Hitoshi Wakabayashi , Shigeharu Yamagami , Risho Koh , Koichi Terashima , Katsuhiko Tanaka , Masayasu Tanaka
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L27/11 , H01L27/1104 , H01L27/1108 , H01L29/785 , Y10S257/903
摘要： A semiconductor device having SRAM cell units each comprising a pair of a first driving transistor and a second driving transistor, a pair of a first load transistor and a second load transistor, and a pair of a first access transistor and a second access transistor, wherein each of the transistors comprises a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulating film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; and the first and second driving transistors each have a channel width larger than that of at least either each of the load transistors or each of the access transistors.
摘要翻译：一种具有SRAM单元单元的半导体器件，每个SRAM单元包括一对第一驱动晶体管和第二驱动晶体管，一对第一负载晶体管和第二负载晶体管，以及一对第一存取晶体管和第二存取晶体管，其中每个晶体管包括从衬底平面向上突出的半导体层，在半导体层的相对侧上延伸以跨越半导体层的顶部的栅极电极，插入在栅极电极和半导体之间的栅极绝缘膜层，以及形成在半导体层中的一对源极/漏极区域; 并且第一和第二驱动晶体管的沟道宽度均大于至少任一个负载晶体管或每个存取晶体管的沟道宽度。

13. 发明授权

US07659772B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07659772B2
公开(公告)日：2010-02-09
申请号：US11813502
申请日：2006-01-06
申请人： Masahiro Nomura , Koichi Takeda
发明人： Masahiro Nomura , Koichi Takeda
IPC分类号： G05F1/10
CPC分类号： H03K19/0008
摘要： A semiconductor integrated circuit device includes: a switching current observer for observing a switching current; a leakage current observer for observing a leakage current; a comparator which compares the switching current and the leakage current with each other; a threshold voltage controller for controlling a substrate bias voltage in order to make a ratio of the switching current and the leakage current constant; a delay observer for observing a delay amount; and a power supply voltage controller for controlling a power supply voltage in order to keep the delay amount in a predetermined range. In the semiconductor integrated circuit device, a process which enables the minimization of an operation power is carried out by controlling the threshold voltage to make the ratio of the switching current and the leakage current constant at a given clock frequency and controlling the power supply voltage to guarantee the operating speed.
摘要翻译：一种半导体集成电路器件，包括：用于观察开关电流的开关电流观察器; 用于观察泄漏电流的漏电流观测器; 将开关电流和漏电流进行比较的比较器; 用于控制衬底偏置电压以使开关电流和漏电流的比率恒定的阈值电压控制器; 用于观察延迟量的延迟观察器; 以及用于控制电源电压以便将延迟量保持在预定范围内的电源电压控制器。在半导体集成电路器件中，通过控制阈值电压来实现能够最小化操作功率的处理，以使给定时钟频率下的开关电流和漏电流的比率恒定，并将电源电压控制为保证运行速度。

14. 发明授权

US07446562B2 Programmable semiconductor device 失效
标题翻译：可编程半导体器件
公开(公告)号：US07446562B2
公开(公告)日：2008-11-04
申请号：US11628532
申请日：2005-05-25
申请人： Masahiro Nomura , Koichi Takeda
发明人： Masahiro Nomura , Koichi Takeda
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17748 , H03K19/17736 , H03K19/1778 , H03K19/17792
摘要： A programmable semiconductor device of the invention includes: processing element unit executing a predetermined operation; input/output connection unit acting as a signal input part and/or a signal output part in processing element unit; interconnecting unit, comprised of a plurality of wires, connecting processing element unit via input/output connection unit; bidirectional repeater unit, arranged between the intersection points of interconnecting unit, performing disconnection, or driving interconnecting unit in the forward direction or in the reverse direction; and interconnection connecting unit, arranged at the intersection point, connecting interconnecting unit at the intersection point.
摘要翻译：本发明的可编程半导体器件包括：执行预定操作的处理元件单元; 用作信号输入部分的输入/输出连接单元和/或处理元件单元中的信号输出部分; 由多根电线组成的互连单元，经由输入/输出连接单元连接处理元件单元; 双向中继器单元，布置在互连单元的交点之间，在正向或反向上执行断开或驱动互连单元; 和互连连接单元，布置在交点处，交叉点处连接互连单元。

15. 发明申请

US20060091936A1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20060091936A1
公开(公告)日：2006-05-04
申请号：US11261753
申请日：2005-10-31
申请人： Yoshifumi Ikenaga , Koichi Takeda , Masahiro Nomura
发明人： Yoshifumi Ikenaga , Koichi Takeda , Masahiro Nomura
IPC分类号： H03K3/01
CPC分类号： H03K19/0013 , H01L2924/0002 , H01L2924/00
摘要： A substrate bias is controlled such that a leakage current is minimum. A semiconductor integrated circuit device comprises a leakage detecting circuit which detects a leakage current by using leakage detecting MOSFETs, a control circuit which generates a control signal depending on an output from the leakage detecting circuit, a substrate bias generating circuit which changes a substrate bias depending on the control signal, and a controlled circuit including a MOSFET having the same characteristics as that of each of the leakage detecting MOSFETs. The leakage detecting circuit detects a substrate leakage current which includes as the substrate bias becomes deep and a subthreshold leakage current which decreases as the substrate bias becomes deep. A control signal is transmitted to the substrate bias generating circuit such that the substrate bias is made deep when the substrate leakage current is smaller than the subthreshold leakage current and such that the substrate bias is made shallow when the substrate leakage current is larger than the subthreshold leakage current.
摘要翻译：控制衬底偏置使得漏电流最小。一种半导体集成电路装置，包括利用泄漏检测用MOSFET检测泄漏电流的漏电检测电路，根据来自漏电检测电路的输出产生控制信号的控制电路，将衬底偏置变化的衬底偏置产生电路控制信号的控制电路以及具有与各漏电检测用MOSFET相同特性的MOSFET的受控电路。泄漏检测电路检测衬底偏置变深时包括的衬底漏电流，以及随着衬底偏压变深而减小的亚阈值漏电流。控制信号被传送到衬底偏置产生电路，使得当衬底漏电流小于亚阈值漏电流时衬底偏压变深，并且当衬底泄漏电流大于次阈值时衬底偏置变浅漏电流。

16. 发明授权

US08008659B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US08008659B2
公开(公告)日：2011-08-30
申请号：US11261753
申请日：2005-10-31
申请人： Yoshifumi Ikenaga , Koichi Takeda , Masahiro Nomura
发明人： Yoshifumi Ikenaga , Koichi Takeda , Masahiro Nomura
IPC分类号： H01L23/58 , H01L29/10 , H03K3/01
CPC分类号： H03K19/0013 , H01L2924/0002 , H01L2924/00
摘要： A substrate bias is controlled such that a leakage current is minimum. A semiconductor integrated circuit device comprises a leakage detecting circuit which detects a leakage current by using leakage detecting MOSFETs, a control circuit which generates a control signal depending on an output from the leakage detecting circuit, a substrate bias generating circuit which changes a substrate bias depending on the control signal, and a controlled circuit including a MOSFET having the same characteristics as that of each of the leakage detecting MOSFETs. The leakage detecting circuit detects a substrate leakage current which includes as the substrate bias becomes deep and a subthreshold leakage current which decreases as the substrate bias becomes deep. A control signal is transmitted to the substrate bias generating circuit such that the substrate bias is made deep when the substrate leakage current is smaller than the subthreshold leakage current and such that the substrate bias is made shallow when the substrate leakage current is larger than the subthreshold leakage current.
摘要翻译：控制衬底偏置使得漏电流最小。一种半导体集成电路装置，包括利用泄漏检测用MOSFET检测泄漏电流的漏电检测电路，根据来自漏电检测电路的输出产生控制信号的控制电路，将衬底偏置变化的衬底偏置产生电路控制信号的控制电路以及具有与各漏电检测用MOSFET相同特性的MOSFET的受控电路。泄漏检测电路检测衬底偏置变深时包括的衬底漏电流，以及随着衬底偏压变深而减小的亚阈值漏电流。控制信号被传送到衬底偏置产生电路，使得当衬底漏电流小于亚阈值漏电流时衬底偏压变深，并且当衬底泄漏电流大于次阈值时衬底偏置变浅漏电流。

17. 发明申请

US20080191791A1 Semiconductor Integrated Circuit Device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20080191791A1
公开(公告)日：2008-08-14
申请号：US11813502
申请日：2006-01-06
申请人： Masahiro Nomura , Koichi Takeda
发明人： Masahiro Nomura , Koichi Takeda
IPC分类号： G05F1/10
CPC分类号： H03K19/0008
摘要： A semiconductor integrated circuit device includes: a switching current observer for observing a switching current; a leakage current observer for observing a leakage current; a comparator which compares the switching current and the leakage current with each other; a threshold voltage controller for controlling a substrate bias voltage in order to make a ratio of the switching current and the leakage current constant; a delay observer for observing a delay amount; and a power supply voltage controller for controlling a power supply voltage in order to keep the delay amount in a predetermined range. In the semiconductor integrated circuit device, a process which enables the minimization of an operation power is carried out by controlling the threshold voltage to make the ratio of the switching current and the leakage current constant at a given clock frequency and controlling the power supply voltage to guarantee the operating speed.
摘要翻译：一种半导体集成电路器件，包括：用于观察开关电流的开关电流观察器; 用于观察泄漏电流的漏电流观测器; 将开关电流和漏电流进行比较的比较器; 用于控制衬底偏置电压以使开关电流和漏电流的比率恒定的阈值电压控制器; 用于观察延迟量的延迟观察器; 以及用于控制电源电压以便将延迟量保持在预定范围内的电源电压控制器。在半导体集成电路器件中，通过控制阈值电压来实现能够最小化操作功率的处理，以使给定时钟频率下的开关电流和漏电流的比率恒定，并将电源电压控制为保证运行速度。

18. 发明申请

US20090201063A1 DYNAMIC SEMICONDUCTOR DEVICE 审中-公开
标题翻译：动态半导体器件
公开(公告)号：US20090201063A1
公开(公告)日：2009-08-13
申请号：US12160071
申请日：2006-12-28
申请人： Masahiro Nomura , Yoshifumi Ikenaga , Koichi Takeda
发明人： Masahiro Nomura , Yoshifumi Ikenaga , Koichi Takeda
IPC分类号： H03K3/289
CPC分类号： H03K3/35625 , H03K19/096
摘要： A dynamic semiconductor device is provided with a plurality of master step sections having hatch sections for temporarily storing input data and dynamic gate sections; a plurality of slave step sections, which are alternately connected with master step sections and provided with dynamic gate sections or with latch sections and dynamic gate sections; and a timing signal generating section for generating a signal for controlling operation of the master step sections and the slave step sections. The timing signal generating section supplies the latch sections with signals for storing data of the previous step before the data is erased.
摘要翻译：动态半导体器件具有多个具有用于临时存储输入数据和动态门部分的开关部分的主步进部分; 多个从步骤部分，与主阶段部分交替地连接并设置有动态门部分或者具有锁存部分和动态门部分; 以及定时信号产生部分，用于产生用于控制主步进部分和从步进部分的操作的信号。定时信号生成部分在锁存部分提供用于存储数据被擦除之前的前一步骤的数据的信号。

19. 发明申请

US20070247188A1 Programmable Semiconductor Device 失效
标题翻译：可编程半导体器件
公开(公告)号：US20070247188A1
公开(公告)日：2007-10-25
申请号：US11628532
申请日：2005-05-25
申请人： Masahiro Nomura , Koichi Takeda
发明人： Masahiro Nomura , Koichi Takeda
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , H03K19/17736 , H03K19/1778 , H03K19/17792
摘要： A programmable semiconductor device of the invention includes: processing element unit executing a predetermined operation; input/output connection unit acting as a signal input part and/or a signal output part in processing element unit; interconnecting unit, comprised of a plurality of wires, connecting processing element unit via input/output connection unit; bidirectional repeater unit, arranged between the intersection points of interconnecting unit, performing disconnection, or driving interconnecting unit in the forward direction or in the reverse direction; and interconnection connecting unit, arranged at the intersection point, connecting interconnecting unit at the intersection point.
摘要翻译：本发明的可编程半导体器件包括：执行预定操作的处理元件单元; 用作信号输入部分的输入/输出连接单元和/或处理元件单元中的信号输出部分; 由多根电线组成的互连单元，经由输入/输出连接单元连接处理元件单元; 双向中继器单元，布置在互连单元的交点之间，在正向或反向上执行断开或驱动互连单元; 和互连连接单元，布置在交点处，交叉点处连接互连单元。

20. 发明申请

US20130165482A1 PEST CONTROL AGENT 有权
标题翻译：虫控制剂
公开(公告)号：US20130165482A1
公开(公告)日：2013-06-27
申请号：US13814753
申请日：2011-08-26
申请人： Shinzo Kagabu , Masaaki Mitomi , Shigeki Kitsuda , Ryo Horikoshi , Masahiro Nomura , Yasumichi Onozaki
发明人： Shinzo Kagabu , Masaaki Mitomi , Shigeki Kitsuda , Ryo Horikoshi , Masahiro Nomura , Yasumichi Onozaki
IPC分类号： C07D211/98 , A01N43/40
CPC分类号： A01N43/40 , A01N37/18 , A01N43/50 , A01N43/54 , A01N43/58 , A01N43/78 , A01N47/02 , A01N47/12 , A01N47/40 , A01N57/32 , C07C233/05 , C07C233/12 , C07C261/04 , C07C271/12 , C07C311/09 , C07D211/98 , C07D213/36 , C07D213/40 , C07D213/42 , C07D213/61 , C07D213/75 , C07D237/08 , C07D277/32 , C07D333/20 , C07D401/06 , C07D401/12 , C07D405/12 , C07D417/12 , C07F9/58
摘要： Specific amine derivatives have been found to possess excellent activities as pest control agents.
摘要翻译：已发现特定的胺衍生物作为害虫控制剂具有优良的活性。

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