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11. 发明授权

US06286007B1 Method and system for efficiently storing and viewing data in a database 失效
标题翻译：在数据库中高效地存储和查看数据的方法和系统
公开(公告)号：US06286007B1
公开(公告)日：2001-09-04
申请号：US09170901
申请日：1998-10-13
申请人： Clinton Frederick Miller , Paul Gerard Villarrubia
发明人： Clinton Frederick Miller , Paul Gerard Villarrubia
IPC分类号： G06F900
CPC分类号： G06F17/30958 , Y10S707/99936 , Y10S707/99942
摘要： A method and system are disclosed for efficiently storing and viewing data in a database. Data is stored in a nested data model which includes a plurality of nodes. A plurality of edges connect the plurality of nodes. Each edge has a unique edge name. A plurality of instances of data objects are associated with the nested data model. Each instance is associated with one of the edges such that the instance is also associated with that edge's name. An instance ordinal is associated with each instance which represents the number of times the edge associated with each instance is encountered during a traversal of the nested data model. The data stored utilizing the nested data model is accessed utilizing the instance ordinal and edge name associated with each of the plurality of instances, such that the data is accessed as being flat without flattening the nested data model.
摘要翻译：公开了一种用于在数据库中有效地存储和查看数据的方法和系统。数据被存储在包括多个节点的嵌套数据模型中。多个边缘连接多个节点。每个边缘都有一个独特的边缘名称。数据对象的多个实例与嵌套数据模型相关联。每个实例与其中一个边缘相关联，使得实例也与该边缘的名称相关联。实例序数与每个实例相关联，表示在遍历嵌套数据模型期间遇到与每个实例相关联的边的次数。使用嵌套数据模型存储的数据使用与多个实例中的每个实例相关联的实例序数和边缘名称被访问，使得数据被访问为平坦而不使嵌套数据模型变平。

12. 发明授权

US06230302B1 Method and system for performing timing analysis on an integrated circuit design 失效
标题翻译：用于对集成电路设计进行定时分析的方法和系统
公开(公告)号：US06230302B1
公开(公告)日：2001-05-08
申请号：US09119271
申请日：1998-07-20
申请人： Carol Ivash Gabele , Stephen Thomas Quay , Paul Gerard Villarrubia , Parsotam Trikam Patel , Alexander Koos Spencer
发明人： Carol Ivash Gabele , Stephen Thomas Quay , Paul Gerard Villarrubia , Parsotam Trikam Patel , Alexander Koos Spencer
IPC分类号： G06F1750
CPC分类号： G06F17/5031
摘要： A method and system for performing timing analysis on an integrated circuit design are disclosed. It is always advantageous to be able to conveniently perform a timing analysis on the entire IC design at any stage of the design process in order to gain more accurate timing information about the design. However, at an early stage of the design process, the available physical circuit data are often incomplete, not to mention these preliminary data are usually of a lower quality as far as capability of providing an accurate RC delay and capacitance estimation is concerned. To make the best usage of the preliminary data, the present disclosure describes a method of performing a fleeting timing analysis that can be very useful during an early floor planning stage of the design process when there is no opportunity to buffer or widen any exceptionally long interconnect wires within the IC circuit design. As a result, much faster design turn-around time may be achieved because buffer insertion need not be run for every new pass of the physical circuit design data.
摘要翻译：公开了一种用于对集成电路设计进行定时分析的方法和系统。能够方便地在设计过程的任何阶段对整个IC设计进行时序分析，以便获得关于设计的更准确的时序信息。然而，在设计过程的早期阶段，可用的物理电路数据通常是不完整的，更不用说，就提供准确的RC延迟和电容估计的能力而言，这些初步数据通常质量较差。为了最佳地利用初步数据，本公开描述了一种执行短暂定时分析的方法，其在设计过程的早期楼层规划阶段非常有用，当不存在缓冲或加宽任何特别长的互连电线内IC电路设计。因此，可以实现更快的设计周转时间，因为不需要为物理电路设计数据的每个新的通过运行缓冲器插入。

13. 发明授权

US07464356B2 Method and apparatus for diffusion based cell placement migration 失效
标题翻译：用于基于扩散的细胞置换迁移的方法和装置
公开(公告)号：US07464356B2
公开(公告)日：2008-12-09
申请号：US11304955
申请日：2005-12-15
申请人： Charles Jay Alpert , Haoxing Ren , Paul Gerard Villarrubia
发明人： Charles Jay Alpert , Haoxing Ren , Paul Gerard Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method for cell placement in an integrated circuit design that uses a calculated diffusion velocity determined from a density value in order to relocate the cells until the cell placement reduces the density below a predetermined threshold. The method acts to control the movement of different cells to reduce the density of the cells prior to legalization of the cell placement.
摘要翻译：一种集成电路设计中的细胞放置方法，其使用从密度值确定的计算的扩散速度，以便重新定位细胞，直到细胞放置将密度降低到低于预定阈值。该方法用于控制不同细胞的运动，以在细胞放置合法化之前降低细胞的密度。

14. 发明授权

US07020861B2 Latch placement technique for reduced clock signal skew 失效
标题翻译：锁定放置技术可减少时钟信号偏移
公开(公告)号：US07020861B2
公开(公告)日：2006-03-28
申请号：US10621950
申请日：2003-07-17
申请人： Charles Jay Alpert , Gary Robert Ellis , Gi-Joon Nam , Paul Gerard Villarrubia
发明人： Charles Jay Alpert , Gary Robert Ellis , Gi-Joon Nam , Paul Gerard Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5072
摘要： A method of designing an integrated circuit including executing a placement algorithm to place a set of objects within the integrated circuit. The set of objects includes latched objects and non-latched objects. The algorithm places objects to minimize clock signal delay subject to a constraint on the placement distribution of the latched objects relative to the placement distribution of the non-latched objects. The latched object and non-latched object placement constraints may limit the difference between the latched object center of mass and a non-latched object center of mass. The latched object center of mass equals a sum of size-location products for each latched object divided by the sum of sizes for each latched object. The constraints may require that the latched object center of mass and the non-latched center of mass both equal the center of mass for all objects.
摘要翻译：一种设计集成电路的方法，包括执行放置算法以将一组对象放置在集成电路内。对象集包括锁存对象和非锁定对象。该算法使对象最小化时钟信号延迟，受限于锁存对象相对于非锁定对象的位置分布的位置分布。锁定对象和非锁定对象放置约束可能会限制被锁定的物体质心和未锁定的物体质心之间的差异。被锁定的物体质心等于每个被锁定物体的大小位置乘积之和除以每个锁定物体的大小之和。约束可能要求被锁定的物体质心和非锁定质心均等于所有物体的质心。

15. 发明授权

US06360350B1 Method and system for performing circuit analysis on an integrated-circuit design having design data available in different forms 失效
标题翻译：对具有不同形式的设计数据的集成电路设计进行电路分析的方法和系统
公开(公告)号：US06360350B1
公开(公告)日：2002-03-19
申请号：US08944975
申请日：1997-10-07
申请人： Carol Ivash Gabele , Stephen Thomas Quay , Paul Gerard Villarrubia , Parsotam Trikam Patel , Jean-Paul Watson
发明人： Carol Ivash Gabele , Stephen Thomas Quay , Paul Gerard Villarrubia , Parsotam Trikam Patel , Jean-Paul Watson
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method for performing circuit analysis on an integrated-circuit design having design data available in different forms is disclosed. In accordance with the method and system of the present invention, the integrated-circuit design includes multiple networks, and the different forms of design data may appear within one of the networks. For all of the networks within the integrated-circuit design, different forms of design data are categorized into at least three databases. The first of the at least three databases may contain three-dimensional extraction information, the second of the databases may contain wiring information, and the third of the databases may contain pre-wiring information. For each of the networks, a determination is made as to whether or not three-dimensional extraction information is available. In response to a determination that three-dimensional extraction information is available, performing circuit analysis by utilizing the three-dimensional extraction information.
摘要翻译：公开了一种用于对具有不同形式的设计数据的集成电路设计进行电路分析的方法。根据本发明的方法和系统，集成电路设计包括多个网络，并且不同形式的设计数据可以出现在一个网络内。对于集成电路设计中的所有网络，不同形式的设计数据分为至少三个数据库。至少三个数据库中的第一个可能包含三维提取信息，第二个数据库可能包含布线信息，第三个数据库可能包含预接线信息。对于每个网络，确定三维提取信息是否可用。响应于三维提取信息可用的确定，通过利用三维提取信息进行电路分析。

16. 发明授权

US6080201A Integrated placement and synthesis for timing closure of microprocessors 失效
标题翻译：微处理器定时闭合的集成放置和合成
公开(公告)号：US6080201A
公开(公告)日：2000-06-27
申请号：US21135
申请日：1998-02-10
申请人： Shervin Hojat , Paul Gerard Villarrubia
发明人： Shervin Hojat , Paul Gerard Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5068
摘要： One aspect of the invention relates to a method for improving timing convergence in computer aided semiconductor circuit design. In one particular version of the invention, the method includes the steps of generating a behavioral model of a desired semiconductor circuit, which includes timing constraints for individual paths in the circuit, synthesizing the behavioral model to produce a netlist which represents an implementation of the desired semiconductor circuit mapped to a specific semiconductor technology, the netlist including a list of components in the circuit and a list of nets which connect the components in the circuit, and the step of synthesizing includes performing a timing analysis on the implementation so that the paths in the circuit represented by the netlist meet the timing constraints, the timing analysis being performed using estimated wire lengths for the nets. Next, the components in the netlist are placed into an image representing a predefined area of the semiconductor chip. During this step, actual wire lengths are determined for the nets in the netlist. The steps of synthesizing and placing are then repeated until timing convergences is achieved. Each time the step of synthesizing is repeated, the actual wire lengths from the step of placing are substituted for the estimated wire lengths. Finally, the circuit is routed to produce the final design data.
摘要翻译：本发明的一个方面涉及一种用于改善计算机辅助半导体电路设计中的定时收敛的方法。在本发明的一个特定版本中，该方法包括以下步骤：产生期望的半导体电路的行为模型，其包括电路中各个路径的定时约束，合成行为模型以产生表示期望的实现的网表映射到特定半导体技术的半导体电路，网表包括电路中的组件列表和连接电路中的组件的网络列表，并且合成步骤包括对实现进行定时分析，使得由网表表示的电路满足时序约束，使用网络的估计线长度来执行定时分析。接下来，将网表中的组件放置在表示半导体芯片的预定区域的图像中。在此步骤中，为网表中的网络确定实际的线长度。然后重复合成和放置的步骤，直到达到定时收敛。每次重复合成步骤时，从放置步骤的实际线长度代替估计的线长度。最后，电路被路由以产生最终的设计数据。

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