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11. 发明申请

US20070226464A1 PATCHABLE AND/OR PROGRAMMABLE PRE-DECODE 有权
标题翻译：可调和/或可编程的预编译
公开(公告)号：US20070226464A1
公开(公告)日：2007-09-27
申请号：US11277735
申请日：2006-03-28
申请人： Shailender Chaudhry , Paul Caprioli , Quinn A. Jacobson , Marc Tremblay
发明人： Shailender Chaudhry , Paul Caprioli , Quinn A. Jacobson , Marc Tremblay
IPC分类号： G06F9/40
CPC分类号： G06F9/30145 , G06F9/30174 , G06F9/30196 , G06F9/382 , G06F9/3822 , G06F9/3897
摘要： Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a programmable pre-decode mechanism can be employed to alter the behavior of a processor. For example, pre-decode hints for sequencing, synchronization or speculation control may altered or mappings of ISA instructions to native instructions or operation sequences may be altered. Such techniques may be employed to adapt a processor implementation (in the field) to varying memory models, implementations or interfaces or to varying memory latencies or timing characteristics. Similarly, such techniques may be employed to adapt a processor implementation to correspond to an extended/adapted instruction set architecture. In some realizations, instruction pre-decode functionality may be adapted at processor run-time to handle or mitigate a timing, concurrency or speculation issue. In some realizations, operation of pre-decode may be reprogrammed post-manufacture, at (or about) initialization, or at run-time.
摘要翻译：已经开发了用于在处理器指令处理，排序和执行中提供极大灵活性的机制。特别地，已经发现可以采用可编程预解码机制来改变处理器的行为。例如，用于排序，同步或推测控制的预解码提示可以改变或者将ISA指令映射到本地指令或操作序列可以被改变。可以采用这样的技术来使处理器实现（在现场中）适应于变化的存储器模型，实现或接口或者改变存储器延迟或定时特性。类似地，可以采用这样的技术来使处理器实现适应于扩展/适应的指令集架构。在一些实现中，可以在处理器运行时调整指令预解码功能以处理或减轻定时，并发或推测问题。在某些实现中，可以在（或大约）初始化或运行时在制造后重新编程预解码的操作。

12. 发明申请

US20100191993A1 LOGICAL POWER THROTTLING 有权
标题翻译：逻辑功率曲线
公开(公告)号：US20100191993A1
公开(公告)日：2010-07-29
申请号：US12361422
申请日：2009-01-28
申请人： Shailender Chaudhry , Quinn A. Jacobson , Marc Tremblay
发明人： Shailender Chaudhry , Quinn A. Jacobson , Marc Tremblay
IPC分类号： G06F1/32 , G06F1/26 , G06F9/30
CPC分类号： G06F9/3867 , G06F1/206 , G06F1/3203 , G06F9/3869 , Y02D10/16
摘要： A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.
摘要翻译：处理器包括提供节流功率输出信号的装置。节流电源输出信号用于确定何时逻辑地调节处理器消耗的功率。处理器中的至少一个核心包括具有解码管道的管线; 以及耦合到所述设备以接收所述输出信号并且耦合到所述解码管的逻辑功率节流单元。在接收到满足预定标准的功率节流输出信号的逻辑功率节流单元之后，逻辑功率节流单元使得解码管减少在每个处理器周期解码的平均指令数，而不会物理地改变处理器周期或任何处理器供电电压。

13. 发明授权

US07565511B2 Working register file entries with instruction based lifetime 有权
标题翻译：工作寄存器文件条目与指令生命周期
公开(公告)号：US07565511B2
公开(公告)日：2009-07-21
申请号：US11425869
申请日：2006-06-22
申请人： Shailender Chaudhry , Quinn A. Jacobson , Marc Tremblay
发明人： Shailender Chaudhry , Quinn A. Jacobson , Marc Tremblay
IPC分类号： G06F9/30
CPC分类号： G06F9/3867 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A technique for operating a computing apparatus includes allocating a working register file entry corresponding to a register in a working register file when an instruction referencing the register proceeds through a particular stage of the computing apparatus. The technique maintains the working register file entry until at least a predetermined number of subsequent instructions have similarly proceeded through the particular stage.
摘要翻译：一种用于操作计算设备的技术包括：当参考寄存器的指令通过计算设备的特定阶段进行时，分配与工作寄存器文件中的寄存器相对应的工作寄存器文件条目。该技术维持工作寄存器文件条目，直到至少预定数量的后续指令已经类似地进行到特定阶段。

14. 发明授权

US07509481B2 Patchable and/or programmable pre-decode 有权
标题翻译：可修补和/或可编程预解码
公开(公告)号：US07509481B2
公开(公告)日：2009-03-24
申请号：US11277735
申请日：2006-03-28
申请人： Shailender Chaudhry , Paul Caprioli , Quinn A. Jacobson , Marc Tremblay
发明人： Shailender Chaudhry , Paul Caprioli , Quinn A. Jacobson , Marc Tremblay
IPC分类号： G06F9/00
CPC分类号： G06F9/30145 , G06F9/30174 , G06F9/30196 , G06F9/382 , G06F9/3822 , G06F9/3897
摘要： Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a programmable pre-decode mechanism can be employed to alter the behavior of a processor. For example, pre-decode hints for sequencing, synchronization or speculation control may altered or mappings of ISA instructions to native instructions or operation sequences may be altered. Such techniques may be employed to adapt a processor implementation (in the field) to varying memory models, implementations or interfaces or to varying memory latencies or timing characteristics. Similarly, such techniques may be employed to adapt a processor implementation to correspond to an extended/adapted instruction set architecture. In some realizations, instruction pre-decode functionality may be adapted at processor run-time to handle or mitigate a timing, concurrency or speculation issue. In some realizations, operation of pre-decode may be reprogrammed post-manufacture, at (or about) initialization, or at run-time.
摘要翻译：已经开发了用于在处理器指令处理，排序和执行中提供极大灵活性的机制。特别地，已经发现可以采用可编程预解码机制来改变处理器的行为。例如，用于排序，同步或推测控制的预解码提示可以改变或者将ISA指令映射到本地指令或操作序列可以被改变。可以采用这样的技术来使处理器实现（在现场中）适应于变化的存储器模型，实现或接口或者改变存储器延迟或定时特性。类似地，可以采用这样的技术来使处理器实现适应于扩展/适应的指令集架构。在一些实现中，可以在处理器运行时调整指令预解码功能以处理或减轻定时，并发或推测问题。在某些实现中，可以在（或大约）初始化或运行时在制造后重新编程预解码的操作。

15. 发明授权

US07490229B2 Storing results of resolvable branches during speculative execution to predict branches during non-speculative execution 有权
标题翻译：在投机执行期间存储可分解分支的结果，以在非投机执行期间预测分支
公开(公告)号：US07490229B2
公开(公告)日：2009-02-10
申请号：US11093197
申请日：2005-03-29
申请人： Marc Tremblay , Shailender Chaudhry , Quinn A. Jacobson
发明人： Marc Tremblay , Shailender Chaudhry , Quinn A. Jacobson
IPC分类号： G06F9/00
CPC分类号： G06F9/3844 , G06F9/30105 , G06F9/3838 , G06F9/3842 , G06F9/3863
摘要： One embodiment of the present invention provides a system that facilitates storing results of resolvable branches during speculative execution, and then using the results to predict the same branches during non-speculative execution. During operation, the system executes code within a processor. Upon encountering a stall condition, the system speculatively executes the code from the point of the stall, without committing results of the speculative execution to the architectural state of the processor. Upon encountering a branch instruction that is resolved during speculative execution, the system stores the result of the resolved branch in a branch queue, so that the result can be subsequently used to predict the branch during non-speculative execution.
摘要翻译：本发明的一个实施例提供一种便于在推测性执行期间存储可解析分支的结果的系统，然后在非推测性执行期间使用结果来预测相同的分支。在操作期间，系统在处理器内执行代码。在遇到停顿状态时，系统从失速点推测地执行代码，而不会将推测性执行的结果提交给处理器的体系结构状态。在遇到在推测执行期间解析的分支指令时，系统将解析的分支的结果存储在分支队列中，以便随后可以在非推测性执行期间将结果用于预测分支。

16. 发明授权

US07216202B1 Method and apparatus for supporting one or more servers on a single semiconductor chip 有权
标题翻译：用于在单个半导体芯片上支持一个或多个服务器的方法和装置
公开(公告)号：US07216202B1
公开(公告)日：2007-05-08
申请号：US10787386
申请日：2004-02-24
申请人： Shailender Chaudhry , Marc Tremblay , Quinn A. Jacobson
发明人： Shailender Chaudhry , Marc Tremblay , Quinn A. Jacobson
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F9/3004 , G06F9/3005 , G06F9/30087 , G06F9/30116 , G06F9/528 , G06F12/0815 , G06F2212/507 , G06F2212/681
摘要： One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section.
摘要翻译：本发明的一个实施例提供一种通过推测性地执行代码的关键部分来有助于避免锁定的系统。在操作期间，系统允许进程在程序中推测性地执行代码的关键部分而不首先获得与关键部分相关联的锁定。如果该过程随后完成关键部分而没有遇到来自另一进程的干扰数据访问，则系统进行在推测执行期间所做的更改，并且通过关键部分恢复程序的正常非推测性执行。否则，如果在执行关键部分期间遇到来自其他进程的干扰数据访问，则系统将丢弃在推测执行期间所做的更改，并尝试重新执行临界部分。

17. 发明授权

US07836290B2 Return address stack recovery in a speculative execution computing apparatus 有权
标题翻译：在推测执行计算设备中返回地址堆栈恢复
公开(公告)号：US07836290B2
公开(公告)日：2010-11-16
申请号：US11363625
申请日：2006-02-28
申请人： Shailender Chaudhry , Quinn A. Jacobson , Paul Caprioli , Marc Tremblay
发明人： Shailender Chaudhry , Quinn A. Jacobson , Paul Caprioli , Marc Tremblay
IPC分类号： G06F9/44
CPC分类号： G06F9/3806 , G06F9/3863 , G06F9/3867
摘要： A technique recovers return address stack (RAS) content and restores alignment of a RAS top-of-stack (TOS) pointer for occurrences of mispredictions due to speculative operation, out-of-order instruction processing, and exception handling. In at least one embodiment of the invention, an apparatus includes a speculative execution processor pipeline, a first structure for maintaining return addresses relative to instruction flow at a first stage of the pipeline, at least a second structure for maintaining return addresses relative to instruction flow at a second stage of the pipeline. The second stage of the pipeline is deeper in the pipeline than the first stage. The apparatus includes circuitry operable to reproduce at least return addresses from the second structure to the first structure.
摘要翻译：一种技术恢复返回地址堆栈（RAS）内容，并恢复RAS堆栈顶部（TOS）指针的对齐，用于由于推测操作，无序指令处理和异常处理引起的错误预测。在本发明的至少一个实施例中，一种装置包括推测执行处理器流水线，用于在流水线的第一阶段保持相对于指令流的返回地址的第一结构，用于维持相对于指令流的返回地址的至少第二结构在管道的第二阶段。管道的第二阶段比第一阶段管道更深。该装置包括可操作以至少将从第二结构返回地址再现到第一结构的电路。

18. 发明申请

US20070226475A1 EFFECTIVE ELIMINATION OF DELAY SLOT HANDLING FROM A FRONT SECTION OF A PROCESSOR PIPELINE 有权
标题翻译：从处理器管道的前部分有效消除延迟槽处理
公开(公告)号：US20070226475A1
公开(公告)日：2007-09-27
申请号：US11534125
申请日：2006-09-21
申请人： Shailender Chaudhry , Quinn A. Jacobson , Marc Tremblay
发明人： Shailender Chaudhry , Quinn A. Jacobson , Marc Tremblay
IPC分类号： G06F9/44
CPC分类号： G06F9/3867 , G06F9/3804 , G06F9/3842
摘要： Architectural techniques and implementations that defer enforcement of certain delayed control transfer instruction (DCTI) sequencing constraints or conventions to later stages of an execution pipeline are described. In this way, complexity of a processor pipeline front-end (including fetch sequencing) can be simplified, at least in-part, by fetching instructions generally without regard to such constraints or conventions. Instead, enforcement of such sequencing constraints and/or conventions may be deferred to one or more pipeline stages associated with commitment or retirement of instructions. Higher fetch bandwidth may be achieved in some realizations when, for example, DCTI couples are encountered in an execution sequence.
摘要翻译：描述将某些延迟控制传输指令（DCTI）排序约束或约定的执行推迟到执行流水线的后期的架构技术和实现。以这种方式，处理器流水线前端（包括读取排序）的复杂性可以至少部分地通过一般地取指令来简化，而不考虑这些约束或约定。相反，这种排序约束和/或约定的执行可以推迟到与指令的承诺或退出相关联的一个或多个流水线阶段。当在执行序列中遇到例如DCTI耦合时，在某些实现中可以实现更高的获取带宽。

19. 发明授权

US07269693B2 Selectively monitoring stores to support transactional program execution 有权
标题翻译：选择性地监控存储以支持事务性程序执行
公开(公告)号：US07269693B2
公开(公告)日：2007-09-11
申请号：US10637167
申请日：2003-08-08
申请人： Marc Tremblay , Quinn A. Jacobson , Shailender Chaudhry
发明人： Marc Tremblay , Quinn A. Jacobson , Shailender Chaudhry
IPC分类号： G06F12/14
CPC分类号： G06F12/0862 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/3857 , G06F9/467 , G06F12/0815
摘要： One embodiment of the present invention provides a system that selectively monitors store instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a store instruction during transactional execution of a block of instructions, the system determines whether the store instruction is a monitored store instruction or an unmonitored store instruction. If the store instruction is a monitored store instruction, the system performs the store operation, and store-marks a cache line associated with the store instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the store instruction is an unmonitored store instruction, the system performs the store operation without store-marking the cache line.
摘要翻译：本发明的一个实施例提供了一种系统，其选择性地监视存储指令以支持进程的事务性执行，其中在事务执行期间进行的改变不被提交到处理器的体系结构状态，直到事务执行成功完成。在交易执行指令块期间遇到存储指令时，系统确定存储指令是监视存储指令还是非监视存储指令。如果存储指令是监视的存储指令，则系统执行存储操作，并存储与存储指令相关联的高速缓存行，以便随后检测到来自另一进程的高速缓存行的干扰数据访问。如果存储指令是不受监视的存储指令，则系统执行存储操作而不存储标记高速缓存行。

20. 发明授权

US07058877B2 Method and apparatus for providing error correction within a register file of a CPU 有权
标题翻译：用于在CPU的寄存器文件内提供纠错的方法和装置
公开(公告)号：US07058877B2
公开(公告)日：2006-06-06
申请号：US10146100
申请日：2002-05-14
申请人： Marc Tremblay , Shailender Chaudhry , Quinn A. Jacobson
发明人： Marc Tremblay , Shailender Chaudhry , Quinn A. Jacobson
IPC分类号： H03M13/03
CPC分类号： G06F11/1405
摘要： A system that facilitates error correction within a register file in a central processing unit (CPU). During execution of an instruction by the CPU, the system retrieves a dataword and an associated syndrome from a source register in the register file. Next, the system uses information in the dataword and the associated syndrome to detect, and if necessary correct, an error in the dataword or associated syndrome. This error detection and correction takes place in parallel with using the dataword to perform a computational operation specified by the instruction. If an error is detected, the system prevents the instruction from performing a writeback to a destination register in the register file. The system also writes a corrected dataword to the source register in the register file. Next, the system flushes the instruction pipeline, and restarts execution of the instruction so that the corrected dataword is retrieved for the computational operation.
摘要翻译：便于在中央处理单元（CPU）中的寄存器文件内进行纠错的系统。在CPU执行指令期间，系统从寄存器文件中的源寄存器中检索数据字和相关联的校正子。接下来，系统使用数据字和相关联的综合征中的信息来检测数据字或相关综合征中的错误，并且如果必要的话纠正错误。该错误检测和校正与使用数据字并行执行由指令指定的计算操作。如果检测到错误，系统将阻止该指令对寄存器文件中的目标寄存器执行回写。该系统还将更正的数据字写入寄存器文件中的源寄存器。接下来，系统刷新指令流水线，并且重新开始指令的执行，从而为计算操作检索校正的数据字。

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