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11. 发明授权

US07849373B2 Method of testing a memory module and hub of the memory module 失效
标题翻译：测试内存模块和内存模块集线器的方法
公开(公告)号：US07849373B2
公开(公告)日：2010-12-07
申请号：US12285149
申请日：2008-09-30
申请人： Seung-Man Shin , Byung-Se So , Seung-Jin Seo , You-Keun Han
发明人： Seung-Man Shin , Byung-Se So , Seung-Jin Seo , You-Keun Han
IPC分类号： G11C29/00
CPC分类号： G11C29/08 , G11C5/04 , G11C2029/5602
摘要： Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.
摘要翻译：示例性实施例涉及一种测试存储器模块的方法和系统，该存储器模块具有经由差分输入端子接收单端输入信号的过程，通过该差分输入端子可以从测试设备接收分组信号的差分对，其中测试设备的多个终端可以与存储器模块的多个端子不同，并且基于单端输入信号测试存储器模块的存储器芯片。

12. 发明申请

US20070022335A1 Methods and apparatus for interfacing between test system and memory 失效
标题翻译：用于测试系统和存储器之间接口的方法和设备
公开(公告)号：US20070022335A1
公开(公告)日：2007-01-25
申请号：US11517259
申请日：2006-09-08
申请人： Seung-Man Shin , Seung-Jin Seo , You-Keun Han , Hui-Chong Shin , Jong-Geon Lee , Kyung-Hee Han
发明人： Seung-Man Shin , Seung-Jin Seo , You-Keun Han , Hui-Chong Shin , Jong-Geon Lee , Kyung-Hee Han
IPC分类号： G11C29/00
CPC分类号： G06F11/267
摘要： Methods and apparatuses for entering at least one memory into a test mode are provided. At least one test MRS bit may be stored in a first register for controlling the memory. At least one test MRS code may be programmed into a second register. Each of the at least one bits stored in the first register may correspond one of the at least one test MRS codes stored in the second register.
摘要翻译：提供了将至少一个存储器进入测试模式的方法和装置。至少一个测试MRS位可以存储在用于控制存储器的第一寄存器中。至少一个测试MRS代码可以被编程到第二个寄存器中。存储在第一寄存器中的至少一个比特中的每一个可以对应于存储在第二寄存器中的至少一个测试MRS码之一。

13. 发明授权

US07519873B2 Methods and apparatus for interfacing between test system and memory 失效
标题翻译：用于测试系统和存储器之间接口的方法和设备
公开(公告)号：US07519873B2
公开(公告)日：2009-04-14
申请号：US11517259
申请日：2006-09-08
申请人： Seung-Man Shin , Seung-Jin Seo , You-Keun Han , Hui-Chong Shin , Jong-Geon Lee , Kyung-Hee Han
发明人： Seung-Man Shin , Seung-Jin Seo , You-Keun Han , Hui-Chong Shin , Jong-Geon Lee , Kyung-Hee Han
IPC分类号： G01R31/28
CPC分类号： G06F11/267
摘要： Methods and apparatuses for entering at least one memory into a test mode are provided. At least one test MRS bit may be stored in a first register for controlling the memory. At least one test MRS code may be programmed into a second register. Each of the at least one bits stored in the first register may correspond one of the at least one test MRS codes stored in the second register.
摘要翻译：提供了将至少一个存储器进入测试模式的方法和装置。至少一个测试MRS位可以存储在用于控制存储器的第一寄存器中。至少一个测试MRS代码可以被编程到第二个寄存器中。存储在第一寄存器中的至少一个比特中的每一个可以对应于存储在第二寄存器中的至少一个测试MRS码之一。

14. 发明申请

US20050289287A1 Method and apparatus for interfacing between test system and embedded memory on test mode setting operation 审中-公开
标题翻译：用于在测试模式设置操作之间测试系统和嵌入式存储器之间进行接口的方法和装置
公开(公告)号：US20050289287A1
公开(公告)日：2005-12-29
申请号：US11142673
申请日：2005-06-02
申请人： Seung-Man Shin , Seung-Jin Seo , You-Keun Han , Hui-Chong Shin , Jong-Geon Lee , Kyung Han
发明人： Seung-Man Shin , Seung-Jin Seo , You-Keun Han , Hui-Chong Shin , Jong-Geon Lee , Kyung Han
IPC分类号： G01R31/28 , G06F12/00 , G11C29/00
CPC分类号： G06F11/267
摘要： A method of entering memory module mounted on a memory system or a plurality of memories mounted on the memory module into a test mode, and a first register and a second register for performing the method are introduced. Each of the memory manufacturers provides a different MRS code for entering the memory into the test mode and a different method of entering the memory into the test mode from one another. As a result, the number of the test MRS is stored in the first register for controlling the memory, and the test MRS codes are programmed into the second register. Additionally, each of the bits stored in the first register used for determining the number of the test MRS corresponds to each of the second registers that store a corresponding test MRS code, respectively.
摘要翻译：将安装在存储器系统上的存储器模块或安装在存储器模块上的多个存储器进入测试模式的方法，以及用于执行该方法的第一寄存器和第二寄存器。每个存储器制造商提供用于将存储器输入测试模式的不同MRS代码以及将存储器彼此进入测试模式的不同方法。结果，测试MRS的数量被存储在用于控制存储器的第一寄存器中，并且测试MRS代码被编程到第二寄存器中。此外，存储在用于确定测试MRS的数量的第一寄存器中的每个位分别对应于存储对应的测试MRS代码的每个第二寄存器。

15. 发明授权

US07930465B2 Determining operation mode for semiconductor memory device 有权
标题翻译：确定半导体存储器件的工作模式
公开(公告)号：US07930465B2
公开(公告)日：2011-04-19
申请号：US11256580
申请日：2005-10-21
申请人： Seok-Il Kim , Young-Man Ahn , Byung-Se So , Seung-Jin Seo
发明人： Seok-Il Kim , Young-Man Ahn , Byung-Se So , Seung-Jin Seo
IPC分类号： G06F12/00
CPC分类号： G11C29/46 , G11C11/401
摘要： A semiconductor memory device capable of determining an operation mode by using states of data pins, and an operation mode determining method for the same are disclosed. The semiconductor memory device includes at least one MRS input pad, at least one data input pad, and an operation mode determining circuit. The operation mode determining circuit generates an operation mode determining signal, when an MRS command input through the MRS input pad corresponds to a predetermined MRS command and data signals input through the data input pad or pads include a predetermined combination. Accordingly, the efficiency in the manufacturing and producing processes may be improved by determining the operation mode of the semiconductor memory device in a module assembly process.
摘要翻译：公开了能够通过使用数据引脚的状态来确定操作模式的半导体存储器件及其操作模式确定方法。半导体存储器件包括至少一个MRS输入焊盘，至少一个数据输入焊盘和操作模式确定电路。当通过MRS输入焊盘输入的MRS命令对应于预定的MRS命令并且通过数据输入焊盘或焊盘输入的数据信号包括预定的组合时，操作模式确定电路产生操作模式确定信号。因此，可以通过在模块组装过程中确定半导体存储器件的操作模式来改善制造和制造工艺中的效率。

16. 发明申请

US20060098513A1 Determining operation mode for semiconductor memory device 有权
标题翻译：确定半导体存储器件的工作模式
公开(公告)号：US20060098513A1
公开(公告)日：2006-05-11
申请号：US11256580
申请日：2005-10-21
申请人： Seok-Il Kim , Young-Man Ahn , Byung-Se So , Seung-Jin Seo
发明人： Seok-Il Kim , Young-Man Ahn , Byung-Se So , Seung-Jin Seo
IPC分类号： G11C8/00
CPC分类号： G11C29/46 , G11C11/401
摘要： A semiconductor memory device capable of determining an operation mode by using states of data pins, and an operation mode determining method for the same are disclosed. The semiconductor memory device includes at least one MRS input pad, at least one data input pad, and an operation mode determining circuit. The operation mode determining circuit generates an operation mode determining signal, when an MRS command input through the MRS input pad corresponds to a predetermined MRS command and data signals input through the data input pad or pads include a predetermined combination. Accordingly, the efficiency in the manufacturing and producing processes may be improved by determining the operation mode of the semiconductor memory device in a module assembly process.
摘要翻译：公开了能够通过使用数据引脚的状态来确定操作模式的半导体存储器件及其操作模式确定方法。半导体存储器件包括至少一个MRS输入焊盘，至少一个数据输入焊盘和操作模式确定电路。当通过MRS输入焊盘输入的MRS命令对应于预定的MRS命令并且通过数据输入焊盘或焊盘输入的数据信号包括预定的组合时，操作模式确定电路产生操作模式确定信号。因此，可以通过在模块组装过程中确定半导体存储器件的操作模式来改善制造和制造工艺中的效率。

17. 发明授权

US08159853B2 Memory module cutting off DM pad leakage current 有权
标题翻译：内存模块切断DM焊盘漏电流
公开(公告)号：US08159853B2
公开(公告)日：2012-04-17
申请号：US12693010
申请日：2010-01-25
申请人： Seok-Il Kim , You-Keun Han , Seung-Jin Seo
发明人： Seok-Il Kim , You-Keun Han , Seung-Jin Seo
IPC分类号： G11C5/02
CPC分类号： G11C7/1078 , G11C5/06 , G11C7/1084 , G11C11/4093 , G11C2207/105
摘要： A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground state signal from the DM pad and a bit configuration signal from the memory device and disables the pull-up transistors to cut off a current path between the pull-up resistors of the ODT circuit and the DM pad during a ODT enable mode.
摘要翻译：存储器模块包括：存储器件上的ODT电路，并且包括连接在上拉和下拉晶体管之间的上拉和下拉电阻。在模块板的抽头区域中提供数据屏蔽（DM）焊盘。还提供电流泄漏监测单元并接收来自DM焊盘的基态信号和来自存储器件的位配置信号，并禁止上拉晶体管截止ODT电路的上拉电阻之间的电流通路和ODT使能模式下的DM焊盘。

18. 发明申请

US20060280024A1 Memory system with registered memory module and control method 失效
标题翻译：具有注册内存模块和控制方法的内存系统
公开(公告)号：US20060280024A1
公开(公告)日：2006-12-14
申请号：US11254696
申请日：2005-10-21
申请人： Young-Man Ahn , Seung-Jin Seo , Seung-Hee Mun , Jong-Cheol Seo , Jung-Kuk Lee , Soon-Deok Jang
发明人： Young-Man Ahn , Seung-Jin Seo , Seung-Hee Mun , Jong-Cheol Seo , Jung-Kuk Lee , Soon-Deok Jang
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/222 , G11C11/4076
摘要： A memory module and related method are disclosed. The memory module comprises a clock generator configured to generate first and second internal clock signals in relation to an external clock signal, and a register configured to receive the first and second internal clock signals. The register stores an external control/address signal in response to the first internal clock signal and transmits an internal control/address signal derived from the external control/address in response to the second internal control/address signal.
摘要翻译：公开了一种存储器模块及相关方法。存储器模块包括被配置为相对于外部时钟信号产生第一和第二内部时钟信号的时钟发生器以及被配置为接收第一和第二内部时钟信号的寄存器。寄存器响应于第一内部时钟信号存储外部控制/地址信号，并响应于第二内部控制/地址信号发送从外部控制/地址导出的内部控制/地址信号。

19. 发明授权

US08462534B2 Memory module cutting off DM pad leakage current 有权
标题翻译：内存模块切断DM焊盘漏电流
公开(公告)号：US08462534B2
公开(公告)日：2013-06-11
申请号：US13430860
申请日：2012-03-27
申请人： Seok-Il Kim , You-Keun Han , Seung-Jin Seo
发明人： Seok-Il Kim , You-Keun Han , Seung-Jin Seo
IPC分类号： G11C5/02
CPC分类号： G11C7/1078 , G11C5/06 , G11C7/1084 , G11C11/4093 , G11C2207/105
摘要： A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground state signal from the DM pad and a bit configuration signal from the memory device and disables the pull-up transistors to cut off a current path between the pull-up resistors of the ODT circuit and the DM pad during a ODT enable mode.
摘要翻译：存储器模块包括：存储器件上的ODT电路，并且包括连接在上拉和下拉晶体管之间的上拉和下拉电阻。在模块板的抽头区域中提供数据屏蔽（DM）焊盘。还提供电流泄漏监测单元并接收来自DM焊盘的基态信号和来自存储器件的位配置信号，并禁止上拉晶体管截止ODT电路的上拉电阻之间的电流通路和ODT使能模式下的DM焊盘。

20. 发明授权

US07319635B2 Memory system with registered memory module and control method 失效
标题翻译：具有注册内存模块和控制方法的内存系统
公开(公告)号：US07319635B2
公开(公告)日：2008-01-15
申请号：US11254696
申请日：2005-10-21
申请人： Young-Man Ahn , Seung-Jin Seo , Seung-Hee Mun , Jong-Cheol Seo , Jung-Kuk Lee , Soon-Deok Jang
发明人： Young-Man Ahn , Seung-Jin Seo , Seung-Hee Mun , Jong-Cheol Seo , Jung-Kuk Lee , Soon-Deok Jang
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/222 , G11C11/4076
摘要： A memory module and related method are disclosed. The memory module comprises a clock generator configured to generate first and second internal clock signals in relation to an external clock signal, and a register configured to receive the first and second internal clock signals. The register stores an external control/address signal in response to the first internal clock signal and transmits an internal control/address signal derived from the external control/address in response to the second internal control/address signal.
摘要翻译：公开了一种存储器模块及相关方法。存储器模块包括被配置为相对于外部时钟信号产生第一和第二内部时钟信号的时钟发生器以及被配置为接收第一和第二内部时钟信号的寄存器。寄存器响应于第一内部时钟信号存储外部控制/地址信号，并响应于第二内部控制/地址信号发送从外部控制/地址导出的内部控制/地址信号。

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