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11. 发明授权

US06559051B1 Electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors 有权
标题翻译：用于嵌入栅极MOS晶体管的介电材料前体材料的无电沉积
公开(公告)号：US06559051B1
公开(公告)日：2003-05-06
申请号：US09679881
申请日：2000-10-05
申请人： Matthew S. Buynoski , Paul R. Besser , Paul L. King , Eric N. Paton , Qi Xang
发明人： Matthew S. Buynoski , Paul R. Besser , Paul L. King , Eric N. Paton , Qi Xang
IPC分类号： H01L2144
CPC分类号： H01L21/28194 , H01L21/28114 , H01L29/42376 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/66583
摘要： High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are formed by electrolessly plating a metal or metal-based dielectric precursor layer comprising at least one refractory or lanthanum series transition metal, such as of Zr and/or Hf, on a silicon-based semiconductor substrate and then reacting the precursor layer with oxygen or with oxygen and the Si-based semiconductor substrate to form the at least one metal oxide or silicate. The inventive methodology prevents, or at least substantially reduces, oxygen access to the substrate surface during at least the initial stage(s) of formation of the gate insulator layer, thereby minimizing deleterious formation of oxygen-induced surface states at the semiconductor substrate/gate insulator interface.
摘要翻译：通过无电镀法形成高质量电介质层，例如由至少一种耐火材料或镧系列过渡金属氧化物或硅酸盐构成的高k电介质层，用作叠层金属栅极MOS晶体管和CMOS器件中的栅极绝缘体层金属或金属基电介质前体层，其在硅基半导体衬底上包含至少一种难熔或镧系过渡金属，例如Zr和/或Hf，然后使前体层与氧或氧与Si反应的半导体衬底以形成至少一种金属氧化物或硅酸盐。本发明的方法在至少形成栅极绝缘体层的初始阶段期间防止或至少基本上减少氧接触到衬底表面，从而最小化半导体衬底/栅极处的氧诱导表面状态的有害形成绝缘子接口。

12. 发明授权

US06380057B1 Enhancement of nickel silicide formation by use of nickel pre-amorphizing implant 有权
标题翻译：通过使用镍前非晶化植入物来增强硅化镍的形成
公开(公告)号：US06380057B1
公开(公告)日：2002-04-30
申请号：US09781225
申请日：2001-02-13
申请人： Matthew S. Buynoski , George Jonathan Kluth , Paul R. Besser , Paul L. King
发明人： Matthew S. Buynoski , George Jonathan Kluth , Paul R. Besser , Paul L. King
IPC分类号： H01L213205
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/28044 , H01L21/28052 , H01L21/28518
摘要： Nickel salicide processing is implemented by implanting nickel into the active regions, prior to depositing Ni, to catalyze the reaction of Ni and Si during annealing to form a NiSi layer on the polysilicon gate electrodes and source/drain regions without the formation of rough interfaces between the nickel silicide layers and underlying silicon and without conductive bridging between the metal silicide layer on the gate electrode and the metal silicide layers on associated source/drain regions, particularly in the presence of silicon nitride sidewall spacers.
摘要翻译：镍自杀化处理通过在沉积Ni之前将镍注入活性区域来实现，以在退火期间催化Ni和Si的反应，以在多晶硅栅极电极和源极/漏极区域上形成NiSi层，而不形成在硅化镍层和底层硅，并且在栅电极上的金属硅化物层与相关源极/漏极区域上的金属硅化物层之间没有导电桥接，特别是在存在氮化硅侧壁间隔物的情况下。

13. 发明授权

US06611576B1 Automated control of metal thickness during film deposition 失效
标题翻译：膜沉积期间金属厚度的自动控制
公开(公告)号：US06611576B1
公开(公告)日：2003-08-26
申请号：US09780476
申请日：2001-02-12
申请人： Paul R. Besser , Paul L. King
发明人： Paul R. Besser , Paul L. King
IPC分类号： G01N23223
CPC分类号： C23C14/545 , G01N23/223 , G01N2223/076
摘要： A novel method of automatically controlling thickness of a metal film during film deposition in a deposition chamber. The method involves producing an X-ray beam directed to the metal film deposited on a wafer in a deposition chamber, and detecting X-ray fluorescence of the metal film. The thickness of the metal film determined based on the detected X-ray fluorescence is compared with a preset value to continue deposition if the determined thickness is less than the preset value. Deposition is stopped when the determined thickness reaches the preset value.
摘要翻译：一种在淀积室中成膜期间自动控制金属膜厚度的新方法。该方法包括产生指向沉积在沉积室中的晶片上的金属膜的X射线束，并且检测金属膜的X射线荧光。如果确定的厚度小于预设值，则将基于检测到的X射线荧光确定的金属膜的厚度与预设值进行比较以继续沉积。当确定的厚度达到预设值时，停止沉积。

14. 发明授权

US06368950B1 Silicide gate transistors 有权
标题翻译：硅化物栅极晶体管
公开(公告)号：US06368950B1
公开(公告)日：2002-04-09
申请号：US09734186
申请日：2000-12-12
申请人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
发明人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
IPC分类号： H01L213205
CPC分类号： H01L29/66545 , H01L21/28097
摘要： A method for implementing a self-aligned metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying metal to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The silicon is removed except for the portion of the silicon in the recess. The remaining portions of the metal are removed by manipulating the etch selectivity between the metal and the self-aligned metal silicide gate.
摘要翻译：实现自对准金属硅化物栅极的方法是通过将非晶硅限制在覆盖沟道的凹槽中并退火以使非晶硅与其上覆金属相互作用以形成自对准金属硅化物栅极来实现的。在沉积硅之前，在凹陷的底部和侧壁上形成由氧氮化物或氮化物/氧化物堆叠形成的栅极电介质层。除了凹部中硅的部分之外，除去硅。通过操纵金属和自对准金属硅化物栅之间的蚀刻选择性来去除金属的剩余部分。

15. 发明授权

US06342414B1 Damascene NiSi metal gate high-k transistor 有权
标题翻译：大马士革NiSi金属栅极高k晶体管
公开(公告)号：US06342414B1
公开(公告)日：2002-01-29
申请号：US09734189
申请日：2000-12-12
申请人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
发明人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
IPC分类号： H01L218238
CPC分类号： H01L21/28194 , H01L21/28097 , H01L21/28114 , H01L29/495 , H01L29/4975 , H01L29/51 , H01L29/517 , H01L29/665 , H01L29/66545
摘要： A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining a low temperature silicidation metal within a recess overlying a channel and annealing to cause the low temperature silicidation metal and its overlying silicon to interact to form the self-aligned low temperature metal silicide gate. A planarization step is performed to remove the remaining unreacted silicon by chemical mechanical polishing until no silicon is detected.
摘要翻译：实现自对准低温金属硅化物栅极的方法是通过将低温硅化金属限制在覆盖沟道的凹槽内并进行退火以使低温硅化金属及其上覆的硅相互作用以形成自对准低温度金属硅化物门。进行平面化步骤以通过化学机械抛光除去剩余的未反应的硅，直到没有检测到硅。

16. 发明授权

US06297107B1 High dielectric constant materials as gate dielectrics 有权
标题翻译：高介电常数材料作为栅极电介质
公开(公告)号：US06297107B1
公开(公告)日：2001-10-02
申请号：US09691228
申请日：2000-10-19
申请人： Eric Paton , Matthew S. Byunoski , Paul R. Besser , Paul L. King , Qi Xiang
发明人： Eric Paton , Matthew S. Byunoski , Paul R. Besser , Paul L. King , Qi Xiang
IPC分类号： H01L21336
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/31691 , H01L29/517 , H01L29/66545
摘要： A semiconductor structure having a gate dielectric between a gate electrode and a semiconductor substrate is formed with a high dielectric metal oxide layer by replacing a sacrificial gate oxide. Embodiments include forming the metal oxide layer by applying a chemical solution deposition of a metalorganic on to an exposed surface of the substrate followed by pyrolizing the metalorganic residue to a metal oxide.
摘要翻译：通过替代牺牲栅极氧化物，在栅电极和半导体衬底之间具有栅极电介质的半导体结构形成有高介电金属氧化物层。实施例包括通过将金属有机物的化学溶液沉积施加到基板的暴露表面上，然后将金属有机残渣热解成金属氧化物来形成金属氧化物层。

17. 发明授权

US4181194A Safety clamp device and apparatus utilizing same 失效
标题翻译：安全钳装置及利用该装置的装置
公开(公告)号：US4181194A
公开(公告)日：1980-01-01
申请号：US914277
申请日：1978-06-09
申请人： James H. Bassett , Paul L. King
发明人： James H. Bassett , Paul L. King
IPC分类号： E04G3/32 , E04G3/10
CPC分类号： E04G3/32 , Y10T24/3949
摘要： An improved safety clamp device for use with movable platforms and the like includes a body member having a safety cable receiving cradle, a lever arm having a safety cable engaging portion, the lever arm being pivotally connected to the body member and pivotally connected to an elongate bar member, and a modified bellcrank. The modified bellcrank has a first arm pivotally connected to the body member, a second arm pivotally coupled to a hoist line, and its apex pivotally connected to the elongate bar member. When the elongate bar member is in a first position relative to the body member, the safety cable engaging portion confronts but does not engage the safety cable. When the elongate bar member is in a second position relative to the body member, the safety cable engaging portion engages the safety cable thereby wedging the safety cable between the cradle and the safety cable engaging portions. The modified bellcrank and the lever arm operate cooperatively to maintain the body member and the elongate bar member in parallel relationship to the safety cable.
摘要翻译：一种用于可移动平台等的改进的安全夹紧装置包括具有安全电缆接收支架的主体构件，具有安全缆线接合部分的杠杆臂，杠杆臂可枢转地连接到主体构件并枢转地连接到细长酒吧会员和修改后的曲拐。改进的曲拐具有枢转地连接到主体构件的第一臂，枢转地联接到提升线的第二臂，并且其顶点枢转地连接到细长杆构件。当细长杆构件相对于主体构件处于第一位置时，安全缆线接合部分面对但不接合安全缆线。当细长杆构件相对于主体构件处于第二位置时，安全缆线接合部分接合安全缆线，从而将安全缆线楔入托架和安全缆线接合部分之间。改进的曲拐和杠杆臂协同工作以使主体构件和细长杆构件保持与安全缆线平行的关系。

18. 发明授权

US07250667B2 Selectable open circuit and anti-fuse element 有权
标题翻译：可选开路和反熔丝元件
公开(公告)号：US07250667B2
公开(公告)日：2007-07-31
申请号：US11306663
申请日：2006-01-05
申请人： Darin A. Chan , Simon Siu-Sing Chan , Paul L. King
发明人： Darin A. Chan , Simon Siu-Sing Chan , Paul L. King
IPC分类号： H01L29/00
CPC分类号： H01L27/112 , H01L23/5252 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is provided with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. Source/drain junctions are in the semiconductor substrate. A silicide is on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is above the semiconductor substrate. Contacts and connection points are in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.
摘要翻译：集成电路设置有半导体衬底，当半导体衬底反应以形成这种硅化物时，半导体衬底被掺杂为具有与硅化物的顶表面分离的类型的可氧化掺杂剂的设定浓度。栅极电介质位于半导体衬底上，栅极位于栅极电介质上。源极/漏极结在半导体衬底中。硅化物在源极/漏极结上，掺杂剂分离到硅化物的顶表面。分离的掺杂剂的顶表面上的掺杂剂被氧化以在硅化物之上形成氧化掺杂剂的绝缘层。层间电介质在半导体衬底之上。触点和连接点位于硅化物之上的氧化掺杂剂的绝缘层的层间电介质中。

19. 发明授权

US07151020B1 Conversion of transition metal to silicide through back end processing in integrated circuit technology 有权
标题翻译：在集成电路技术中通过后端处理将过渡金属转化为硅化物
公开(公告)号：US07151020B1
公开(公告)日：2006-12-19
申请号：US10839437
申请日：2004-05-04
申请人： Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Robert J. Chiu , Errol Todd Ryan , Darin A. Chan , Paul R. Besser , Paul L. King , Minh Van Ngo
发明人： Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Robert J. Chiu , Errol Todd Ryan , Darin A. Chan , Paul R. Besser , Paul L. King , Minh Van Ngo
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A transition metal layer is formed on the source/drain junctions and on the gate. An interlayer dielectric is formed above the semiconductor substrate. Contacts are then formed in the interlayer dielectric, whereby a silicide is formed from the transition metal layer at a temperature no higher than the maximum temperature at which the interlayer dielectric and the contacts are formed.
摘要翻译：提供一种形成具有半导体衬底的集成电路的方法。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。在半导体衬底中形成源极/漏极结。在源极/漏极结和栅极上形成过渡金属层。在半导体衬底上形成层间电介质。然后在层间电介质中形成触点，由此在不高于形成层间电介质和触点的最高温度的温度下由过渡金属层形成硅化物。

20. 发明授权

US07015076B1 Selectable open circuit and anti-fuse element, and fabrication method therefor 失效
标题翻译：可选开路和反熔丝元件及其制造方法
公开(公告)号：US07015076B1
公开(公告)日：2006-03-21
申请号：US10791098
申请日：2004-03-01
申请人： Darin A. Chan , Simon Siu-Sing Chan , Paul L. King
发明人： Darin A. Chan , Simon Siu-Sing Chan , Paul L. King
IPC分类号： H01L21/82
CPC分类号： H01L27/112 , H01L23/5252 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A method is provided of forming an integrated circuit with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is deposited above the semiconductor substrate. Contacts and connection points are then formed in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.
摘要翻译：提供了一种形成集成电路的方法，该半导体衬底在半导体衬底反应形成这种硅化物时，掺杂有一定类型的可氧化掺杂剂的分解与硅化物顶表面的浓度。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。在半导体衬底中形成源极/漏极结。在源极/漏极结上形成硅化物，掺杂剂分离到硅化物的顶表面。分离的掺杂剂的顶表面上的掺杂剂被氧化以在硅化物之上形成氧化掺杂剂的绝缘层。在半导体衬底上沉积层间电介质。接触点和连接点然后在层间电介质中形成到硅化物之上的氧化掺杂剂的绝缘层。

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