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11. 外观设计

USD642173S1 External CD-ROM drive 有权
标题翻译：外置CD-ROM驱动器
公开(公告)号：USD642173S1
公开(公告)日：2011-07-26
申请号：US29363832
申请日：2010-06-15
申请人： Chul Lee , Gang Ho Woo , Young Won Jeong
设计人： Chul Lee , Gang Ho Woo , Young Won Jeong

12. 发明申请

US20080315282A1 Semiconductor Devices Including Transistors Having Three Dimensional Channels 审中-公开
标题翻译：包括具有三维通道的晶体管的半导体器件
公开(公告)号：US20080315282A1
公开(公告)日：2008-12-25
申请号：US12199237
申请日：2008-08-27
申请人： Eun-Suk Cho , Chul Lee
发明人： Eun-Suk Cho , Chul Lee
IPC分类号： H01L29/788
CPC分类号： H01L23/485 , H01L29/41791 , H01L29/66795 , H01L29/785 , H01L29/7853 , H01L29/7854 , H01L2029/7858 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices including a gate electrode crossing over a semiconductor fin on a semiconductor substrate are provided. A gate insulating layer is provided between the gate electrode and the semiconductor fin. A channel region having a three-dimensional structure defined at the semiconductor fin under the gate electrode is also provided. Doped region is provided in the semiconductor fin at either side of the gate electrode and an interlayer insulating layer is provided on a surface of the semiconductor substrate. A connector region is coupled to the doped region and provided in an opening, which penetrates the interlayer insulating layer. A recess region is provided in the doped region and is coupled to the connector region. The connector region contacts an inner surface of the recess region. Related methods of fabricating semiconductor devices are also provided herein.
摘要翻译：提供包括在半导体衬底上与半导体鳍状物交叉的栅电极的半导体器件。栅极绝缘层设置在栅电极和半导体鳍之间。还提供了在栅电极下方的半导体鳍片处限定的具有三维结构的沟道区域。掺杂区域设置在栅电极的任一侧的半导体鳍片中，并且在半导体衬底的表面上设置层间绝缘层。连接器区域耦合到掺杂区域并且设置在穿过层间绝缘层的开口中。在掺杂区域中提供凹陷区域并且耦合到连接器区域。连接器区域接触凹部区域的内表面。本文还提供了制造半导体器件的相关方法。

13. 发明授权

US07323375B2 Fin field effect transistor device and method of fabricating the same 失效
标题翻译： Fin场效应晶体管器件及其制造方法
公开(公告)号：US07323375B2
公开(公告)日：2008-01-29
申请号：US11091457
申请日：2005-03-28
申请人： Jae-Man Yoon , Dong-Gun Park , Choong-Ho Lee , Chul Lee
发明人： Jae-Man Yoon , Dong-Gun Park , Choong-Ho Lee , Chul Lee
IPC分类号： H01L21/00
CPC分类号： H01L29/7851 , H01L21/84 , H01L29/66795
摘要： Methods of forming field effect transistors (FETs) having fin-shaped active regions include patterning a semiconductor substrate to define a fin-shaped semiconductor active region therein, which is surrounded by a trench. At least an upper portion of the fin-shaped semiconductor active region is covered with a sacrificial layer. This sacrificial layer is selectively etched-back to define sacrificial spacers on sidewalls of the fin-shaped semiconductor active region. The electrically insulating region is formed on the sacrificial spacers. The sacrificial spacers are then removed by selectively etching the sacrificial spacers using the electrically insulating region as an etching mask. An insulated gate electrode is then formed on the sidewalls of the fin-shaped semiconductor active region.
摘要翻译：形成具有鳍状有源区的场效应晶体管（FET）的方法包括图案化半导体衬底以在其中限定由沟槽包围的鳍状半导体有源区。鳍形半导体有源区域的至少上部被牺牲层覆盖。该牺牲层被有选择地回蚀刻以在鳍状半导体有源区域的侧壁上限定牺牲隔离物。电绝缘区域形成在牺牲间隔物上。然后通过使用电绝缘区域作为蚀刻掩模选择性地蚀刻牺牲隔离物来去除牺牲间隔物。然后在鳍状半导体有源区的侧壁上形成绝缘栅电极。

14. 发明授权

US07227220B2 Semiconductor devices having buried bit lines and methods of manufacturing semiconductor devices having buried bit lines 失效
标题翻译：具有掩埋位线的半导体器件和具有掩埋位线的半导体器件的制造方法
公开(公告)号：US07227220B2
公开(公告)日：2007-06-05
申请号：US11240544
申请日：2005-09-30
申请人： Tae-yong Kim , Choong-ho Lee , Chul Lee , Eun-suk Cho , Suk-kang Sung , Hye-jin Cho
发明人： Tae-yong Kim , Choong-ho Lee , Chul Lee , Eun-suk Cho , Suk-kang Sung , Hye-jin Cho
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L27/11568
摘要： A semiconductor device includes a semiconductor substrate having a first conductivity type and having an upper portion, a pair of bit lines extending in a first direction and doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in the upper portion of the semiconductor substrate, a first line formed between the pair of bit lines having a plurality of alternating recessed device isolation regions and channel regions, with each of the channel regions contacting each bit line of the at least one pair of bit lines, and word lines formed at right angles to the first lines and covering the channel regions.
摘要翻译：半导体器件包括具有第一导电类型并具有上部的半导体衬底，一对位线沿着第一方向延伸并且掺杂有与第一导电类型相反并且彼此间隔开的第二导电类型的杂质所述半导体衬底的上部，形成在所述一对位线之间的第一线，所述第一线具有多个交替的凹陷器件隔离区域和沟道区域，其中每个沟道区域与所述至少一对位线的每个位线接触以及与第一线成直角形成并覆盖沟道区的字线。

15. 发明申请

US20070104929A1 Method for plating printed circuit board and printed circuit board manufactured therefrom 审中-公开
标题翻译：电镀印刷电路板和印刷电路板的方法
公开(公告)号：US20070104929A1
公开(公告)日：2007-05-10
申请号：US11586006
申请日：2006-10-25
申请人： Kyu Yim , Sung Chun , Dek Yang , Dong An , Chul Lee , Mi Han
发明人： Kyu Yim , Sung Chun , Dek Yang , Dong An , Chul Lee , Mi Han
IPC分类号： B05D5/12 , B32B3/00
CPC分类号： H05K3/244 , C23C18/44 , C23C18/54 , H01L21/4846 , H01L23/498 , H01L24/85 , H01L2224/45124 , H01L2224/45144 , H01L2224/85444 , H01L2924/00011 , H01L2924/0002 , H05K3/28 , H05K2203/072 , H05K2203/073 , Y10T428/24917 , H01L2924/00 , H01L2924/01033
摘要： Disclosed herein are a method for plating a printed circuit board and the printed circuit board manufactured therefrom. In the method, a bare soldering or wire bonding portion of a copper (Cu)- or copper alloy layer, is plated with palladium (Pd) or a palladium alloy, and then gold (Au) or a gold alloy is deposited over the palladium or palladium alloy plated layer by an electroless substitution plating process based on ionization tendency. Having superior hardness, ductility and corrosion resistance, palladium is suitable for use between a connector and a substrate and meets requirements for the printed circuit board even when applied to a low thickness, greatly reducing the process time. Accordingly, the problem of black pad, which frequently occur on electroless nickel and electroless gold finish upon surface mount technology, can be perfectly solved. Particularly, fatal bending cracks can be prevented from occurring in the rigid-flexible or flexible printed circuit boards.
摘要翻译：这里公开了印刷电路板和由其制造的印刷电路板的电镀方法。在该方法中，铜（Cu）或铜合金层的裸焊或引线接合部分镀钯（Pd）或钯合金，然后将金（Au）或金合金沉积在钯或钯合金镀层，通过基于电离倾向的无电取代电镀工艺。具有优异的硬度，延展性和耐腐蚀性，钯适用于连接器和基板之间，并且即使应用于低厚度也可满足印刷电路板的要求，大大减少了处理时间。因此，通过表面贴装技术在化学镀镍和无电镀金上经常出现的黑色焊盘的问题可以得到很好的解决。特别地，可以防止在刚性柔性或柔性印刷电路板中发生致命的弯曲裂纹。

16. 发明授权

US07160780B2 Method of manufacturing a fin field effect transistor 有权
标题翻译：制造鳍式场效应晶体管的方法
公开(公告)号：US07160780B2
公开(公告)日：2007-01-09
申请号：US11066703
申请日：2005-02-23
申请人： Chul Lee , Jae-Man Yoon , Choong-Ho Lee
发明人： Chul Lee , Jae-Man Yoon , Choong-Ho Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L29/66795
摘要： In an exemplary embodiment, a fin active region is protruded along one direction from a bulk silicon substrate on which a shallow trench insulator is entirely formed so as to cover the fin active region. The shallow trench insulator is removed to selectively expose an upper part and sidewall of the fin active region, along a line shape that at least one time crosses with the fin active region, thus forming a trench. The fin active region is exposed by the trench and thereon a gate insulation layer is formed. Thereby, productivity is increased and performance of the device is improved. A fin FET employs a bulk silicon substrate of which a manufacturing cost is lower than that of a conventional SOI type silicon substrate. Also, a floating body effect can be prevented, or is substantially reduced.
摘要翻译：在一个示例性实施例中，翅片有源区域沿着整体形成浅沟槽绝缘体的体硅基板沿着一个方向突出，以覆盖翅片有源区域。去除浅沟槽绝缘体，以沿着至少一次与翅片有源区交叉的线形状选择性地暴露翅片有源区的上部和侧壁，从而形成沟槽。翅片有源区域被沟槽暴露，并且形成有栅极绝缘层。从而，提高了生产效率并提高了设备的性能。翅片FET采用其制造成本低于常规SOI型硅衬底的制造成本的体硅衬底。此外，可以防止浮体效应或大大降低浮体效应。

17. 发明申请

US20050269629A1 Fin field effect transistors and methods of fabricating the same 有权
标题翻译： Fin场效应晶体管及其制造方法
公开(公告)号：US20050269629A1
公开(公告)日：2005-12-08
申请号：US11084922
申请日：2005-03-21
申请人： Chul Lee , Min-Sang Kim , Dong-gun Park , Choong-ho Lee , Chang-woo Oh , Jae-man Yoon , Dong-won Kim , Jeong-dong Choe , Ming Li , Hye-jin Cho
发明人： Chul Lee , Min-Sang Kim , Dong-gun Park , Choong-ho Lee , Chang-woo Oh , Jae-man Yoon , Dong-won Kim , Jeong-dong Choe , Ming Li , Hye-jin Cho
IPC分类号： H01L21/00 , H01L21/20 , H01L21/265 , H01L21/336 , H01L21/84 , H01L29/76 , H01L29/786 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/785 , H01L21/26513 , H01L21/845 , H01L29/66795 , H01L29/78624
摘要： A fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top of a portion of the fin. The gate insulation layer is between the gate electrode and the fin. The source region and the drain region in the fin and adjacent to opposite sides of the gate electrode. The source region of the fin has a different width than the drain region of the fin.
摘要翻译：翅片场效应晶体管（FinFET）包括衬底，鳍，栅电极，栅极绝缘层以及鳍中的源极和漏极区。翅片在基底上并沿着和垂直方向横向延伸。栅电极覆盖翅片的一侧和顶部。栅绝缘层位于栅电极和鳍之间。翅片中的源极区域和漏极区域，并且与栅电极的相对侧相邻。翅片的源极区域具有与鳍片的漏极区域不同的宽度。

18. 发明申请

US20050267317A1 Bisphenyl-2,3,5,6-tetrafluoro-4-trifluoromethylphenyl phosphine oxide derivative and synthesis thereof 失效
标题翻译：二苯基-2,3,5,6-四氟-4-三氟甲基苯基氧化膦衍生物及其合成
公开(公告)号：US20050267317A1
公开(公告)日：2005-12-01
申请号：US11016293
申请日：2004-12-17
申请人： Tae-Ho Yoon , Chul Lee , Kwak Min
发明人： Tae-Ho Yoon , Chul Lee , Kwak Min
IPC分类号： C07B61/00 , C07F9/02 , C07F9/53 , C07F9/553 , C08G73/10
CPC分类号： C08G73/0246 , C07F9/5325 , C07F9/5537
摘要： The present invention relates to bisphenyl-2,3,5,6-tetrafluoro-4-trifluoromethylphenylphosphine oxide compounds and synthesis thereof, more particularly to novel bisphenyl-2,3,5,6-tetrafluoro-4-trifluoromethylphenylphosphine oxide compounds having both a perfluorinated benzene substituent and a phosphine oxide moiety. Compounds of the invention can be useful as a monomer for preparing polyimides having a low dielectric constant and a superior adhesion while maintaining the superior thermal and mechanical properties of polyimides themselves, and their synthesis thereof.
摘要翻译：本发明涉及双苯基-2,3,5,6-四氟-4-三氟甲基苯基氧化膦化合物及其合成，更具体地涉及新的双苯基-2,3,5,6-四氟-4-三氟甲基苯基氧化膦化合物，其具有全氟化苯取代基和氧化膦部分。本发明的化合物可用作制备具有低介电常数和优异粘附性的聚酰亚胺的单体，同时保持聚酰亚胺本身的优异的热和机械性能及其合成。

19. 发明申请

US20050250285A1 Fin field effect transistor device and method of fabricating the same 失效
标题翻译： Fin场效应晶体管器件及其制造方法
公开(公告)号：US20050250285A1
公开(公告)日：2005-11-10
申请号：US11091457
申请日：2005-03-28
申请人： Jae-Man Yoon , Dong-Gun Park , Choong-Ho Lee , Chul Lee
发明人： Jae-Man Yoon , Dong-Gun Park , Choong-Ho Lee , Chul Lee
IPC分类号： H01L21/00 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L29/786 , H01L29/94
CPC分类号： H01L29/7851 , H01L21/84 , H01L29/66795
摘要： Methods of forming field effect transistors (FETs) having fin-shaped active regions include patterning a semiconductor substrate to define a fin-shaped semiconductor active region therein, which is surrounded by a trench. At least an upper portion of the fin-shaped semiconductor active region is covered with a sacrificial layer. This sacrificial layer is selectively etched-back to define sacrificial spacers on sidewalls of the fin-shaped semiconductor active region. The electrically insulating region is formed on the sacrificial spacers. The sacrificial spacers are then removed by selectively etching the sacrificial spacers using the electrically insulating region as an etching mask. An insulated gate electrode is then formed on the sidewalls of the fin-shaped semiconductor active region.
摘要翻译：形成具有鳍状有源区的场效应晶体管（FET）的方法包括图案化半导体衬底以在其中限定由沟槽包围的鳍状半导体有源区。鳍形半导体有源区域的至少上部被牺牲层覆盖。该牺牲层被有选择地回蚀刻以在鳍状半导体有源区域的侧壁上限定牺牲隔离物。电绝缘区域形成在牺牲间隔物上。然后通过使用电绝缘区域作为蚀刻掩模选择性地蚀刻牺牲隔离物来去除牺牲间隔物。然后在鳍状半导体有源区的侧壁上形成绝缘栅电极。

20. 发明申请

US20050088585A1 Liquid crystal display module including thermoelectric device 有权
标题翻译：液晶显示模块包括热电装置
公开(公告)号：US20050088585A1
公开(公告)日：2005-04-28
申请号：US10972449
申请日：2004-10-26
申请人： Chul Lee
发明人： Chul Lee
IPC分类号： G02F1/13357 , G02F1/133 , G02F1/1335 , H01L35/30
CPC分类号： H01L35/30 , G02F1/133
摘要： A liquid crystal display device includes a backlight unit having a lamp, wherein the lamp includes opposing ends and electrodes at respective ones of the opposing ends; at least one thermoelectric device operably proximate to the lamp; and a liquid crystal (LC) panel over the backlight unit. Each thermoelectric device includes a hot junction disposed near the lamp; a cold junction spaced apart from the hot junction and disposed farther from the lamp than the hot junction; two different thermoelectric materials between the hot and cold junctions, wherein the two different thermoelectric materials are spaced from each other and wherein opposing ends of each of the different thermoelectric materials contact the hot and cold junctions; and first and second wires connected to respective ones of the two different thermoelectric materials.
摘要翻译：液晶显示装置包括具有灯的背光单元，其中所述灯在相对端的相应端部包括相对端和电极; 至少一个可操作地靠近所述灯的热电装置; 以及背光单元上的液晶（LC）面板。每个热电装置包括设置在灯附近的热连接点; 与热接点间隔开的冷连接处，并且比热连接处设置得比灯更远; 两个不同的热电材料在热连接点和冷连接点之间，其中两个不同的热电材料彼此间隔开，并且每个不同热电材料的相对端部接触热连接点和冷连接点; 以及连接到两个不同热电材料中的相应的第一和第二导线。

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