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    • 14. 发明授权
    • Method using a thin resist mask for dual damascene stop layer etch
    • 使用薄抗蚀剂掩模的双镶嵌停止层蚀刻方法
    • US06184128B2
    • 2001-02-06
    • US09497222
    • 2000-01-31
    • Fei WangChristopher F. LyonsKhanh B. NguyenScott A. BellHarry J. LevinsonChih Yuh Yang
    • Fei WangChristopher F. LyonsKhanh B. NguyenScott A. BellHarry J. LevinsonChih Yuh Yang
    • H01L214763
    • H01L21/7681H01L21/31144
    • In one embodiment, the present invention relates to a dual damascene method involving the steps of providing a substrate having a first low k material layer; forming a first hard mask layer over the first low k material layer; patterning a first opening having a first width in the first hard mask layer using a first photoresist thereby exposing a portion of the first low k material layer; removing the first photoresist; depositing a second low k material layer over the patterned first hard mask layer and the exposed portion of the first low k material layer; forming a second hard mask layer over the second low k material layer; patterning a second opening having a width larger than the first width in the second hard mask layer using a second photoresist thereby exposing a portion of the second low k material layer; anisotropically etching the exposed portions of the first and second low k material layers; and removing the second photoresist, wherein and at least one of the first photoresist and the second photoresist have a thickness of about 1,500 Å or less.
    • 在一个实施例中,本发明涉及一种双镶嵌方法,包括以下步骤:提供具有第一低k材料层的基底; 在所述第一低k材料层上形成第一硬掩模层; 使用第一光致抗蚀剂构图在第一硬掩模层中具有第一宽度的第一开口,从而暴露第一低k材料层的一部分; 去除第一光致抗蚀剂; 在图案化的第一硬掩模层和第一低k材料层的暴露部分上沉积第二低k材料层; 在所述第二低k材料层上形成第二硬掩模层; 使用第二光致抗蚀剂构图在第二硬掩模层中形成具有大于第一宽度的宽度的第二开口,从而暴露第二低k材料层的一部分; 各向异性地蚀刻第一和第二低k材料层的暴露部分; 并且去除所述第二光致抗蚀剂,其中所述第一光致抗蚀剂和所述第二光致抗蚀剂中的至少一个具有大约等于或小于1500埃的厚度。
    • 15. 发明授权
    • Mark protection scheme with no masking
    • 标记保护方案,无掩蔽
    • US06057206A
    • 2000-05-02
    • US410526
    • 1999-10-01
    • Khanh B. NguyenMarina PlatChristopher F. LyonsHarry J. Levinson
    • Khanh B. NguyenMarina PlatChristopher F. LyonsHarry J. Levinson
    • H01L23/544H01L21/76
    • H01L23/544H01L2223/54426H01L2223/54453H01L2223/54493H01L2924/0002
    • A method of forming an alignment mark protection structure is disclosed and includes forming an alignment mark protection layer over a substrate which has an alignment mark associated therewith. The method also includes forming a negative photoresist layer over the alignment mark protection layer and removing a portion of the negative photoresist layer which does not overlie the alignment mark. The removal exposes a portion of the alignment mark protection layer which does not overlie the alignment mark and the exposed portion of the alignment mark protection layer is then removed. Preferably, the removal of a portion of the negative photoresist includes selectively exposing a peripheral portion thereof using an edge-bead removal tool, thereby allowing for the formation of an alignment mark protection structure without an extra masking step.
    • 公开了一种形成对准标记保护结构的方法,并且包括在具有与其相关联的对准标记的衬底上形成对准标记保护层。 该方法还包括在对准标记保护层上形成负光致抗蚀剂层,并且去除不覆盖对准标记的负光致抗蚀剂层的一部分。 去除暴露出不覆盖对准标记的对准标记保护层的一部分,然后去除对准标记保护层的暴露部分。 优选地,去除负光致抗蚀剂的一部分包括使用边缘珠去除工具选择性地暴露其周边部分,从而允许形成对准标记保护结构而没有额外的掩模步骤。
    • 16. 发明授权
    • System for controlling reflection reticle temperature in microlithography
    • 微光刻反射标线温度系统
    • US6098408A
    • 2000-08-08
    • US189228
    • 1998-11-11
    • Harry J. LevinsonKhanh B. Nguyen
    • Harry J. LevinsonKhanh B. Nguyen
    • F25B21/02G03F7/20G05D23/19
    • G03F7/707F25B21/02G03F7/70283G03F7/70875G05D23/1919G05D23/1934G05D23/24Y02B30/765
    • A system for regulating reticle temperature is provided. The system includes a reticle for use in a lithographic process and a chuck assembly for supporting the reticle. The chuck assembly includes: a backplate having front and back surfaces, the front surface engaging with a backside of the reticle; and a thermoelectric cooling system operatively coupled to the backplate for regulating temperature of at least a portion of the reticle via heat conduction through the backplate. The chuck assembly also includes a temperature sensing system coupled to the backplate for sensing temperature of at least a portion of the reticle via heat conduction through the backplate; and a heat sink operatively coupled to the thermoelectric cooling system. A voltage driver operatively is coupled to the thermoelectric cooling system, the voltage driver provides a bias voltage to drive the thermoelectric cooling system. A processor is operatively coupled to the voltage driver, the processor employing the voltage driver in controlling the thermoelectric cooling system.
    • 提供了一种用于调节掩模版温度的系统。 该系统包括用于光刻工艺的掩模版和用于支撑掩模版的卡盘组件。 卡盘组件包括:背板,其具有前表面和后表面,前表面与掩模版的背面接合; 以及可操作地耦合到所述背板的热电冷却系统,用于通过所述背板的热传导来调节所述掩模版的至少一部分的温度。 卡盘组件还包括耦合到背板的温度感测系统,用于通过背板的热传导来感测至少一部分光罩的温度; 以及可操作地耦合到热电冷却系统的散热器。 电压驱动器可操作地耦合到热电冷却系统,电压驱动器提供偏置电压来驱动热电冷却系统。 处理器可操作地耦合到电压驱动器,处理器采用电压驱动器来控制热电冷却系统。
    • 20. 发明授权
    • Methods of forming contacts for semiconductor devices using a local interconnect processing scheme
    • 使用局部互连处理方案形成用于半导体器件的触点的方法
    • US08809184B2
    • 2014-08-19
    • US13465633
    • 2012-05-07
    • Lei YuanJin ChoJongwook KyeHarry J. Levinson
    • Lei YuanJin ChoJongwook KyeHarry J. Levinson
    • H01L21/762H01L21/768H01L21/8238H01L21/441H01L23/535
    • H01L21/823475H01L21/76895H01L23/485H01L27/0207H01L2924/0002H01L2924/00
    • One method disclosed herein includes forming a plurality of source/drain contacts that are conductively coupled to a source/drain region of a plurality of transistor devices, wherein at least one of the source/drain contacts is a local interconnect structure that spans the isolation region and is conductively coupled to a first source/drain region in a first active region and to a second source/drain region in a second active region, and forming a patterned mask layer that covers the first and second active regions and exposes at least a portion of the local interconnect structure positioned above an isolation region that separates the first and second active regions. The method further includes performing an etching process through the patterned mask layer to remove a portion of the local interconnect structure, thereby defining a recess positioned above a remaining portion of the local interconnect structure, and forming an insulating material in the recess.
    • 本文公开的一种方法包括形成导电耦合到多个晶体管器件的源极/漏极区域的多个源极/漏极接触,其中源极/漏极接触中的至少一个是跨越隔离区域的局部互连结构 并且导电地耦合到第一有源区域中的第一源极/漏极区域和第二有源区域中的第二源极/漏极区域,并且形成覆盖第一和第二有源区域并且暴露至少一部分的图案化掩模层 的局部互连结构位于分离第一和第二有源区域的隔离区域之上。 该方法还包括通过图案化掩模层执行蚀刻工艺以移除局部互连结构的一部分,从而限定位于局部互连结构的剩余部分上方的凹槽,以及在凹部中形成绝缘材料。