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11. 发明申请

US20130237038A1 TWO-STEP HYDROGEN ANNEALING PROCESS FOR CREATING UNIFORM NON-PLANAR SEMICONDUCTOR DEVICES AT AGGRESSIVE PITCH 失效
标题翻译：两步氢化退火工艺，用于在均质玻璃板上形成均匀的非平面半导体器件
公开(公告)号：US20130237038A1
公开(公告)日：2013-09-12
申请号：US13414744
申请日：2012-03-08
申请人： Jeffrey W. Sleight , Sarunya Bangsaruntip
发明人： Jeffrey W. Sleight , Sarunya Bangsaruntip
IPC分类号： H01L21/20 , B82Y40/00
CPC分类号： H01L21/02104 , B82Y10/00 , B82Y40/00 , H01L21/3247 , H01L29/0673 , H01L29/42392 , H01L29/513 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： A two-step hydrogen anneal process has been developed for use in fabricating semiconductor nanowires for use in non-planar semiconductor devices. In the first part of the two-step hydrogen anneal process, which occurs prior to suspending a semiconductor nanowire, the initial roughness of at least the sidewalls of the semiconductor nanowire is reduced, while having at least the bottommost surface of the nanowire pinned to an uppermost surface of a substrate. After performing the first hydrogen anneal, the semiconductor nanowire is suspended and then a second hydrogen anneal is performed which further reduces the roughness of all exposed surfaces of the semiconductor nanowire and reshapes the semiconductor nanowire. By breaking the anneal into two steps, smaller semiconductor nanowires at a tight pitch survive the process and yield.
摘要翻译：已经开发了用于制造用于非平面半导体器件的半导体纳米线的两步骤氢退火工艺。在悬浮半导体纳米线之前发生的两步氢退火工艺的第一部分中，至少半导体纳米线的侧壁的初始粗糙度减小，同时至少将纳米线的最底表面固定到基板的最上表面。在执行第一氢退火之后，将半导体纳米线悬浮，然后执行第二氢退火，这进一步降低了半导体纳米线的所有暴露表面的粗糙度并重新形成了半导体纳米线。通过将退火分解为两个步骤，较窄的半导体纳米线在工艺和产量方面存在。

12. 发明授权

US08455334B2 Planar and nanowire field effect transistors 失效
标题翻译：平面和纳米线场效应晶体管
公开(公告)号：US08455334B2
公开(公告)日：2013-06-04
申请号：US12631342
申请日：2009-12-04
申请人： Sarunya Bangsaruntip , Guy M. Cohen , Shreesh Narasimha , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy M. Cohen , Shreesh Narasimha , Jeffrey W. Sleight
IPC分类号： H01L21/84
CPC分类号： H01L29/78696 , B82Y10/00 , B82Y40/00 , H01L21/84 , H01L27/1203 , H01L29/0665 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66469 , H01L29/66772
摘要： A method for forming an integrated circuit, the method includes forming a first nanowire suspended above an insulator substrate, the first nanowire attached to a first silicon on insulator (SOI) pad region and a second SOI pad region that are disposed on the insulator substrate, a second nanowire disposed on the insulator substrate attached to a third SOI pad region and a fourth SOI pad region that are disposed on the insulator substrate, and a SOI slab region that is disposed on the insulator substrate, and forming a first gate surrounding a portion of the first nanowire, a second gate on a portion of the second nanowire, and a third gate on a portion of the SOI slab region.
摘要翻译：一种用于形成集成电路的方法，所述方法包括形成悬置在绝缘体衬底上的第一纳米线，所述第一纳米线附接到绝缘体上的第一绝缘体（SOI）焊盘区域和设置在所述绝缘体衬底上的第二SOI焊盘区域，布置在绝缘体基板上的第二纳米线，其连接到设置在绝缘体基板上的第三SOI焊盘区域和第四SOI焊盘区域，以及SOI板状区域，其设置在绝缘体基板上，并且形成围绕部分的第一栅极的第一纳米线，第二纳米线的一部分上的第二栅极和SOI板区域的一部分上的第三栅极。

13. 发明申请

US20130105897A1 Nanowire FET and FINFET Hybrid Technology 失效
标题翻译：纳米线FET和FINFET混合技术
公开(公告)号：US20130105897A1
公开(公告)日：2013-05-02
申请号：US13286311
申请日：2011-11-01
申请人： Sarunya Bangsaruntip , Josephine B. Chang , Leland Chang , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Josephine B. Chang , Leland Chang , Jeffrey W. Sleight
IPC分类号： H01L27/12 , H01L21/8238
CPC分类号： H01L27/1211 , B82Y10/00 , B82Y40/00 , H01L21/3247 , H01L21/845 , H01L29/0673 , H01L29/42392 , H01L29/66469 , H01L29/78696
摘要： Hybrid nanowire FET and FinFET devices and methods for fabrication thereof are provided. In one aspect, a method for fabricating a CMOS circuit having a nanowire FET and a finFET includes the following steps. A wafer is provided having an active layer over a BOX. A first region of the active layer is thinned. An organic planarizing layer is deposited on the active layer. Nanowires and pads are etched in the first region of the active layer using a first hardmask. The nanowires are suspended over the BOX. Fins are etched in the second region of the active layer using a second hardmask. A first gate stack is formed that surrounds at least a portion of each of the nanowires. A second gate stack is formed covering at least a portion of each of the fins. An epitaxial material is grown on exposed portions of the nanowires, pads and fins.
摘要翻译：提供了混合纳米线FET和FinFET器件及其制造方法。一方面，制造具有纳米线FET和finFET的CMOS电路的方法包括以下步骤。提供了在BOX上具有活性层的晶片。有源层的第一区域变薄。有机平面化层沉积在有源层上。使用第一硬掩模在有源层的第一区域中蚀刻纳米线和焊盘。纳米线悬挂在BOX上。使用第二硬掩模在活性层的第二区域中蚀刻金箔。形成围绕每个纳米线的至少一部分的第一栅极堆叠。形成第二栅极堆叠，覆盖每个散热片的至少一部分。在纳米线，焊盘和鳍片的暴露部分上生长外延材料。

14. 发明申请

US20120280206A1 Nanowire Circuits in Matched Devices 有权
标题翻译：匹配器件中的纳米线电路
公开(公告)号：US20120280206A1
公开(公告)日：2012-11-08
申请号：US13554057
申请日：2012-07-20
申请人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
IPC分类号： H01L27/085 , H01L21/8232
CPC分类号： H03K19/20 , B82Y10/00 , G11C11/412 , G11C11/54 , H01L27/092 , H01L27/11 , H01L27/1104 , H01L27/12 , H01L29/0665 , H01L29/0673 , H01L29/775 , H01L29/78696
摘要： A memory device includes a first nanowire connected to a first bit line node and a ground node, a first field effect transistor (FET) having a gate disposed on the first nanowire, a second FET having a gate disposed on the first nanowire, a second nanowire connected to a voltage source node and a first input node, a third FET having a gate disposed on the second nanowire, a third nanowire connected to the voltage source node and a second input node, a fourth FET having a gate disposed on the third nanowire, a fourth nanowire connected to a second bit line node and the ground node, a fifth FET having a gate disposed on the fourth nanowire, and a sixth FET having a gate disposed on the fourth nanowire.
摘要翻译：存储器件包括连接到第一位线节点和接地节点的第一纳米线，具有设置在第一纳米线上的栅极的第一场效应晶体管（FET），具有设置在第一纳米线上的栅极的第二FET，连接到电压源节点和第一输入节点的纳米线，具有设置在第二纳米线上的栅极的第三FET，连接到电压源节点的第三纳米线和第二输入节点，具有设置在第三纳米线上的栅极的第四FET 纳米线，连接到第二位线节点的第四纳米线和所述接地节点，具有设置在所述第四纳米线上的栅极的第五FET以及设置在所述第四纳米线上的栅极的第六FET。

15. 发明授权

US08298881B2 Nanowire FET with trapezoid gate structure 有权
标题翻译：具有梯形栅极结构的纳米线FET
公开(公告)号：US08298881B2
公开(公告)日：2012-10-30
申请号：US12824293
申请日：2010-06-28
申请人： Jeffrey W. Sleight , Sarunya Bangsaruntip , Sebastian U. Engelmann , Ying Zhang
发明人： Jeffrey W. Sleight , Sarunya Bangsaruntip , Sebastian U. Engelmann , Ying Zhang
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/4232 , H01L29/513 , H01L29/66439
摘要： In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include forming a trapezoid gate structure surrounding at least a portion of a circumference of a nanowire. The first portion of the trapezoid gate structure that is in direct contact with an upper surface of the nanowire has a first width and a second portion of the trapezoid gate structure that is in direct contact with a lower surface of the nanowire has a second width. The second width of the trapezoid gate structure is greater than the first width of the trapezoid gate structure. The exposed portions of the nanowire that are adjacent to the portion of the nanowire that the trapezoid gate structure is surrounding are then doped to provide source and drain regions.
摘要翻译：在一个实施例中，提供了一种提供纳米线半导体器件的方法，其中对纳米线半导体器件的栅极结构具有梯形形状。该方法可以包括形成围绕纳米线的圆周的至少一部分的梯形栅极结构。与纳米线的上表面直接接触的梯形栅极结构的第一部分具有与纳米线的下表面直接接触的梯形栅极结构的第一宽度和第二部分具有第二宽度。梯形栅极结构的第二宽度大于梯形栅极结构的第一宽度。然后，与梯形栅极结构所围绕的部分纳米线相邻的纳米线的暴露部分被掺杂以提供源区和漏区。

16. 发明申请

US20110249489A1 Nanowire Circuits in Matched Devices 有权
标题翻译：匹配器件中的纳米线电路
公开(公告)号：US20110249489A1
公开(公告)日：2011-10-13
申请号：US12758939
申请日：2010-04-13
申请人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
IPC分类号： G11C11/00 , H01L21/8238 , H01L21/336 , H03K19/20
CPC分类号： H03K19/20 , B82Y10/00 , G11C11/412 , G11C11/54 , H01L27/092 , H01L27/11 , H01L27/1104 , H01L27/12 , H01L29/0665 , H01L29/0673 , H01L29/775 , H01L29/78696
摘要： An inverter device includes a first nanowire connected to a voltage source node and a ground node, a first p-type field effect transistor (pFET) device having a gate disposed on the first nanowire, and a first n-type field effect transistor (nFET) device having a gate disposed on the first nanowire.
摘要翻译：逆变器装置包括连接到电压源节点和接地节点的第一纳米线，具有设置在第一纳米线上的栅极的第一p型场效应晶体管（pFET）器件和第一n型场效应晶体管（nFET ）器件，其具有设置在第一纳米线上的栅极。

17. 发明申请

US20110133280A1 DIFFERENT THICKNESS OXIDE SILICON NANOWIRE FIELD EFFECT TRANSISTORS 失效
标题翻译：不同厚度的氧化硅纳米线场效应晶体管
公开(公告)号：US20110133280A1
公开(公告)日：2011-06-09
申请号：US12631148
申请日：2009-12-04
申请人： Sarunya Bangsaruntip , Andres Bryant , Guy M. Cohen , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Andres Bryant , Guy M. Cohen , Jeffrey W. Sleight
IPC分类号： H01L29/786 , H01L21/336 , H01L29/78
CPC分类号： H01L29/78696 , H01L29/42392
摘要： A method (that produces a structure) patterns at least two wires of semiconductor material such that a first wire of the wires has a larger perimeter than a second wire of the wires. The method performs an oxidation process simultaneously on the wires to form a first gate oxide on the first wire and a second gate oxide on the second wire. The first gate oxide is thicker than the second gate oxide. The method also forms gate conductors over the first gate oxide and the second gate oxide, forms sidewall spacers on the gate conductors, and dopes portions of the first wire and the second wire not covered by the sidewall spacers and the gate conductors to form source and drain regions within the first wire and the second wire.
摘要翻译：产生结构的方法（图案）至少形成两条半导体材料线，使得电线的第一线具有比电线的第二线更大的周长。该方法在导线上同时进行氧化处理，以在第一布线上形成第一栅极氧化物，在第二布线上形成第二栅极氧化物。第一栅极氧化物比第二栅极氧化物厚。该方法还在第一栅极氧化物和第二栅极氧化物上形成栅极导体，在栅极导体上形成侧壁间隔物，以及第一导线和第二导线的掺杂部分未被侧壁间隔物和栅极导体覆盖以形成源极和第一线和第二线内的漏极区。

18. 发明申请

US20110133165A1 SELF-ALIGNED CONTACTS FOR NANOWIRE FIELD EFFECT TRANSISTORS 有权
标题翻译：用于纳米效应晶体管的自对准接触
公开(公告)号：US20110133165A1
公开(公告)日：2011-06-09
申请号：US12631213
申请日：2009-12-04
申请人： Sarunya Bangsaruntip , Guy M. Cohen , Shreesh Narasimha , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy M. Cohen , Shreesh Narasimha , Jeffrey W. Sleight
IPC分类号： H01L29/66 , H01L21/336
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , H01L21/823418 , H01L29/0665 , H01L29/0673 , H01L29/42392 , H01L29/458 , H01L29/66439 , H01L29/66772 , H01L29/78696
摘要： A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a capping layer on the gate structure; forming a first spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, forming a hardmask layer on the capping layer and the first spacer, removing exposed portions of the nanowire, epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region, forming a silicide material in the epitaxially grown doped semiconductor material, and forming a conductive material on the source and drain regions.
摘要翻译：形成纳米线场效应晶体管（FET）器件的方法包括在半导体衬底上形成纳米线，在纳米线的一部分周围形成栅极结构，在栅极结构上形成覆盖层; 形成邻近所述栅极的侧壁和从所述栅极延伸的纳米线的周围的第一间隔物，在所述覆盖层和所述第一间隔物上形成硬掩模层，去除所述纳米线的暴露部分，在暴露的横截面上外延生长掺杂半导体材料以形成源极区和漏极区，在外延生长的掺杂半导体材料中形成硅化物材料，并在源极和漏极区上形成导电材料。

19. 发明授权

US07884004B2 Maskless process for suspending and thinning nanowires 有权
标题翻译：用于悬浮和稀化纳米线的无掩模工艺
公开(公告)号：US07884004B2
公开(公告)日：2011-02-08
申请号：US12365623
申请日：2009-02-04
申请人： Sarunya Bangsaruntip , Guy Cohen , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Jeffrey W. Sleight
IPC分类号： H01L21/00
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , H01L21/02488 , H01L21/02532 , H01L21/02603 , H01L21/0262 , H01L21/02639 , H01L21/02667 , H01L29/0665 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/78696 , Y10S977/762
摘要： Semiconductor-based electronic devices and techniques for fabrication thereof are provided. In one aspect, a device is provided comprising a first pad; a second pad and a plurality of nanowires connecting the first pad and the second pad in a ladder-like configuration formed in a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer, the nanowires having one or more dimensions defined by a re-distribution of silicon from the nanowires to the pads. The device can comprise a field-effect transistor (FET) having a gate surrounding the nanowires wherein portions of the nanowires surrounded by the gate form channels of the FET, the first pad and portions of the nanowires extending out from the gate adjacent to the first pad form a source region of the FET and the second pad and portions of the nanowires extending out from the gate adjacent to the second pad form a drain region of the FET.
摘要翻译：提供了基于半导体的电子器件及其制造技术。在一个方面，提供了一种包括第一垫的装置; 第二焊盘和多个纳米线，其以形成在掩埋氧化物（BOX）层上的绝缘体上硅（SOI）层中的梯形结构连接第一焊盘和第二焊盘，该纳米线具有一个或多个维度由硅从纳米线重新分配到焊盘。该器件可以包括具有围绕纳米线的栅极的场效应晶体管（FET），其中纳米线的部分由FET的栅极沟道围绕，第一焊盘和纳米线的部分从邻近第一焊盘形成FET的源极区域，并且第二焊盘和从与第二焊盘相邻的栅极延伸出的纳米线的部分形成FET的漏极区域。

20. 发明授权

US09184301B2 Planar and nanowire field effect transistors 有权
标题翻译：平面和纳米线场效应晶体管
公开(公告)号：US09184301B2
公开(公告)日：2015-11-10
申请号：US13600598
申请日：2012-08-31
申请人： Sarunya Bangsaruntip , Guy M. Cohen , Shreesh Narasimha , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy M. Cohen , Shreesh Narasimha , Jeffrey W. Sleight
IPC分类号： H01L29/66 , H01L29/786 , B82Y10/00 , B82Y40/00 , H01L21/84 , H01L27/12 , H01L29/06 , H01L29/423
CPC分类号： H01L29/78696 , B82Y10/00 , B82Y40/00 , H01L21/84 , H01L27/1203 , H01L29/0665 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66469 , H01L29/66772
摘要： An integrated circuit includes a plurality of gate-all-around (GAA) nanowire field effect transistors (FETs), a plurality of omega-gate nanowire FETs, and a plurality of planar channel FETs, wherein the plurality of GAA FETs, the plurality of omega-gate nanowire FETs, and the plurality of planar channel FETs are disposed on a single wafer.
摘要翻译：集成电路包括多个栅极全能（GAA）纳米线场效应晶体管（FET），多个Ω-栅极纳米线FET和多个平面沟道FET，其中多个GAA FET，多个 ω-门纳米线FET，并且多个平面沟道FET设置在单个晶片上。

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