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11. 发明授权

US6162721A Semiconductor processing methods 失效
标题翻译：半导体加工方法
公开(公告)号：US6162721A
公开(公告)日：2000-12-19
申请号：US183486
申请日：1998-10-30
申请人： Sanh Tang
发明人： Sanh Tang
IPC分类号： H01L23/522 , H01L21/28 , H01L21/768 , H01L21/822 , H01L23/485 , H01L27/04 , H01L29/417 , H01L21/44
CPC分类号： H01L29/417 , H01L21/76885 , H01L23/485 , H01L2924/0002 , Y10S257/903 , Y10S438/97 , H01L2924/00
摘要： A semiconductor processing method includes: a) providing a substrate having a base region to which electrical connection is to be made; b) providing a first layer of a conductive first material; c) providing an etch stop layer over the first layer; d) etching a contact opening through the etch stop and first layers to the base region; e) providing a second layer of first material outwardly of the etch stop layer and within the contact opening to a thickness greater than the first layer thickness and extending outwardly beyond the contact opening upper edge; f) removing first material of the second layer and defining a second layer plug within the contact, the second layer plug having an outermost surface extending outwardly beyond the contact opening upper edge and thereby providing the second layer plug to be of greater thickness than the first layer; g) masking outwardly of the first layer and the second layer plug to define a mask pattern for definition of a circuit component from the first layer which connects with the base region through the second layer plug; and h) etching unmasked portions of the first layer and second layer plug to define a circuit component which connects with the base region through the second layer plug, the greater thickness of the second layer plug as compared to the thickness of the first layer restricting etching into the base region during etching. Integrated circuitry is also disclosed.
摘要翻译：半导体处理方法包括：a）提供具有要与其进行电连接的基极区域的基板; b）提供第一层导电第一材料; c）在第一层上提供蚀刻停止层; d）通过蚀刻停止层和第一层蚀刻到基底区域的接触开口; e）在所述蚀刻停止层的外部和所述接触开口内提供第二层第一材料，其厚度大于所述第一层厚度并向外延伸超出所述接触开口上边缘; f）去除第二层的第一材料并在接触件内限定第二层塞，第二层塞具有向外延伸超过接触开口上边缘的最外表面，从而使第二层塞具有比第一层层; g）从第一层和第二层插塞向外掩蔽，以限定掩模图案，用于定义来自第一层的电路部件，该第一层通过第二层插塞与基部区域连接; 以及h）蚀刻所述第一层和第二层插塞的未屏蔽部分以限定通过所述第二层插塞与所述基底区域连接的电路部件，所述第二层插塞的厚度与所述第一层限制蚀刻的厚度相比较大在蚀刻期间进入基底区域。还公开了集成电路。

12. 发明授权

US6160296A Titanium nitride interconnects 有权
标题翻译：氮化钛互连
公开(公告)号：US6160296A
公开(公告)日：2000-12-12
申请号：US338211
申请日：1999-06-22
申请人： Michael P. Violette , Sanh Tang , Daniel M. Smith
发明人： Michael P. Violette , Sanh Tang , Daniel M. Smith
IPC分类号： H01L21/3205 , H01L21/3213 , H01L21/768 , H01L29/76 , H01L23/48 , H01L29/94
CPC分类号： H01L21/76855 , H01L21/32053 , H01L21/32137 , H01L21/76843 , H01L21/76846 , H01L21/76895
摘要： A method for use in the fabrication of semiconductor devices includes forming a titanium nitride film and depositing a silicon hard mask over the titanium nitride film. The silicon hard mask is used to pattern a titanium nitride interconnect from the titanium nitride film and the silicon hard mask is also used as a contact etch stop for forming a contact area. In forming the interconnect, the silicon hard mask is dry etched stopping selectively on and exposing portions of the titanium nitride film and the exposed portions of the titanium nitride film are etched resulting in the titanium nitride interconnect. In using the silicon hard mask as a contact etch stop, an insulating layer is deposited over the silicon hard mask and the insulating layer is etched using the silicon hard mask as an etch stop to form the contact area. The silicon hard mask is then converted to a metal silicide contact area. Interconnects formed using the method are also described.
摘要翻译：用于制造半导体器件的方法包括在氮化钛膜上形成氮化钛膜并沉积硅硬掩模。硅硬掩模用于从氮化钛膜图案化氮化钛互连，并且硅硬掩模也用作用于形成接触区域的接触蚀刻停止。在形成互连件时，将硅硬掩模干蚀刻选择性地停止并暴露氮化钛膜的部分，并且氮化钛膜的暴露部分被蚀刻，导致氮化钛互连。在使用硅硬掩模作为接触蚀刻停止件时，在硅硬掩模上沉积绝缘层，并且使用硅硬掩模作为蚀刻停止层来蚀刻绝缘层以形成接触区域。然后将硅硬掩模转换成金属硅化物接触区域。还描述了使用该方法形成的互连。

13. 发明申请

US20080099847A1 Integrated Circuits and Methods of Forming a Field Effect Transistor 有权
标题翻译：集成电路和形成场效应晶体管的方法
公开(公告)号：US20080099847A1
公开(公告)日：2008-05-01
申请号：US11957013
申请日：2007-12-14
申请人： Sanh Tang , Gordon Haller
发明人： Sanh Tang , Gordon Haller
IPC分类号： H01L29/786
CPC分类号： H01L29/0653 , H01L21/0237 , H01L21/02532 , H01L21/02595 , H01L21/0262 , H01L21/823412 , H01L21/823418 , H01L21/823481 , H01L21/84 , H01L27/1203
摘要： Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material. Electrically insulative material is received within the bulk semiconductive material. Semiconductor material is formed on the insulative material. A field effect transistor is included and comprises a gate, a channel region, and a pair of source/drain regions. In one implementation, one of the source/drain regions is formed in the semiconductor material, and the other of the source/drain regions is formed in the bulk semiconductive material. In one implementation, the electrically insulative material extends from beneath one of the source/drain regions to beneath only a portion of the channel region. Other aspects and implementations, including methodical aspects, are disclosed.
摘要翻译：公开了形成场效应晶体管的集成电路和方法。在一个方面，集成电路包括包括本体半导体材料的半导体衬底。电绝缘材料容纳在本体半导体材料内。在绝缘材料上形成半导体材料。包括场效应晶体管，并包括栅极，沟道区和一对源极/漏极区。在一个实施方案中，源/漏区中的一个形成在半导体材料中，并且源/漏区中的另一个在体半导体材料中形成。在一个实施方案中，电绝缘材料从源极/漏极区域之一延伸到仅沟道区域的仅一部分的下方。公开了其他方面和实施方式，包括方法方面。

14. 发明申请

US20070264771A1 Dual work function recessed access device and methods of forming 有权
标题翻译：双功能凹槽接入设备及其成型方法
公开(公告)号：US20070264771A1
公开(公告)日：2007-11-15
申请号：US11432270
申请日：2006-05-11
申请人： Venkatesan Ananthan , Sanh Tang
发明人： Venkatesan Ananthan , Sanh Tang
IPC分类号： H01L21/8242
CPC分类号： H01L29/7827 , H01L29/42376 , H01L29/4966 , H01L29/66621
摘要： A recessed access device having a gate electrode formed of two or more gate materials having different work functions may reduce the gate-induced drain leakage current losses from the recessed access device. The gate electrode may include a first gate material having a high work function disposed in a bottom portion of the recessed access device and a second gate material having a lower work function disposed over the first gate material and in an upper portion of the recessed access device.
摘要翻译：具有由具有不同功函数的两个或多个栅极材料形成的栅电极的凹陷存取装置可以减小来自凹陷存取装置的栅极引起的漏极漏电流损耗。栅电极可以包括具有设置在凹陷入口装置的底部中的高功函的第一栅极材料和具有设置在第一栅极材料上的下功函数的第二栅极材料以及凹陷入口装置的上部。

15. 发明申请

US20070066040A1 Microfeature workpieces and methods of forming a redistribution layer on microfeature workpieces 审中-公开
标题翻译：微型工件和在微型工件上形成再分布层的方法
公开(公告)号：US20070066040A1
公开(公告)日：2007-03-22
申请号：US11603816
申请日：2006-11-21
申请人： Sanh Tang , Troy Gugel , John Lee , Fred Fishburn
发明人： Sanh Tang , Troy Gugel , John Lee , Fred Fishburn
IPC分类号： H01L21/28 , H01L23/48
CPC分类号： H01L23/3114 , H01L24/05 , H01L24/11 , H01L24/12 , H01L2224/0231 , H01L2224/02311 , H01L2224/0401 , H01L2224/04073 , H01L2224/05082 , H01L2224/05181 , H01L2224/0558 , H01L2224/05624 , H01L2224/05647 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要： Methods for forming a redistribution layer on microfeature workpieces, and microfeature workpieces having such a redistribution layer are disclosed herein. In one embodiment, a method includes constructing a dielectric structure on a microfeature workpiece having a substrate and a terminal carried by the substrate, and removing a section of the dielectric structure to form an opening. The opening has a first portion extending through the dielectric structure and exposing the terminal and a second portion extending to an intermediate depth in the dielectric structure. The second portion is spaced laterally apart from the terminal. The method further includes forming a conductive layer on the microfeature workpiece with the conductive layer in electrical contact with the terminal and disposed in the first and second portions of the opening.
摘要翻译：在微型工件上形成再分布层的方法以及具有这种再分配层的微特征工件在此公开。在一个实施例中，一种方法包括在具有衬底和由衬底承载的端子的微特征工件上构造电介质结构，以及去除电介质结构的一部分以形成开口。开口具有延伸穿过电介质结构并且暴露端子的第一部分和延伸到电介质结构中的中间深度的第二部分。第二部分与端子横向间隔开。该方法还包括在微特征工件上形成导电层，导电层与端子电接触并设置在开口的第一和第二部分中。

16. 发明申请

US20070051997A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20070051997A1
公开(公告)日：2007-03-08
申请号：US11218184
申请日：2005-08-31
申请人： Gordon Haller , Sanh Tang , Steve Cummings
发明人： Gordon Haller , Sanh Tang , Steve Cummings
IPC分类号： H01L29/94 , H01L21/8242
CPC分类号： H01L21/823487 , H01L27/10817 , H01L27/10823 , H01L27/10876 , H01L27/10888
摘要： A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.
摘要翻译：包括垂直晶体管的存储器件包括直接耦合到每个存储器单元的源极区域的数字线。由于不使用电插头来形成数字线和源极区之间的接触，所以可以减少多个制造步骤，并且还可以减少制造缺陷的可能性。在一些实施例中，存储器件可以包括垂直晶体管，其具有从硅衬底的上部凹陷的栅极区域。随着从硅衬底凹入的栅极区域，栅极区域与源极/漏极区域进一步间隔开，因此，可以减小栅极区域和源极/漏极区域之间的交叉电容。

17. 发明申请

US20070045712A1 Memory cell layout and process flow 有权
标题翻译：存储单元格布局和流程
公开(公告)号：US20070045712A1
公开(公告)日：2007-03-01
申请号：US11219349
申请日：2005-09-01
申请人： Gordon Haller , David Hwang , Sanh Tang , Ceredig Roberts
发明人： Gordon Haller , David Hwang , Sanh Tang , Ceredig Roberts
IPC分类号： H01L29/788
CPC分类号： H01L21/3088 , H01L21/0338 , H01L27/0207 , H01L27/10891 , H01L27/10894
摘要： A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are defined by a first pitch, with one word line located between each drain and the source. Digit lines are defined by a second pitch, one of the digit lines being coupled to the source and forming a second axis. The active areas of the memory array are tilted at 45° to the grid defined by the word lines and digit lines. The word line pitch is about 1.5 F, while the digit line pitch is about 3 F.
摘要翻译：存储器件包括有源区域，其包括源极和限定第一轴线的至少两个漏极。至少两个基本上平行的字线由第一间距限定，一个字线位于每个漏极和源之间。数字线由第二间距限定，其中一个数字线耦合到源并形成第二轴。存储器阵列的有效区域与由字线和数字线限定的栅格倾斜45°。字线间距约为1.5 F，而数字线间距约为3 F。

18. 发明申请

US20060046424A1 Methods of forming semiconductor constructions 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US20060046424A1
公开(公告)日：2006-03-02
申请号：US10925789
申请日：2004-08-24
申请人： Randal Chance , Gordon Haller , Sanh Tang , Steven Cummings
发明人： Randal Chance , Gordon Haller , Sanh Tang , Steven Cummings
IPC分类号： H01L21/76
CPC分类号： H01L29/66666 , H01L21/823437 , H01L21/823487 , H01L27/10808 , H01L27/10876 , H01L29/42368 , H01L29/512 , H01L29/7827
摘要： The invention includes semiconductor constructions containing vertically-extending pillars, and methods for forming such constructions. The vertically-extending pillars can be incorporated into transistor devices, and can contain vertically-extending channel regions of the transistor devices. The transistor devices can be incorporated into integrated circuitry, and in some aspects are incorporated into memory constructions, such as, for example, dynamic random access memory (DRAM) constructions.
摘要翻译：本发明包括包含垂直延伸柱的半导体结构以及用于形成这种结构的方法。垂直延伸的柱可以并入晶体管器件中，并且可以包含晶体管器件的垂直延伸的沟道区域。晶体管器件可以并入到集成电路中，并且在一些方面被并入存储器结构中，例如动态随机存取存储器（DRAM）结构。

19. 发明授权

US5945350A Methods for use in formation of titanium nitride interconnects and interconnects formed using same 失效
标题翻译：用于形成氮化钛互连的方法和使用其形成的互连
公开(公告)号：US5945350A
公开(公告)日：1999-08-31
申请号：US710175
申请日：1996-09-13
申请人： Michael P. Violette , Sanh Tang , Daniel M. Smith
发明人： Michael P. Violette , Sanh Tang , Daniel M. Smith
IPC分类号： H01L21/3205 , H01L21/3213 , H01L21/768 , H01L21/3065 , H01L21/324
CPC分类号： H01L21/76855 , H01L21/32053 , H01L21/32137 , H01L21/76843 , H01L21/76846 , H01L21/76895
摘要： A method for use in the fabrication of semiconductor devices includes forming a titanium nitride film and depositing a silicon hard mask over the titanium nitride film. The silicon hard mask is used to pattern a titanium nitride interconnect from the titanium nitride film and the silicon hard mask is also used as a contact etch stop for forming a contact area. In forming the interconnect, the silicon hard mask is dry etched stopping selectively on and exposing portions of the titanium nitride film and the exposed portions of the titanium nitride film are etched resulting in the titanium nitride interconnect. In using the silicon hard mask as a contact etch stop, an insulating layer is deposited over the silicon hard mask and the insulating layer is etched using the silicon hard mask as an etch stop to form the contact area. The silicon hard mask is then converted to a metal silicide contact area. Interconnects formed using the method are also described.
摘要翻译：用于制造半导体器件的方法包括在氮化钛膜上形成氮化钛膜并沉积硅硬掩模。硅硬掩模用于从氮化钛膜图案化氮化钛互连，并且硅硬掩模也用作用于形成接触区域的接触蚀刻停止。在形成互连件时，将硅硬掩模干蚀刻选择性地停止并暴露氮化钛膜的部分，并且氮化钛膜的暴露部分被蚀刻，导致氮化钛互连。在使用硅硬掩模作为接触蚀刻停止件时，在硅硬掩模上沉积绝缘层，并且使用硅硬掩模作为蚀刻停止层来蚀刻绝缘层以形成接触区域。然后将硅硬掩模转换成金属硅化物接触区域。还描述了使用该方法形成的互连。

20. 发明授权

US5585285A Method of forming dynamic random access memory circuitry using SOI and isolation trenches 失效
标题翻译：使用SOI和隔离沟槽形成动态随机存取存储器电路的方法
公开(公告)号：US5585285A
公开(公告)日：1996-12-17
申请号：US568356
申请日：1995-12-06
申请人： Sanh Tang
发明人： Sanh Tang
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L27/12
CPC分类号： H01L27/10861 , H01L27/10829 , H01L27/1203 , H01L28/40
摘要： A semiconductor processing method of forming dynamic random access memory circuitry includes, a) providing an electrically conductive capacitor cell plate substrate; b) providing an electrically insulative layer over the cell plate; c) providing a layer of semiconductive material on the insulative layer thereby defining a semiconductor-on-insulator (SOI) layer; d) patterning and etching the SOI layer to define active area region islands and isolation trenches between the islands; e) filling the isolation trenches with insulative material; f) providing capacitor openings through the SOI layer and insulative layer into the cell plate substrate; g) providing a capacitor dielectric layer over the cell plate substrate within the capacitor openings; h) providing respective capacitor storage nodes over the dielectric layer within the capacitor openings, the respective storage nodes being in ohmic connection with the SOI layer; i) after providing the storage nodes, filling any remaining portions of the capacitor container openings with insulative material; j) providing a gate dielectric layer atop the SOI layer islands; k) providing conductive word lines over the gate dielectric layer on the islands and over the filled isolation trenches; l) providing opposing FET source and drain regions within the SOI layer; and m) providing bit lines outwardly of the word lines, the bit lines connecting with selected drain regions. Also contemplated is a DRAM array having sources and drains formed within an SOI layer, wherein capacitors of the array comprise trenches formed within a monocrystalline substrate, with the substrate comprising a common cell plate of the capacitors.
摘要翻译：形成动态随机存取存储器电路的半导体处理方法包括：a）提供导电电容器单元板基板; b）在电池板上提供电绝缘层; c）在绝缘层上提供半导体材料层，从而限定绝缘体上半导体（SOI）层; d）图案化和蚀刻SOI层以限定岛之间的有源区域岛和隔离沟槽; e）用绝缘材料填充隔离沟; f）提供通过SOI层和绝缘层的电容器开口进入电池板衬底; g）在电容器开口内的电池板衬底上提供电容器电介质层; h）在电容器开口内的电介质层上提供相应的电容器存储节点，各个存储节点与SOI层欧姆连接; i）在提供存储节点之后，用绝缘材料填充电容器容器开口的剩余部分; j）在SOI层岛顶上提供栅介质层; k）在岛上的栅极电介质层和填充的隔离沟槽之上提供导电字线; l）在SOI层内提供相对的FET源极和漏极区域; 并且m）在字线外部提供位线，位线与选择的漏极区域连接。还考虑了具有形成在SOI层内的源极和漏极的DRAM阵列，其中阵列的电容器包括形成在单晶衬底内的沟槽，衬底包括电容器的公共电池板。

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