专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07928498B2 Gate structures in semiconductor devices 有权
标题翻译：半导体器件中的栅极结构
公开(公告)号：US07928498B2
公开(公告)日：2011-04-19
申请号：US12428303
申请日：2009-04-22
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L27/10873 , H01L29/4941 , H01L29/517
摘要： A gate structure includes an insulation layer on a substrate, a first conductive layer pattern on the insulation layer, a metal ohmic layer pattern on the first conductive layer pattern, a diffusion preventing layer pattern on the metal ohmic layer pattern, an amorphous layer pattern on the diffusion preventing layer pattern, and a second conductive layer pattern on the amorphous layer pattern. The gate structure may have a low sheet resistance and desired thermal stability.
摘要翻译：栅极结构包括在衬底上的绝缘层，绝缘层上的第一导电层图案，第一导电层图案上的金属欧姆层图案，金属欧姆层图案上的扩散防止层图案，扩散防止层图案和非晶层图案上的第二导电层图案。栅极结构可以具有低的薄层电阻和期望的热稳定性。

12. 发明授权

US07879737B2 Methods for fabricating improved gate dielectrics 有权
标题翻译：制造改进的栅极电介质的方法
公开(公告)号：US07879737B2
公开(公告)日：2011-02-01
申请号：US12801115
申请日：2010-05-24
申请人： Woong-Hee Sohn , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Tae-Ho Cha , Hee-Sook Park , Jae-Hwa Park , Geum-Jung Seong
发明人： Woong-Hee Sohn , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Tae-Ho Cha , Hee-Sook Park , Jae-Hwa Park , Geum-Jung Seong
IPC分类号： H01L21/31
CPC分类号： H01L21/823481 , H01L21/28202 , H01L21/28211 , H01L21/2822 , H01L29/518 , H01L29/66545 , H01L29/78 , Y10S438/981
摘要： Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.
摘要翻译：公开了用于增加栅极电介质图案的外围或边缘区域中的相对厚度以抑制这些区域的泄漏的各种方法。这些方法提供了常规GPOX工艺的替代方案，并提供改进的耐漏电性，而不会导致与GPOX工艺相关的增加的栅电极电阻的程度。每种方法包括形成第一开口以暴露有源区域区域，在暴露部分上形成氧化控制区域，然后形成第二开口，由此暴露氧化控制区域的外围区域以形成栅极介电层。得到的栅极介电层的特征在于由较厚的外围区域包围或界定的较薄的中心区域。

13. 发明授权

US07585787B2 Semiconductor memory device and method of manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07585787B2
公开(公告)日：2009-09-08
申请号：US11648595
申请日：2007-01-03
申请人： Tae-Ho Cha , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jang-Hee Lee , Geum-Jung Seong
发明人： Tae-Ho Cha , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jang-Hee Lee , Geum-Jung Seong
IPC分类号： H01L21/469
CPC分类号： H01L29/4941 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11536 , H01L27/11568 , H01L29/513
摘要： A semiconductor memory device, e.g., a charge trapping type non-volatile memory device, may include a charge trapping structure formed in a first area of a substrate and a gate structure formed in a second area of the substrate. The charge trapping structure may include a tunnel oxide layer pattern, a charge trapping layer pattern and a dielectric layer pattern of aluminum-containing tertiary metal oxide. The gate structure may include a gate oxide layer pattern, a polysilicon layer pattern and an ohmic layer pattern of aluminum-containing tertiary metal silicide. A first electrode and a second electrode may be formed on the charge trapping structure. A lower electrode and an upper electrode may be provided on the gate structure. The dielectric layer pattern may have a higher dielectric constant, and the ohmic layer pattern may have improved thermal stability, thereby enhancing programming and erasing operations of the charge trapping type non-volatile memory device.
摘要翻译：半导体存储器件，例如电荷俘获型非易失性存储器件，可以包括形成在衬底的第一区域中的电荷俘获结构和形成在衬底的第二区域中的栅极结构。电荷捕获结构可以包括隧道氧化物层图案，电荷俘获层图案和含铝三级金属氧化物的介电层图案。栅极结构可以包括栅极氧化物层图案，多晶硅层图案和含铝三次金属硅化物的欧姆层图案。第一电极和第二电极可以形成在电荷捕获结构上。可以在栅极结构上设置下电极和上电极。电介质层图案可以具有更高的介电常数，并且欧姆层图案可以具有改善的热稳定性，从而增强电荷俘获型非易失性存储器件的编程和擦除操作。

14. 发明申请

US20080211038A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080211038A1
公开(公告)日：2008-09-04
申请号：US11965420
申请日：2007-12-27
申请人： Jong-Ho Yun , Gil-Heyun Choi , Byung-Hee Kim , Hyun-Su Kim , Eun-Ok Lee
发明人： Jong-Ho Yun , Gil-Heyun Choi , Byung-Hee Kim , Hyun-Su Kim , Eun-Ok Lee
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L21/28097 , H01L29/4975 , H01L29/66545
摘要： A method of fabricating a semiconductor device includes forming a preliminary gate pattern on a semiconductor substrate. The preliminary gate pattern includes a gate oxide pattern, a conductive pattern, and a sacrificial insulating pattern. The method further includes forming spacers on opposite sidewalls of the preliminary gate pattern, forming an interlayer dielectric pattern to expose the sacrificial insulating pattern, removing the sacrificial insulating pattern to form an opening to expose the conductive pattern, transforming the conductive pattern into a metal silicide layer and forming a metal barrier pattern along an inner profile of the opening and a metal conductive pattern to fill the opening including the metal barrier pattern. The metal silicide layer and the metal conductive pattern constitute a gate electrode.
摘要翻译：制造半导体器件的方法包括在半导体衬底上形成初步栅极图案。初步栅极图案包括栅极氧化物图案，导电图案和牺牲绝缘图案。该方法还包括在初步栅极图案的相对侧壁上形成间隔物，形成层间电介质图案以暴露牺牲绝缘图案，去除牺牲绝缘图案以形成露出导电图案的开口，将导电图案转变为金属硅化物并且沿着开口的内部轮廓形成金属阻挡图案和金属导电图案以填充包括金属阻挡图案的开口。金属硅化物层和金属导电图案构成栅电极。

15. 发明申请

US20060263966A1 Methods of forming electronic devices including high-K dielectric layers and electrode barrier layers and related structures 有权
标题翻译：形成包括高K电介质层和电极阻挡层及相关结构的电子器件的方法
公开(公告)号：US20060263966A1
公开(公告)日：2006-11-23
申请号：US11479551
申请日：2006-06-30
申请人： Byung-Hee Kim , Gil-Heyun Choi , Kyung-In Choi , Chang-Won Lee
发明人： Byung-Hee Kim , Gil-Heyun Choi , Kyung-In Choi , Chang-Won Lee
IPC分类号： H01L21/8238
CPC分类号： H01L21/28088 , H01L21/28194 , H01L21/823857 , H01L29/4966 , H01L29/517 , H01L29/6656 , H01L29/66583 , H01L29/6659 , H01L29/7833
摘要： Methods of forming a microelectronic device can include providing a gate dielectric layer on a channel region of a semiconductor substrate wherein the gate dielectric layer is a high-k dielectric material. A gate electrode barrier layer can be provided on the gate dielectric layer opposite the channel region of the semiconductor substrate, and a gate electrode metal layer can be provided on the gate electrode barrier layer opposite the channel region of the semiconductor substrate. The gate electrode barrier layer and the gate electrode metal layer can be formed of different materials. Moreover, the gate electrode metal layer can include a first material and the gate electrode barrier layer can include a second material, and the first material can have a lower electrical resistivity than the second material.
摘要翻译：形成微电子器件的方法可以包括在半导体衬底的沟道区上提供栅极电介质层，其中栅极电介质层是高k电介质材料。可以在与半导体衬底的沟道区相对的栅极电介质层上设置栅电极阻挡层，并且可以在与半导体衬底的沟道区相对的栅极电极阻挡层上设置栅电极金属层。栅电极阻挡层和栅电极金属层可以由不同的材料形成。此外，栅电极金属层可以包括第一材料，并且栅电极阻挡层可以包括第二材料，并且第一材料可以具有比第二材料更低的电阻率。

16. 发明授权

US07067420B2 Methods for forming a metal layer on a semiconductor 有权
标题翻译：在半导体上形成金属层的方法
公开(公告)号：US07067420B2
公开(公告)日：2006-06-27
申请号：US10404360
申请日：2003-04-01
申请人： Kyung-In Choi , Gil-Heyun Choi , Byung-Hee Kim , Sang-Bum Kang
发明人： Kyung-In Choi , Gil-Heyun Choi , Byung-Hee Kim , Sang-Bum Kang
IPC分类号： H10L21/4763 , H10L21/20 , H10L21/44
CPC分类号： H01L21/76843 , C23C16/34 , C23C16/45542 , C23C16/45553 , H01L21/28562 , H01L21/32051 , H01L21/76877
摘要： A metal layer is formed on an integrated circuit device including forming an insulating layer on an integrated circuit substrate. A contact hole is formed by selectively etching the insulating layer to thereby partially expose the substrate. A metal layer including tantalum nitride is formed on the insulating layer including the contact hole using a tantalum precursor including a tantalum element and at least one bonding element that is chemically bonded to the tantalum element. A part of the at least one bonding element include at least one ligand bonding element that is ligand-bonded to the tantalum element. Forming the metal layer may include removing at least some of the ligand bonded elements with a removing gas that is substantially free of hydrogen radicals. The metal layer may be formed using a chemical vapor deposition (CVD) or an atomic layer deposition (ALD) process. A copper or other metal layer may be deposited on the metal layer including tantalum nitride.
摘要翻译：金属层形成在集成电路器件上，包括在集成电路衬底上形成绝缘层。通过选择性地蚀刻绝缘层从而部分地暴露衬底而形成接触孔。包括氮化钽的金属层使用包括钽元素的钽前体和与钽元素化学键合的至少一个结合元件在包括接触孔的绝缘层上形成。至少一个键合元件的一部分包括与钽元素配位键合的至少一个配体结合元件。形成金属层可以包括用基本上不含氢自由基的去除气体去除至少一些配体键合元件。可以使用化学气相沉积（CVD）或原子层沉积（ALD）工艺来形成金属层。可以在包括氮化钽的金属层上沉积铜或其它金属层。

17. 发明授权

US07989892B2 Gate structure, and semiconductor device having a gate structure 有权
标题翻译：栅极结构和具有栅极结构的半导体器件
公开(公告)号：US07989892B2
公开(公告)日：2011-08-02
申请号：US12483761
申请日：2009-06-12
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Jong-Min Baek , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Hee-Sook Park
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Jong-Min Baek , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Hee-Sook Park
IPC分类号： H01L21/44
CPC分类号： H01L29/4933 , H01L21/28061 , H01L27/10873
摘要： A gate structure can include a polysilicon layer, a metal layer on the polysilicon layer, a metal silicide nitride layer on the metal layer and a silicon nitride mask on the metal silicide nitride layer.
摘要翻译：栅极结构可以包括多晶硅层，多晶硅层上的金属层，金属层上的金属硅化物氮化物层和金属硅化物氮化物层上的氮化硅掩模。

18. 发明授权

US07550353B2 Method of forming semiconductor device 有权
标题翻译：半导体器件形成方法
公开(公告)号：US07550353B2
公开(公告)日：2009-06-23
申请号：US11685644
申请日：2007-03-13
申请人： Byung-Hak Lee , Woong-Hee Sohn , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park
发明人： Byung-Hak Lee , Woong-Hee Sohn , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park
IPC分类号： H01L21/8236
CPC分类号： H01L21/28282 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/11568
摘要： One embodiment of a method for forming a semiconductor device can include forming a gate pattern on a semiconductor substrate and performing a selective re-oxidation process on the gate pattern in gas ambient including hydrogen, oxygen, and nitrogen. When the gate pattern includes a tunnel insulation layer, a metal nitride layer and a metal layer, the selective re-oxidation process heals the etching damage of a gate pattern and simultaneously prevents oxidation of the metal nitride layer and a tungsten electrode.
摘要翻译：用于形成半导体器件的方法的一个实施例可以包括在半导体衬底上形成栅极图案，并且在包括氢，氧和氮在内的气体环境中对栅极图案进行选择性再氧化处理。当栅极图案包括隧道绝缘层，金属氮化物层和金属层时，选择性再氧化工艺会修复栅极图案的蚀刻损伤，同时防止金属氮化物层和钨电极的氧化。

19. 发明申请

US20080121983A1 Gate and method of forming the same, and memory device and method of manufacturing the same 审中-公开
标题翻译：门及其形成方法，以及存储器件及其制造方法
公开(公告)号：US20080121983A1
公开(公告)日：2008-05-29
申请号：US11606899
申请日：2006-12-01
申请人： Geum-Jung Seong , Gil-Heyun Choi , Byung-Hee Kim , Tae-Ho Cha , Hee-Sook Park , Jang-Hee Lee
发明人： Geum-Jung Seong , Gil-Heyun Choi , Byung-Hee Kim , Tae-Ho Cha , Hee-Sook Park , Jang-Hee Lee
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/792 , H01L27/105 , H01L27/11568 , H01L27/11573 , H01L29/40117 , H01L29/4234
摘要： A gate of a memory device may include a charge trapping structure having a tunnel oxide layer, a charge storing layer, and a blocking layer on a semiconductor substrate; a conductive pattern on the charge trapping structure, the conductive pattern including metal nitride; an ohmic film on the conductive pattern; and a gate electrode on the ohmic film.
摘要翻译：存储器件的栅极可以包括在半导体衬底上具有隧道氧化物层，电荷存储层和阻挡层的电荷俘获结构; 电荷捕获结构上的导电图案，导电图案包括金属氮化物; 导电图案上的欧姆膜; 和欧姆膜上的栅电极。

20. 发明授权

US07211769B2 Heating chamber and method of heating a wafer 有权
标题翻译：加热室和加热晶片的方法
公开(公告)号：US07211769B2
公开(公告)日：2007-05-01
申请号：US10115111
申请日：2002-04-01
申请人： Byung-Hee Kim , Jong-Myeong Lee , Myoung-Bum Lee , Ju-Young Yun , Gil-Heyun Choi
发明人： Byung-Hee Kim , Jong-Myeong Lee , Myoung-Bum Lee , Ju-Young Yun , Gil-Heyun Choi
IPC分类号： F27B5/14
CPC分类号： H01L21/67109 , C30B25/10 , C30B31/14
摘要： A heating chamber which can be used during a reflow process to form a metal wiring having a multi-layered writing structure and a method of heating a wafer using the same, are provided. The heating chamber is movable upward and downward between the upper process position and the lower loading position, and includes a pedestal having a supporting surface for supporting a wafer, a cover installed above the pedestal to form a processing area together with the supporting surface when the pedestal is placed in its raised process position and a heating unit for heating the waver. In the method of heating the wafer, the temperature in the processing area is maintained suitable for heating the wafer before the wafer is loaded onto the supporting surface, the wafer is loaded onto the supporting surface and the loaded wafer is heating in the processing area.
摘要翻译：提供了可以在回流工艺期间使用以形成具有多层书写结构的金属布线的加热室和使用其加热晶片的方法。加热室可以在上部处理位置和下部装载位置之间上下移动，并且包括具有用于支撑晶片的支撑表面的基座，安装在基座上方的盖子，当与该支撑表面一起形成处理区域时基座放置在其升高的处理位置和用于加热摇摆的加热单元。在加热晶片的方法中，在将晶片加载到支撑表面之前，处理区域中的温度保持适于加热晶片，晶片被加载到支撑表面上，并且加载的晶片在处理区域中被加热。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式