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11. 发明授权

US06587388B2 Method and apparatus for reducing write operation time in dynamic random access memories 失效
公开(公告)号：US06587388B2
公开(公告)日：2003-07-01
申请号：US09844837
申请日：2001-04-27
申请人： Toshiaki Kirihata , Sang Hoo Dhong , Hwa-Joon Oh
发明人： Toshiaki Kirihata , Sang Hoo Dhong , Hwa-Joon Oh
IPC分类号： G11C700
CPC分类号： G11C7/22 , G11C11/4076
摘要： A method for preparing a dynamic random access memory (DRAM) cell for a write operation with a preset condition is disclosed. In an exemplary embodiment, the method includes creating a preset voltage level within the cell prior to a delayed write back in a destructive read architecture, which preset voltage level has a value between a logic 0 voltage level and a logic 1 voltage level. The logic 0 voltage level corresponds to a first cell voltage value when the cell has a 0 bit stored therein, and the logic 1 voltage level corresponds to a second cell voltage value when the cell has a 1 bit stored therein. Prior to the creation of the preset voltage level within the cell, the cell has an initial voltage value corresponding to either the logic 0 voltage level or the logic 1 voltage level.

12. 发明授权

US06510093B1 Method and apparatus for cycle time reduction in a memory system using alternating reference cells and isolated sense lines 失效
标题翻译：使用交替参考单元和隔离感测线的存储器系统中的周期时间减少的方法和装置
公开(公告)号：US06510093B1
公开(公告)日：2003-01-21
申请号：US09982163
申请日：2001-10-18
申请人： Sang Hoo Dhong , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Hwa-Joon Oh
IPC分类号： G11C700
CPC分类号： G11C7/12 , G11C7/14 , G11C11/4076 , G11C11/4094 , G11C11/4099
摘要： In one aspect, reading a memory includes conductively coupling a memory cell and a first reference cell to respective lines of a selected bit line pair for a voltage development interval. During the interval a voltage differential develops on the bit line pair and is transmitted to a corresponding sense line pair. A second reference cell is precharged for the selected bit line pair for a reference cell precharging interval, the reference cell precharging interval being concurrent with at least a portion of the voltage development interval. A sense amplifier is enabled for a voltage detection interval. The bit line pair is precharged for a bit line precharging interval. The sense line pair is isolated from the bit line pair during the bit line precharging interval and the bit line precharging interval is concurrent with at least a portion of the voltage detection interval.
摘要翻译：在一个方面，读取存储器包括将存储器单元和第一参考单元导电地耦合到用于电压发展间隔的所选位线对的各个线。在间隔期间，位线对上产生电压差，并传输到相应的感测线对。对于所选择的位线对，对于参考单元预充电间隔，第二参考单元被预充电，所述参考单元预充电间隔与所述电压显影间隔的至少一部分同时。读出放大器使能电压检测间隔。对于位线预充电间隔，位线对被预充电。在位线预充电间隔期间，感测线对与位线对隔离，并且位线预充电间隔与电压检测间隔的至少一部分同时发生。

13. 发明授权

US08229989B2 Method for controlling rounding modes in single instruction multiple data (SIMD) floating-point units 有权
标题翻译：用于控制单指令多数据（SIMD）浮点单元中舍入模式的方法
公开(公告)号：US08229989B2
公开(公告)日：2012-07-24
申请号：US12238500
申请日：2008-09-26
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/38
CPC分类号： G06F7/49947 , G06F7/483 , G06F7/49968 , G06F7/49973 , G06F7/49989 , G06F2207/3828
摘要： A method for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.
摘要翻译：公开了一种用于在单指令多数据（SIMD）浮点单元中控制舍入模式的方法。 SIMD浮点单元包括具有第一舍入模式位字段和第二舍入模式位字段的浮点状态和控制寄存器（FPSCR）。 SIMD浮点单元还包括用于生成第一切片和第二切片的装置。在浮点运算期间，SIMD浮点单元根据第一舍入模式位字段中的位并且在第二舍入中的位同时对第一切片进行第一舍入运算，并对第二切片进行第二舍入运算 FPSCR中的模式位字段。

14. 发明授权

US08166085B2 Reducing the latency of sum-addressed shifters 失效
标题翻译：减少和寻址移位器的延迟
公开(公告)号：US08166085B2
公开(公告)日：2012-04-24
申请号：US12105726
申请日：2008-04-18
申请人： Sang Hoo Dhong , Christian Jacobi , Silvia Melitta Mueller , Hiroo Nishikawa , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Christian Jacobi , Silvia Melitta Mueller , Hiroo Nishikawa , Hwa-Joon Oh
IPC分类号： G06F15/00 , G06F7/38
CPC分类号： G06F5/012
摘要： The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a bit group of the shift amount is employable to affect at least one of the plurality of shift stages, thereby decreasing processing time.
摘要翻译：本发明提供了作为多个数字的函数的移位量的计算。至少一个解码器和至少一个加法器并联耦合。移位器被配置为计算多个移位级中的值，并且其中移位量的位组可用于影响多个移位级中的至少一个，从而减少处理时间。

15. 发明授权

US07490119B2 High speed adder design for a multiply-add based floating point unit 失效
标题翻译：用于基于加法的浮点单元的高速加法器设计
公开(公告)号：US07490119B2
公开(公告)日：2009-02-10
申请号：US10733839
申请日：2003-12-11
申请人： Sang Hoo Dhong , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/42 , G06F7/38
CPC分类号： G06F7/483 , G06F7/5443
摘要： An apparatus and computer program product are provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays.
摘要翻译：提供了一种用于在给定计算机系统中改进浮点单元（FPU）的高速加法器的装置和计算机程序产品。改进的加法器利用复合增量器，复合加法器，进位网络，加法器控制/选择器和多路复用器（多路复用器）系列。进位网络同时执行结束进位功能并且独立于优化加法器功能的其他所需功能。此外，还使用最小数量的多路复用器来减少多路复用器延迟。

16. 发明申请

US20080263336A1 Processor Having Efficient Function Estimate Instructions 审中-公开
标题翻译：具有高效功能估计指令的处理器
公开(公告)号：US20080263336A1
公开(公告)日：2008-10-23
申请号：US12145482
申请日：2008-06-24
申请人： Sang Hoo Dhong , Gordon Clyde Fossum , Harm Peter Hofstee , Brad William Michael , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Gordon Clyde Fossum , Harm Peter Hofstee , Brad William Michael , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F9/302
CPC分类号： G06F7/483 , G06F7/535 , G06F7/5443 , G06F7/5525 , G06F9/30014 , G06F2207/5356
摘要： High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.
摘要翻译：高精度浮点函数估计分为两个指令：低精度表查找指令和线性插值指令。可以使用该方案来实现不同功能的估计：为每个不同的功能提供单独的表查找指令，而仅需要单个插补指令，因为单个内插指令可以执行任何功能的内插步骤估计。因此，与专用硬件相比，产生的开销大大降低，同时仍保持统一的FPU延迟，这允许更简单的控制逻辑。

17. 发明授权

US07392270B2 Apparatus and method for reducing the latency of sum-addressed shifters 有权
标题翻译：用于减少和寻址移位器的延迟的装置和方法
公开(公告)号：US07392270B2
公开(公告)日：2008-06-24
申请号：US10902475
申请日：2004-07-29
申请人： Sang Hoo Dhong , Christian Jacobi , Silvia Melitta Mueller , Hiroo Nishikawa , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Christian Jacobi , Silvia Melitta Mueller , Hiroo Nishikawa , Hwa-Joon Oh
IPC分类号： G06F7/00 , G06F7/38
CPC分类号： G06F5/012
摘要： The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a bit group of the shift amount is employable to affect at least one of the plurality of shift stages, thereby decreasing processing time.
摘要翻译：本发明提供了作为多个数字的函数的移位量的计算。至少一个解码器和至少一个加法器并联耦合。移位器被配置为计算多个移位级中的值，并且其中移位量的位组可用于影响多个移位级中的至少一个，从而减少处理时间。

18. 发明申请

US20090024684A1 Method for Controlling Rounding Modes in Single Instruction Multiple Data (SIMD) Floating-Point Units 有权
标题翻译：用于控制单指令多数据（SIMD）浮点单元中舍入模式的方法
公开(公告)号：US20090024684A1
公开(公告)日：2009-01-22
申请号：US12238500
申请日：2008-09-26
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/483
CPC分类号： G06F7/49947 , G06F7/483 , G06F7/49968 , G06F7/49973 , G06F7/49989 , G06F2207/3828
摘要： A method for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.
摘要翻译：公开了一种用于在单指令多数据（SIMD）浮点单元中控制舍入模式的方法。 SIMD浮点单元包括具有第一舍入模式位字段和第二舍入模式位字段的浮点状态和控制寄存器（FPSCR）。 SIMD浮点单元还包括用于生成第一切片和第二切片的装置。在浮点运算期间，SIMD浮点单元根据第一舍入模式位字段中的位并且在第二舍入中的位同时对第一切片进行第一舍入运算，并对第二切片进行第二舍入运算 FPSCR中的模式位字段。

19. 发明授权

US07469265B2 Methods and apparatus for performing multi-value range checks 失效
标题翻译：执行多值范围检查的方法和装置
公开(公告)号：US07469265B2
公开(公告)日：2008-12-23
申请号：US10687437
申请日：2003-10-16
申请人： Sang Hoo Dhong , Silvia Melitta Mueller , Hiroo Nishikawa , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Silvia Melitta Mueller , Hiroo Nishikawa , Hwa-Joon Oh
IPC分类号： G06F7/42 , G06F15/00
CPC分类号： G06F7/026 , G06F5/012 , G06F7/485
摘要： In a first aspect, a method is provided for determining in which of n intervals a sum of two or more numbers resides. The method includes determining the two or more numbers, and providing fewer than n compress circuits each adapted to (1) input the two or more numbers; (2) input range information regarding ranges used to define the n intervals; and (3) compress the two or more numbers and the range information into two or more outputs. The method further includes employing the fewer than n compress circuits to determine in which of the n intervals the sum of the two or more numbers resides. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种用于确定n个间隔中的哪一个是两个或多个数字的和的位置的方法。该方法包括确定两个或多个数字，并且提供少于n个压缩电路，每个压缩电路适于（1）输入两个或多个数字; （2）关于用于定义n个间隔的范围的输入范围信息; 和（3）将两个以上的数字和范围信息压缩成两个以上的输出。该方法还包括采用少于n个压缩电路来确定n个间隔中的哪一个是两个或多个数字的和。提供了许多其他方面。

20. 发明授权

US07137021B2 Power saving in FPU with gated power based on opcodes and data 失效
标题翻译：基于操作码和数据，通过门控电源对FPU进行省电
公开(公告)号：US07137021B2
公开(公告)日：2006-11-14
申请号：US10439037
申请日：2003-05-15
申请人： Sang Hoo Dhong , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F1/26
CPC分类号： G06F9/30014 , G06F1/3203 , G06F1/3243 , G06F1/3287 , G06F9/3836 , G06F9/3885 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： A method and an apparatus are provided for saving power in a microprocessor. The microprocessor has at least one functional unit, which has a plurality of blocks. The blocks each include a plurality of sub-blocks. It is determined whether there is any instruction for the functional unit. Upon a determination that there is no instruction for the functional unit, the functional unit is shut down. Upon a determination that there is at least one instruction for the functional unit, at least one inactive block of the functional unit is shut down based on the instruction.
摘要翻译：提供了一种用于节省微处理器功率的方法和装置。微处理器具有至少一个功能单元，其具有多个块。各块包括多个子块。确定是否存在功能单元的任何指令。在确定没有对功能单元的指令的情况下，功能单元被关闭。在确定对功能单元至少有一条指令的情况下，功能单元的至少一个非活动块基于该指令被关闭。

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