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11. 发明授权

US06972465B2 CMOS process compatible, tunable negative differential resistance (NDR) device and method of operating same 有权
标题翻译： CMOS工艺兼容，可调负差分电阻（NDR）器件及其操作方法
公开(公告)号：US06972465B2
公开(公告)日：2005-12-06
申请号：US10760090
申请日：2004-01-15
申请人： Tsu-Jae King , David K. Y. Liu
发明人： Tsu-Jae King , David K. Y. Liu
IPC分类号： H01L29/78 , G11C5/14 , G11C11/39 , G11C16/04 , H01L21/28 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/66 , H01L29/788 , H01L29/792 , H01L29/72
CPC分类号： B82Y10/00 , G11C5/142 , G11C11/39 , G11C16/04 , H01L21/28273 , H01L21/28282 , H01L27/088 , H01L29/78 , H01L29/788 , H01L29/7881 , H01L29/792
摘要： A CMOS based n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that exhibits a useful negative differential resistance effect is disclosed. The resulting device can be incorporated into a number of useful applications, including as part of a memory device, a logic device, etc.
摘要翻译：公开了一种具有有用的负差分电阻效应的基于CMOS的n沟道金属 - 绝缘体 - 半导体场效应晶体管（MISFET）。所得到的设备可以并入多个有用的应用中，包括作为存储设备的一部分，逻辑设备等。

12. 发明授权

US06512274B1 CMOS-process compatible, tunable NDR (negative differential resistance) device and method of operating same 有权
标题翻译： CMOS工艺兼容，可调NDR（负差分电阻）器件及其操作方法
公开(公告)号：US06512274B1
公开(公告)日：2003-01-28
申请号：US09603101
申请日：2000-06-22
申请人： Tsu-Jae King , David K. Y. Liu
发明人： Tsu-Jae King , David K. Y. Liu
IPC分类号： H01L2902
CPC分类号： B82Y10/00 , G11C5/142 , G11C11/39 , G11C16/04 , H01L21/28273 , H01L21/28282 , H01L27/088 , H01L29/78 , H01L29/788 , H01L29/7881 , H01L29/792
摘要： An n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that exhibits negative differential resistance in its output characteristic (drain current as a function of drain voltage) is disclosed. For a fixed gate voltage, the MISFET channel current, which flows between the drain and source terminals of the transistor, firstly increases as the drain-to-source voltage increases above zero Volts. Once the drain-to-source voltage reaches a pre-determined level, the current subsequently decreases with increasing drain-to-source voltage. In this region of operation, the device exhibits negative differential resistance, as the drain current decreases with increasing drain voltage. The drain-to-source voltage corresponding to the onset of negative differential resistance is also tunable. In addition, the drain current and negative differential resistance can be electronically tailored by adjusting the gate voltage. The resulting device can be incorporated into a number of useful applications, including as part of a memory device, a logic device, etc.
摘要翻译：公开了在其输出特性（作为漏极电压的函数的漏极电流）中呈现负的差分电阻的n沟道金属 - 绝缘体 - 半导体场效应晶体管（MISFET）。对于固定栅极电压，在晶体管的漏极和源极端子之间流动的MISFET沟道电流首先随着漏极 - 源极电压增加到零伏特而增加。一旦漏极到源极电压达到预定电平，电流随着漏极 - 源极电压的增加而减小。在该操作区域中，随着漏极电压的增加，漏极电流降低，器件呈现负的差分电阻。对应于负差分电阻开始的漏极 - 源极电压也是可调谐的。此外，漏电流和负差分电阻可以通过调整栅极电压进行电子定制。所得到的设备可以并入多个有用的应用中，包括作为存储设备的一部分，逻辑设备等。

13. 发明授权

US06417550B1 High voltage MOS devices with high gated-diode breakdown voltage and punch-through voltage 失效
标题翻译：高栅极二极管击穿电压和穿通电压的高压MOS器件
公开(公告)号：US06417550B1
公开(公告)日：2002-07-09
申请号：US08920377
申请日：1997-08-29
申请人： Raminda U. Madurawe , David K. Y. Liu
发明人： Raminda U. Madurawe , David K. Y. Liu
IPC分类号： H01L2976
CPC分类号： H01L21/823807 , H01L27/105 , H01L29/1083
摘要： A transistor device suitable for high voltage and low voltage applications, while maintaining minimum channel lengths. In one embodiment, pocket implants (310) are formed in a minimum channel device causing a reverse channel effect. The reverse channel effect is optimized for the minimum channel length of the device. Field implants (120), enhancement implants (130), and wells (140) are all formed using a single mask.
摘要翻译：适用于高电压和低电压应用的晶体管器件，同时保持最小的通道长度。在一个实施例中，口袋植入物（310）形成在引起反向通道效应的最小通道装置中。针对设备的最小通道长度优化了反向通道效应。现场植入物（120），增强植入物（130）和孔（140）均使用单一掩模形成。

14. 发明授权

US5930174A Circuit and method for erasing flash memory array 失效
标题翻译：擦除闪存阵列的电路和方法
公开(公告)号：US5930174A
公开(公告)日：1999-07-27
申请号：US988872
申请日：1997-12-11
申请人： Kou-Su Chen , David K. Y. Liu
发明人： Kou-Su Chen , David K. Y. Liu
IPC分类号： G11C16/02 , G11C16/34 , G11C16/04 , G11C7/00
CPC分类号： G11C16/345 , G11C16/3404 , G11C16/3409 , G11C16/3445 , G11C2216/18
摘要： A circuit and method for achieving compressed distributions of erased cell threshold voltages in an EEPROM array is disclosed. The invention, when used to condition flash memory cell arrays, results in increased endurance of such arrays, and eliminates the need for pre-programming operations before a bulk erase can take place. By eliminating the need to pre-program the memory array before each erasure, the process provides a signicant improvement for low power applications, because battery life is extended and write cycle time is enhanced.
摘要翻译：公开了一种用于实现EEPROM阵列中擦除的单元阈值电压的压缩分布的电路和方法。本发明在用于调节闪存单元阵列时，导致这种阵列的耐久性增加，并且在大量擦除可能发生之前消除了对预编程操作的需要。通过消除在每次擦除之前对存储器阵列进行预编程的需要，该过程对于低功率应用提供了显着的改进，因为电池寿命延长并且写周期时间增加。

15. 发明授权

US5656509A Method and test structure for determining gouging in a flash EPROM cell during SAS etch 失效
标题翻译：在SAS蚀刻期间确定闪存EPROM单元中的气刨的方法和测试结构
公开(公告)号：US5656509A
公开(公告)日：1997-08-12
申请号：US438434
申请日：1995-05-10
申请人： David K. Y. Liu
发明人： David K. Y. Liu
IPC分类号： H01L23/544 , H01L21/66
CPC分类号： H01L22/34
摘要： In one aspect of the present invention, a method includes the steps of providing a first test cell electrically isolated from the substrate, unexposed to the SAS etch and having a first core profile. The method further includes providing a second test cell electrically isolated from the substrate, exposed to the SAS etch, and having a second core profile. Additionally, the method includes performing the SAS etch, measuring electrical characteristics of the first and second cells, and comparing the measured electrical characteristics to determine an amount of gouging. In a further aspect of the present invention, a method includes the steps of forming a pair of test structures in electrical isolation of a substrate of the cell, and measuring resistance values for each of the pair of test structures to determine the amount of gouging. In addition, the method includes protecting one of the pair of test structures from the SAS etch.
摘要翻译：在本发明的一个方面，一种方法包括以下步骤：提供与基板电隔离的第一测试单元，未暴露于SAS蚀刻并具有第一芯轮廓。该方法还包括提供暴露于SAS蚀刻并具有第二芯轮廓的与衬底电隔离的第二测试单元。此外，该方法包括执行SAS蚀刻，测量第一和第二单元的电特性，以及比较测量的电特性以确定气刨的量。在本发明的另一方面，一种方法包括以下步骤：在电隔离电池单元的电气隔离中形成一对测试结构，以及测量每对测试结构中的每一个的电阻值，以确定气刨的量。此外，该方法包括保护该对测试结构中的一个与SAS蚀刻。

16. 发明授权

US08988103B2 Capacitively coupled logic gate 有权
标题翻译：电容耦合逻辑门
公开(公告)号：US08988103B2
公开(公告)日：2015-03-24
申请号：US13233767
申请日：2011-09-15
申请人： David K. Y. Liu
发明人： David K. Y. Liu
IPC分类号： H03K19/23 , H01L27/115 , H01L27/118
CPC分类号： H03K19/23 , H01L27/11517 , H01L27/11803 , H03K19/173
摘要： An electronic logic circuit uses areal capacitive coupling devices coupled together to process a set of data inputs. Each areal capacitive coupling device can be configured such that a floating gate potential of such device can be altered to at least a first state or a second state in response to receiving an input signal from the set of data inputs, which is coupled electrically to the floating gate. A majority function logic circuit (and other similar circuits) can be interconnected this way using far fewer gates than with a conventional CMOS implementation. Selective logic gates can also be enabled or disabled by configuring them effectively as memory devices.
摘要翻译：电子逻辑电路使用耦合在一起以处理一组数据输入的区域电容耦合装置。可以配置每个面对电容耦合装置，使得这样的装置的浮动栅极电位可以被改变为至少第一状态或第二状态，以响应于接收来自该组数据输入的输入信号，该输入信号电耦合到浮动门。大多数功能逻辑电路（和其他类似的电路）可以通过使用比常规CMOS实现更少的门来互连。还可以通过有选择地将其配置为存储器件来启用或禁用选择逻辑门。

17. 发明授权

US07067873B2 Charge trapping device 有权
标题翻译：电荷捕集装置
公开(公告)号：US07067873B2
公开(公告)日：2006-06-27
申请号：US10753948
申请日：2004-01-07
申请人： Tsu-Jae King , David K. Y. Liu
发明人： Tsu-Jae King , David K. Y. Liu
IPC分类号： H01L29/76 , H01L29/788
CPC分类号： H01L29/42332 , H01L29/51 , H01L29/513 , H01L29/78 , H01L29/788 , H01L29/7881 , H01L29/792
摘要： A silicon based semiconductor device and method uses charge trapping to alter a density of carriers available in a channel of a field effect transistor (FET) for conduction. The charge trapping mechanism can be controlled by a source-drain bias voltages applied to the FET, so that the device can be turned off through a control mechanism separate from a gate voltage.
摘要翻译：硅基半导体器件和方法使用电荷俘获来改变用于导电的场效应晶体管（FET）的通道中可用的载流子的密度。可以通过施加到FET的源极 - 漏极偏置电压来控制电荷捕获机制，使得可以通过与栅极电压分离的控制机制来关闭器件。

18. 发明授权

US06969894B2 Variable threshold semiconductor device and method of operating same 有权
标题翻译：可变阈值半导体器件及其操作方法
公开(公告)号：US06969894B2
公开(公告)日：2005-11-29
申请号：US10757245
申请日：2004-01-14
申请人： Tsu-Jae King , David K. Y. Liu
发明人： Tsu-Jae King , David K. Y. Liu
IPC分类号： H01L29/78 , G11C5/14 , G11C11/39 , G11C16/04 , H01L21/28 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/66 , H01L29/788 , H01L29/792 , H01L29/72
CPC分类号： B82Y10/00 , G11C5/142 , G11C11/39 , G11C16/04 , H01L21/28273 , H01L21/28282 , H01L27/088 , H01L29/78 , H01L29/788 , H01L29/7881 , H01L29/792
摘要： An n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that exhibits a variable threshold voltage is disclosed. The resulting device can be incorporated into a number of useful applications, including as part of a memory device, a logic device, etc.
摘要翻译：公开了具有可变阈值电压的n沟道金属 - 绝缘体 - 半导体场效应晶体管（MISFET）。所得到的设备可以并入多个有用的应用中，包括作为存储设备的一部分，逻辑设备等。

19. 发明授权

US06479862B1 Charge trapping device and method for implementing a transistor having a negative differential resistance mode 有权
标题翻译：用于实现具有负差分电阻模式的晶体管的电荷俘获装置和方法
公开(公告)号：US06479862B1
公开(公告)日：2002-11-12
申请号：US09603102
申请日：2000-06-22
申请人： Tsu-Jae King , David K. Y. Liu
发明人： Tsu-Jae King , David K. Y. Liu
IPC分类号： H01L2972
CPC分类号： H01L29/42332 , H01L29/51 , H01L29/513 , H01L29/78 , H01L29/788 , H01L29/7881 , H01L29/792
摘要： A charge trapping structure for use with an n-channel metal-insulator-semiconductor field-effect transistor (MISFET) is disclosed. A dielectric layer is formed close to a channel region of the MISFET, and includes a number of trapping sites which are arranged and have a concentration sufficient to temporarily store energetic electrons induced by an electric field to move from the channel into the trapping sites. The trapped electrons set up a counter field that depletes the channel of carriers, and as a bias voltage across the channel increases, the device exhibits negative differential resistance (NDR). The charge trapping structure, as well as the rest of the device, are formed using conventional CMOS processing techniques.
摘要翻译：公开了一种与n沟道金属 - 绝缘体 - 半导体场效应晶体管（MISFET）一起使用的电荷俘获结构。电介质层形成在MISFET的沟道区附近，并且包括多个俘获位点，其布置并具有足以临时存储由电场引起的能量电子从该通道移动到捕获位点的浓度。捕获的电子建立了一个消耗载流子通道的反向场，并且随着通道上的偏置电压的增加，器件呈现负的差分电阻（NDR）。电荷捕获结构以及器件的其余部分使用常规CMOS处理技术形成。

20. 发明授权

US6091636A Flash memory cell and a new method for sensing the content of the new memory cell 失效
标题翻译：闪存单元和用于感测新存储单元的内容的新方法
公开(公告)号：US6091636A
公开(公告)日：2000-07-18
申请号：US417234
申请日：1998-03-26
申请人： David K. Y. Liu , Wenchi Ting
发明人： David K. Y. Liu , Wenchi Ting
IPC分类号： G11C16/04 , G11C16/26 , H01L27/115 , H01L27/12 , G11C16/06
CPC分类号： H01L27/1203 , G11C16/0483 , G11C16/26 , H01L27/115
摘要： A method for sensing the content of a FLASH memory cell, and a new FLASH memory cell structure that is suitable for use with this new sensing scheme. In a first aspect, a semiconductor memory cell comprises a lightly doped n-region including a channel region; a first insulating layer overlying portions of said n-region; a floating gate overlying said first insulating layer; a second insulating layer overlying said floating gate; and a control gate overlying second insulating layer.
摘要翻译：一种用于感测闪速存储器单元的内容的方法，以及适用于该新感测方案的新型闪存单元结构。在第一方面，半导体存储单元包括包含沟道区的轻掺杂n区; 覆盖所述n区的部分的第一绝缘层; 覆盖所述第一绝缘层的浮动栅极; 覆盖所述浮动栅极的第二绝缘层; 以及覆盖第二绝缘层的控制栅极。

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