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11. 发明专利

CA2396948A1 A SYSTEM AND METHOD FOR SENDING AND RECEIVING DATA SIGNALS OVER A CLOCK SIGNAL LINE 未知
公开(公告)号：CA2396948A1
公开(公告)日：2002-05-16
申请号：CA2396948
申请日：2001-10-30
申请人： SILICON IMAGE INC
发明人： KIM MIN-KYU , KIM GYUDONG , HWANG SEUNG HO
IPC分类号： G06F13/38 , G06F1/12 , H04L1/12 , H04L7/00 , H04L7/04 , H04L25/02 , H04L25/38 , H04L25/00
摘要： The system preferably includes a unique transmitter that sends both clock an d data signals over the same transmission line. The receiver uses the same transmission line to send data signals back to the transmitter. The transmitter comprises a clock generator, a decoder and a line interface. The clock generator produces a clock signal that includes a variable position falling edge. The falling edge position is decoded by the receiver to extrac t data from the clock signal. The receiver comprises a clock re-generator, a data decoder and a returm channel encoder. The clock re-generator monitors t he transmission line, receives signals, filters them and generates a clock sign al at the receiver from the signal on the transmission line. The return channel encoder generates signals and asserts them on the transmission line. The signal is asserted or superimposed over the clock & data signal provided by the transmitter.

12. 发明申请

WO2010051281A3 TRANSMISSION OF ALTERNATIVE CONTENT OVER STANDARD DEVICE CONNECTORS 审中-公开
标题翻译：通过标准设备连接器传输替代内容
公开(公告)号：WO2010051281A3
公开(公告)日：2010-06-24
申请号：PCT/US2009062232
申请日：2009-10-27
申请人： SILICON IMAGE INC , JONES GRAEME PETER , SHIM DAEYUN , RANADE SHRIKANT , KIM GYUDONG , KIM OOK
发明人： JONES GRAEME PETER , SHIM DAEYUN , RANADE SHRIKANT , KIM GYUDONG , KIM OOK
IPC分类号： G09G5/00 , G06F13/40 , H04L12/40 , H04M11/06
CPC分类号： G09G5/006 , G06F13/409 , G09G2370/10 , G09G2370/12 , H04L12/40006
摘要： Transmission of alternative content over standard device connectors. An embodiment of a method includes connecting a first device to a second device utilizing a standard connector, the connector including multiple pins, and detecting whether the second device is operating in a standard mode or an alternative mode. If the second device is operating in the alternative mode, then switching one or more pins of the standard connector for the alternative mode and transmitting or receiving signals for the alternative mode via the plurality of pins of the standard connector.
摘要翻译：通过标准设备连接器传输替代内容。方法的实施例包括利用标准连接器将第一设备连接到第二设备，该连接器包括多个引脚，并且检测第二设备是以标准模式还是替代模式操作。如果第二设备以替代模式操作，则切换用于备选模式的标准连接器的一个或多个引脚，并且经由标准连接器的多个引脚来发送或接收用于替代模式的信号。

13. 发明申请

WO9912072A3 POWER SAVING CIRCUIT AND METHOD FOR DRIVING AN ACTIVE MATRIX DISPLAY 审中-公开
标题翻译：节电电路和驱动有源矩阵显示的方法
公开(公告)号：WO9912072A3
公开(公告)日：1999-07-08
申请号：PCT/US9818525
申请日：1998-09-04
申请人： SILICON IMAGE INC
发明人： KIM DEOG-KYOON , KIM GYUDONG
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36
CPC分类号： G09G3/3655 , G09G3/3614 , G09G3/3648 , G09G3/3688 , G09G2310/0248 , G09G2330/021 , G09G2330/023
摘要： Switches and capacitors are efficiently used to passively change the voltate level on column electrodes without active driving by the column driver circuit. This significantly reduces the power needed by the column driver circuit to drive voltages of alternating polarity onto the column electrodes. In this way, significant power is saved in both the pixel inversion and the row inversion schemes. The average power savings of various of the embodiments exceeds 50 % compared with a simple conventional implementation of a column driver circuit. Another aspect similarly reduces the power used by the column driver circuit in the back plane switching scheme.
摘要翻译：开关和电容器被有效地用于被动地改变列电极上的电压电平，而无需由列驱动电路进行有源驱动。这显着地降低了列驱动电路所需的功率，以驱动交替极性的电压到列电极上。以这种方式，在像素反转和行反转方案中节省了显着的功率。与列驱动电路的简单常规实施方式相比，各种实施例的平均功率节省超过了50％。另一方面类似地减少了在背面切换方案中列驱动电路所使用的功率。

14. 发明专利

DE69932004T2 未知
公开(公告)号：DE69932004T2
公开(公告)日：2007-06-28
申请号：DE69932004
申请日：1999-01-20
申请人： SILICON IMAGE INC
发明人： MOON YONGSAM , JEONG DEOG-KYOON , KIM GYUDONG
IPC分类号： H04B15/04 , G06F1/04 , H04B1/707 , H04B15/00
摘要： A new spread spectrum phase modulation (SSPM) technique is applicable to both data and clock signals. The SSPM technique is more suitable to board level designs than the direct-sequence spread spectrum (DSSS) technique. In addition, SSPM may be combined with controlled edge rate signaling to outperform DSSS.

15. 发明专利

CA2376971A1 COMBINING A CLOCK SIGNAL AND A DATA SIGNAL 未知
公开(公告)号：CA2376971A1
公开(公告)日：2002-09-16
申请号：CA2376971
申请日：2002-03-15
申请人： SILICON IMAGE INC
发明人： HWANG SEUNG HO , KIM MIN-KYU , KIM BRUCE , KIM OOK , KIM GYUDONG
IPC分类号： H03L7/099 , G09G5/00 , H04L5/06 , H04L7/00 , H04L7/02 , H04L7/027 , H04L7/04 , H04L25/49
摘要： A method of transmitting data is a system including at least one data channe l and a separate clock channel is disclosed. The method involves combining a clock signal to be transmitted on the clock channel with a data signal to generate a combine d clock and data signal. In one embodiment, the data signal has been generated from data words using an encoding scheme that shifts an energy spectrum of the data signal away from an energy spectrum of the clock signal. In another embodiment, the clock signal has a plurality of pulses each having a front edge and a back edge, and the data signal is modulated onto the clock signal by moving at least ones edge (i.e. front or back or both) of the plurality of pulses, thereby to create a combined clock and data signal.

16. 发明专利

CA2343040A1 A SYSTEM AND METHOD FOR SENDING AND RECEIVING DATA SIGNALS OVER A CLOCK SIGNAL LINE 未知
公开(公告)号：CA2343040A1
公开(公告)日：2000-03-23
申请号：CA2343040
申请日：1999-09-10
申请人： SILICON IMAGE INC
发明人： HWANG SEUNG HO , KIM GYUDONG , KIM MIN-KYU
IPC分类号： H04J3/06 , H04L7/00 , H04L25/49 , H04L69/14 , H04L25/02
摘要： The system preferably includes a unique transmitter that sends both clock an d data signals over the same transmission line. The receiver uses the same transmission line to send data signals back to the transmitter. The transmitter comprises a clock generator, a decoder and a line interface. The clock generator produces a clock signal that includes a variable position falling edge. The falling edge position is decoded by the receiver to extrac t data from the clock signal. The receiver comprises a clock re-generator, a data decoder and a return channel encoder. The clock re-generator monitors t he transmission line, receives signals, filters them and generates a clock sign al at the receiver from the signal on the transmission line. The return channel encoder generates signals and asserts them on the transmission line. The signal is asserted or superimposed over the clock and data signal provided b y the transmitter.

17. 发明专利

CA2302367A1 CONTROLLABLE DELAYS IN MULTIPLE SYNCHRONIZED SIGNALS FOR REDUCED ELECTROMAGNETIC INTERFERENCE AT PEAK FREQUENCIES 未知
公开(公告)号：CA2302367A1
公开(公告)日：1999-03-11
申请号：CA2302367
申请日：1998-09-04
申请人： SILICON IMAGE INC
发明人： KIM GYUDONG , JEONG DEOG-KYOON , LEE DAVID D
IPC分类号： H04B3/04 , H04L25/08
摘要： Multiple controllable delays reduce EMI radiated during the transmission of multiple synchronized signals. Each controllable delay introduces a controlled delay into a corresponding signal being transmitted. The controlled delay is such that the combined strength of the multiple signals at peak frequencies is substantially reduced. This results in reduced EMI radiation at those peak frequencies.

18. 发明专利

AU6550398A System and method for driving columns of an active matrix display 未知
公开(公告)号：AU6550398A
公开(公告)日：1998-09-29
申请号：AU6550398
申请日：1998-03-10
申请人： SILICON IMAGE INC
发明人： JEONG DEOG-KYOON , KIM GYUDONG , SONG HO YOUNG , LEE DAVID D
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36
摘要： Described is a system and method for driving columns of an active matrix display using a resistor-string digital-to-analog converter (DAC). The description includes an auto-stop buffer circuit that drives an analog data voltage in two steps-the first step being active buffering by a "dead-zone amplifier" before the output reaches a certain level and the second step being acting as a passive conduit after the output reaches the certain level. The dead-zone amplifier inherently turns itself off when the analog voltage reaches the certain level. Also described are various column driver architectures in which buffers are placed in various ways in a column driver in between the resistor-string DAC and the column decoders in order to minimize the number of required buffers.

19. 发明申请

WO2012109128A3 MECHANISM FOR LOW POWER STANDBY MODE CONTROL CIRCUIT 审中-公开
标题翻译：低功耗待机模式控制电路的机理
公开(公告)号：WO2012109128A3
公开(公告)日：2013-01-10
申请号：PCT/US2012023940
申请日：2012-02-06
申请人： SILICON IMAGE INC , KIM GYUDONG , KIM EUNGU , KIM MIN-KYU , SHIM DAEYUN , SHARMA RAVI , KIM MYOUNGHWAN , LEE JAERYON
发明人： KIM GYUDONG , KIM EUNGU , KIM MIN-KYU , SHIM DAEYUN , SHARMA RAVI , KIM MYOUNGHWAN , LEE JAERYON
IPC分类号： G06F1/32 , G06F13/14
CPC分类号： G06F1/3287 , G06F1/3246 , G06F1/3293 , Y02D10/122 , Y02D10/171 , Y02D50/20
摘要： Embodiments of the invention are generally directed to a low power standby mode control circuit. An embodiment of an apparatus includes a processor, an interface for a connection with a second apparatus, and an operational circuit, wherein the processor is to disable one or more power connections to the operational circuit in a standby mode. The apparatus further includes a standby mode control circuit, the standby control circuit to operate using a standby power source, wherein the standby mode control circuit is to detect a stimulus signal from the second apparatus and in response to the stimulus signal the standby control circuit is to signal the processor, the processor to enable the one or more power connections of the operational circuit.
摘要翻译：本发明的实施例通常涉及低功率待机模式控制电路。装置的实施例包括处理器，用于与第二装置的连接的接口和操作电路，其中处理器在待机模式下禁用与操作电路的一个或多个电源连接。该设备还包括备用模式控制电路，待机控制电路使用待机电源进行操作，其中待机模式控制电路将检测来自第二设备的激励信号，并且响应于激励信号，备用控制电路为为了向处理器发信号，处理器启用操作电路的一个或多个电源连接。

20. 发明申请

WO2012003328A3 DETECTION OF CABLE CONNECTIONS FOR ELECTRONIC DEVICES 审中-公开
标题翻译：检测电子设备的电缆连接
公开(公告)号：WO2012003328A3
公开(公告)日：2012-04-05
申请号：PCT/US2011042611
申请日：2011-06-30
申请人： SILICON IMAGE INC , KIM GYUDONG , HARREL CHANDLEE , RANADE SHRIKANT , PEYSAKHOVICH ALEXANDER
发明人： KIM GYUDONG , HARREL CHANDLEE , RANADE SHRIKANT , PEYSAKHOVICH ALEXANDER
IPC分类号： H04L29/10 , H04L29/06
CPC分类号： G06F13/4072
摘要： Embodiments of the invention are generally directed to detection of cable connections for electronic devices. An embodiment of an apparatus includes a port for the connection of a cable, the port being compatible with a first protocol and a second protocol, the port including multiple pins including a first pin for a first line and a second pin for a second line. The apparatus further includes a processor to determine a type of source device connected to the cable, where determination of the type of source device includes the apparatus detecting a low signal on the first line and a high signal on the second line, and, upon detecting the low signal on first line and the high signal on the second line, the apparatus initiates a discovery sequence, the discovery sequence including transmitting a signal sequence on the second line and attempting to receive the signal sequence on the second line. If the signal sequence is successfully received on the second line, the apparatus determines that a source device compatible with the first protocol is connected to the cable.
摘要翻译：本发明的实施例一般涉及电子设备的电缆连接的检测。装置的实施例包括用于连接电缆的端口，该端口与第一协议和第二协议兼容，该端口包括多个引脚，包括用于第一线路的第一引脚和用于第二线路的第二引脚。该装置还包括处理器，用于确定连接到电缆的源设备的类型，其中源设备的类型的确定包括检测第一线路上的低信号的设备和在第二线路上的高信号，并且在检测到第一行上的低信号和第二行上的高信号，装置启动发现序列，发现序列包括在第二行上发送信号序列并尝试在第二行上接收信号序列。如果在第二行上成功接收到信号序列，则装置确定与第一协议兼容的源设备连接到电缆。

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