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11. 发明专利

JPH0586573B2 失效
公开(公告)号：JPH0586573B2
公开(公告)日：1993-12-13
申请号：JP26573787
申请日：1987-10-20
申请人： SHARP KK
发明人： KOMATSU KOJI
IPC分类号： G06F13/00 , G06F12/00 , G06F13/16 , G06F13/18 , G06F15/82

12. 发明专利

JPH01108647A TEMPLATE MATCHING CIRCUIT 失效
公开(公告)号：JPH01108647A
公开(公告)日：1989-04-25
申请号：JP26573787
申请日：1987-10-20
申请人： SHARP KK
发明人： KOMATSU KOJI
IPC分类号： G06F13/00 , G06F12/00 , G06F13/16 , G06F13/18 , G06F15/82
摘要： PURPOSE:To perform template matching at high speed by executing the pipeline processing of respective datum in parallel for at least one set of parallel input out of packet data consisting of word data of one or more words. CONSTITUTION:In a memory access control circuit 7, only one of memory access parts in memory readout parts 2A and 2B and memory write parts 5A and 5B is permitted to make access to a memory by a memory access permission signal. When contention is generated in plural number of memory access, the memory access is performed preferentially from the memory access part from which a request of memory access is issued earlier in the parts 2A, 2B, 5A, or 5B. The memory access part where the memory access is permitted generates a memory access execution signal representing a period to make access to the memory, and no permission of the memory access by other memory access parts is issued in the period of memory access. In such a way, the memory access of the memory access part from which another request of memory access is issued is permitted after completing the memory access under execution.

13. 发明专利

JPH01108642A DATA PROCESSOR 失效
公开(公告)号：JPH01108642A
公开(公告)日：1989-04-25
申请号：JP26573487
申请日：1987-10-20
申请人： SHARP KK
发明人： KOMATSU KOJI , YOSHIDA SHINICHI , MIYATA SOICHI
IPC分类号： G06F15/82 , G06F9/44
摘要： PURPOSE:To realize a fast template matching by providing a pre-detecting part and a template matching part, and executing the pipeline processing of respective data for data on parallel data transmission paths in parallel. CONSTITUTION:When it is recognized that the flag of the data in the template matching part 2 shows the coincidence of identifiers by comparing the identifiers of the data between confronting data transmission paths at the pre-detecting part 1 and attaching a decision result flag, and when both data make access to the same memory address and a low priority is attached, no access to a matching memory is performed, and frequency to make access to the memory is decreased. In case of generating contention in the access to the data when second readout by the data on the other side is performed by the time when write is performed after performing first readout by the data on one side between different data transmission paths, it is decided that second data read out later is not correct. In such a way, a decision flag makes the access to the matching memory by the data with the low priority wait.

14. 发明专利

JPH11162188A SENSE-AMPLIFIER CIRCUIT 失效
公开(公告)号：JPH11162188A
公开(公告)日：1999-06-18
申请号：JP32791897
申请日：1997-11-28
申请人： SHARP KK
发明人： KOMATSU KOJI
IPC分类号： G11C11/409 , G11C7/06 , G11C11/56 , G11C16/02 , G11C16/06 , G11C16/26
摘要： PROBLEM TO BE SOLVED: To accelerate a sense amplifier circuit in a multilevel memory. SOLUTION: In this sense amplifier circuit for a multilevel memory provided with sub-sense amplifiers of a current mirror type for reference potentials, the sub-sense amplifiers of different polarities are mixedly provided depending on the reference potentials, the sub-sense amplifier of the highest reference potential serves as the sub-sense amplifier SN3 of N type and the sub-sense amplifier of the lowest reference potential serves as the-sub sense amplifier SP1 of P type. Thus, all the sub-sense amplifiers are operated with excellent operation characteristic and the access time is accelerated.

15. 发明专利

JPH11135650A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH11135650A
公开(公告)日：1999-05-21
申请号：JP30105897
申请日：1997-10-31
申请人： SHARP KK
发明人： KOMATSU KOJI
IPC分类号： G11C7/18 , G11C8/12 , G11C16/04 , G11C17/12 , H01L21/8246 , H01L27/112 , H01L27/115
摘要： PROBLEM TO BE SOLVED: To reduce no. of main bit lines to relax wiring design rules by sharing bank select lines with bank select transistor pairs to make auxiliary conductive regions common between adjacent bank regions. SOLUTION: On a semiconductor substrate sub-bit lines SB11-SB27 are wired in the column direction, and word lines WL001-WL232 are wired in the row direction crossing the sub-bit lines SB11-SB27 with bank cells BT11-BT28 formed between the sub-bit lines SB11-SB27 and auxiliary conductive regions BB1, BB2. The bank cells BT15, BT25 use a bank select line BS13 as a common gate electrode, the bank cells BT16, BT26 use a bank select line BS 14 as a common gate electrode and the bank cells BT17, BT27 use a bank select line BS24 as a common gate electrode, and the bank cells BT18, BT28 set bank selected line BS33 as a common gate electrode respectively.

16. 发明专利

JPH052523A ACCESS CONTROL DEVICE 失效
公开(公告)号：JPH052523A
公开(公告)日：1993-01-08
申请号：JP15328891
申请日：1991-06-25
申请人： SHARP KK
发明人： KOMATSU KOJI
IPC分类号： G06F12/00 , G06F15/16 , G06F15/177 , G11C11/407 , G11C11/41
摘要： PURPOSE:To provide an access control device capable of always efficiently driving a storage device even when the access competition of the storage device between plural processors occurs in a multimemory system for sharing the single storage device by plural processors. CONSTITUTION:When addresses to be used coincide with each other at the time of generating access competition between processors A, B sharing the single storage device M, the access processing of one processor is executed by interruption to an idle time for access generated in a series of processing of the other processor. On the other hand when the addresses to be used are different from each other, the access processing of one processor is waited until the end of the final access processing of the other processor.

17. 发明专利

JPH01108632A DATA PROCESSOR 失效
公开(公告)号：JPH01108632A
公开(公告)日：1989-04-25
申请号：JP26573587
申请日：1987-10-20
申请人： SHARP KK
发明人： KOMATSU KOJI , MIYATA SOICHI
IPC分类号： G06F7/00
摘要： PURPOSE:To improve the whole processing capacity of a system by transmitting data on a data transmission path as processing by a transmission time proper to the data transmission path, and setting the applying time of the data smaller than a processing time in each means. CONSTITUTION:The number of stages of the data transmission path is fitted so that a time required for the comparison decision of the data can be set equal to the time at which the data is transmitted from a comparison section A or B. Therefore, it is possible to process transmitted data by a data processing part 4A or 4B provided between the stages of the data transmission path according to the compared result of a comparison decision part 3. When the time required for the processing of the data is larger than the transmission time proper to the data transmission path, the functional constituent of the processing is divided and arranged so that the time required for the processing can be set less than the time proper to the data transmission path, then, a pipeline processing is performed. In such a way, it is possible to process the data without disturbing the transmission of the data.

18. 发明专利

JPS6255730A PROGRAM EDITING AND PRODUCING DEVICE 失效
公开(公告)号：JPS6255730A
公开(公告)日：1987-03-11
申请号：JP19509485
申请日：1985-09-04
申请人： MITSUBISHI ELECTRIC CORP , SHARP KK , MATSUSHITA ELECTRIC IND CO LTD , SANYO ELECTRIC CO
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , AKECHI MITSUO , OKAMOTO TOSHIYA , KOMATSU KOJI , TOKURA TAKESHI , TAKAKURA MINORU , HARA HIDEJI , NISHIKAWA YOICHIRO
IPC分类号： G06F9/06 , G06F15/82 , H03K17/725
摘要： PURPOSE:To edit and produce a program covering plural hierarchies with high efficiency by providing a hierarchical window to display a tree structure of said program on a display part according to an instruction given from an input part and editing the program for each function and over the functions of plural hierarchies. CONSTITUTION:An instruction is given to switch the screens of a main program FO with an instruction given from an input part 2 after programs FO-F2 are produced. Then a processor 4 reads the programs FO out of a main storage 3 and displays it on a display device 1. At the same time, the subprograms F1 and F2 contained in the program FO are also read out of the storage 3 and put into the prescribed positions of the program FO for display. If the program F1 or F2 is corrected under such conditions, the processor 4 receives the editing operation input and edits the subprograms. Thus the contents of programs F1 and F2 are changed. In such a way, the programs are edited by a hierarchical window (a) for each function or over functions of plural hierarchies.

19. 发明专利

JPH1139866A CLOCK SYNCHRONIZING MEMORY 失效
公开(公告)号：JPH1139866A
公开(公告)日：1999-02-12
申请号：JP19679197
申请日：1997-07-23
申请人： SHARP KK
发明人： KOMATSU KOJI
IPC分类号： G11C11/407
摘要： PROBLEM TO BE SOLVED: To set the optimum latency for the power supply potential by selecting a predetermined mode register within a plurality of mode registers to which different operation modes are set depending on a power supply potential detecting signal from a power supply potential detecting circuit. SOLUTION: Different operation modes are set to mode registers 411 to 41n of a mode setting means 19. A mode register selecting circuit 42 detects a power supply potential of a memory and controls a selector 43 with a selection signal Sn depending on the level of the power supply potential, causing it to output any one of the output signals (operation mode signals) MD1 to MDn from the mode registers 411 to 41n to a control logic 18 as a selected output signal SS. Thereby, the optimum latency, etc., can be set depending on the power supply potential and complication of manufacture and product control can be eliminated without requiring preparation of devices in different operation modes for each specification of the devices.

20. 发明专利

JPH10321742A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH10321742A
公开(公告)日：1998-12-04
申请号：JP13223797
申请日：1997-05-22
申请人： SHARP KK
发明人： IMURA KOJI , TACHIKAWA MASAAKI , KOMATSU KOJI
IPC分类号： H01L25/18 , H01L23/00 , H01L23/50 , H01L23/60 , H01L25/065 , H01L25/07
摘要： PROBLEM TO BE SOLVED: To provide a both-face mounting semiconductor integrated circuit device which reduces chip area and prevents increase in signal propagation delay. SOLUTION: This device is constituted so that integrated circuit chips 11, 12 are respectively mounted on both faces of a chip mount part of a lead frame and respective electrodes 15, 16 corresponding to the integrated circuit chips 11, 12 are connected to a common lead terminal 17. In this case, an electrostatic protection circuit provided for the common lead terminal 17 comprises a first portion (an electrostatic protection circuit 13) provided in the one integrated circuit chip 11 and a second portion (an electrostatic protection circuit 14) provided in the other integrated circuit chip 12, and a combined set of the both portions satisfies the necessary functions.

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