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11. 发明授权

US08134855B2 Ferroelectric memory and method for testing the same 有权
标题翻译：铁电存储器和测试方法相同
公开(公告)号：US08134855B2
公开(公告)日：2012-03-13
申请号：US12404157
申请日：2009-03-13
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G11C11/22
CPC分类号： G11C29/50 , G11C11/22 , G11C29/50016
摘要： A driver circuit and a precharge circuit apply, in a test mode, a fixed potential to a bit-line, while applying a second plate-line voltage to a plate-line. Then, the bit-line is switched from a first bit-line precharge potential to a floating state, and the plate-line voltage is raised from the second plate-line voltage to a plate-line voltage.
摘要翻译：在测试模式下，驱动电路和预充电电路将固定电位施加到位线，同时对板线施加第二板线电压。然后，将位线从第一位线预充电电位切换到浮置状态，并且将板线电压从第二板线电压升高到板线电压。

12. 发明授权

US07902913B2 Reference voltage generation circuit 有权
标题翻译：参考电压发生电路
公开(公告)号：US07902913B2
公开(公告)日：2011-03-08
申请号：US12618373
申请日：2009-11-13
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： According to an aspect of the present invention, there is provided a reference voltage generation circuit including: a first transistor having a first gate, a first source and a first drain; a second transistor having a second gate connected to the first gate, a second source connected to the first source and a second drain; a first diode connected between a ground and a V− node; a first resistor connected between the V− node and the first drain; a second diode and a second resistor connected between the ground and a V+ node; a third resistor connected between the V+ node and the first drain; an operational amplifier including input ports connected to the V+ node and the V− node and an output port connected to the first gate and the second gate; and a fourth resistor connected between the ground and the second drain.
摘要翻译：根据本发明的一个方面，提供了一种参考电压产生电路，包括：具有第一栅极，第一源极和第一漏极的第一晶体管; 第二晶体管，具有连接到第一栅极的第二栅极，连接到第一源极和第二漏极的第二源极; 连接在地和V节点之间的第一二极管; 连接在V节点和第一漏极之间的第一电阻器; 连接在地和V +节点之间的第二二极管和第二电阻器; 连接在V +节点和第一漏极之间的第三电阻器; 运算放大器，包括连接到V +节点和V节点的输入端口以及连接到第一门极和第二门极的输出端口; 以及连接在地和第二漏极之间的第四电阻器。

13. 发明授权

US07609099B2 Power-on detecting circuit 失效
标题翻译：上电检测电路
公开(公告)号：US07609099B2
公开(公告)日：2009-10-27
申请号：US11558156
申请日：2006-11-09
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： H03L7/00
CPC分类号： G01R19/16552
摘要： A circuit for detecting a power-on voltage of power supply encompasses a voltage divider connected between a first power supply and a second power supply, the potential of the second power supply is lower than the potential of the first power supply, and a detecting circuit connected between the first power supply and the second power supply. The voltage divider includes a series circuit encompassing a diode, a first dividing resistor connected to the diode and a second dividing resistor connected between the first dividing resistor and the second power supply. The detecting circuit includes a pMOS transistor whose gate electrode is connected to a connection node between the first dividing resistor and the second dividing resistor, a source resistor connected between the first power supply and the source electrode of the pMOS transistor and a drain resistor connected to the drain electrode of the pMOS transistor and the second power supply.
摘要翻译：用于检测电源的通电电压的电路包括连接在第一电源和第二电源之间的分压器，第二电源的电位低于第一电源的电位，检测电路连接在第一电源和第二电源之间。分压器包括串联电路，其包括二极管，连接到二极管的第一分压电阻器和连接在第一分压电阻器和第二电源之间的第二分压电阻器。该检测电路包括一个pMOS晶体管，其栅极连接到第一分压电阻和第二分压电阻之间的连接节点，源电阻连接在第一电源和pMOS晶体管的源电极之间，漏电阻连接到 pMOS晶体管的漏电极和第二电源。

14. 发明授权

US07426147B2 Power supply voltage control circuit 失效
标题翻译：电源电压控制电路
公开(公告)号：US07426147B2
公开(公告)日：2008-09-16
申请号：US11531163
申请日：2006-09-12
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C11/22
摘要： A power supply voltage control circuit supplying a power supply voltage to a memory cell array, including word lines extending along row direction, bit lines extending along column direction, plate lines extending along the row direction, and a plurality of unit cells disposed at intersections of word lines and bit lines, includes a word line control circuit for supplying a first voltage to the word lines; and a plate line control circuit for supplying a second voltage to the plate lines; and the power supply voltage control circuit provides an amount of current flow from the first voltage so as to keep the first voltage potential almost constant during increasing a value of the second voltage in a power-on sequence, firstly increasing a value of the higher voltage of two potential voltages: the first voltage and the second voltage capacitive coupled, and then increasing a value of the lower second voltage.
摘要翻译： 1.一种电源电压控制电路，其向存储单元阵列供给电源电压，所述电源电压包括沿着行方向延伸的字线，沿着列方向延伸的位线，沿着行方向延伸的板条，以及设置在字线和位线包括用于向字线提供第一电压的字线控制电路; 以及板线控制电路，用于向所述板线提供第二电压; 并且电源电压控制电路提供从第一电压的电流量，以便在增加通电序列中的第二电压的值时，保持第一电压电位几乎恒定，首先增加较高电压的值的两个电位电压：第一电压和第二电压电容耦合，然后增加较低的第二电压的值。

15. 发明申请

US20080111575A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20080111575A1
公开(公告)日：2008-05-15
申请号：US11937056
申请日：2007-11-08
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G01R31/27
CPC分类号： G01R31/3004 , G11C29/12005 , G11C29/50
摘要： According to an aspect of the invention, there is provided, a semiconductor device, including an internal voltage generation circuit generating a prescribed voltage, a first test circuit connecting to a voltage-supplying wiring, one end of the voltage-supplying wiring being connected to a source wiring and the other end of the voltage-supplying wiring being connected to the internal voltage generation circuit, the first test circuit being supplied an outer voltage from the source wiring and a voltage of the internal voltage generation circuit through the voltage-supplying wiring, the first test circuit generating a prescribed resistance value on a basis of a control input from an outer portion in a test mode.
摘要翻译：根据本发明的一个方面，提供了一种半导体器件，包括产生规定电压的内部电压产生电路，连接到电压供给布线的第一测试电路，所述电压供给布线的一端连接到源极布线和电压供给布线的另一端连接到内部电压产生电路，第一测试电路通过电压布线从源极布线提供外部电压和内部电压产生电路的电压，所述第一测试电路基于来自测试模式中的外部的控制输入而产生规定的电阻值。

16. 发明授权

US07295456B2 Chain ferroelectric random access memory (CFRAM) having an intrinsic transistor connected in parallel with a ferroelectric capacitor 有权
标题翻译：具有与铁电电容器并联连接的本征晶体管的链式铁电随机存取存储器（CFRAM）
公开(公告)号：US07295456B2
公开(公告)日：2007-11-13
申请号：US11382098
申请日：2006-05-08
申请人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
发明人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
摘要翻译：链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线通过开关晶体管，放大该位线及其互补位线的电压的读出放大器以及插在开关晶体管和读出放大器之间的晶体管。作为板线电压和比较放大的升压期间获得的晶体管中的栅极电压的最小值的值小于在板线掉电期间获得的晶体管中的栅极电压的最大值电压和比较放大。利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

17. 发明申请

US20070121404A1 Temperature sensing circuit, voltage generation circuit, and semiconductor storage device 失效
标题翻译：温度检测电路，电压产生电路和半导体存储装置
公开(公告)号：US20070121404A1
公开(公告)日：2007-05-31
申请号：US11599363
申请日：2006-11-15
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G11C7/02
CPC分类号： G11C29/02 , G11C5/147 , G11C7/04 , G11C7/062 , G11C7/14 , G11C11/22 , G11C29/026 , G11C29/028 , G11C2029/5002 , G11C2207/065
摘要： A first bit line is connected to a memory cell. A second bit line is connected to a dummy cell having a dummy capacitor, and supplied with an electric potential which is complementary to the electric potential of the first bit line. A sense amplifier compares and amplifies the first and second bit lines. A sense amplifier supply voltage generation circuit supplies the sense amplifier with a sense amplifier supply voltage to be used in the comparison and amplification by the sense amplifier. The sense amplifier supply voltage is supplied to a reference potential generation circuit. When data is read out from the memory cell to the first bit line, the reference potential generation circuit supplies, to the second bit line via the dummy cell, a reference potential which fluctuates with a positive correlation to the fluctuation in sense amplifier supply voltage.
摘要翻译：第一位线连接到存储器单元。第二位线连接到具有虚拟电容器的虚拟单元，并且提供与第一位线的电位互补的电位。读出放大器比较和放大第一和第二位线。读出放大器电源电压产生电路为读出放大器提供读出放大器电源电压，以便由读出放大器进行比较和放大。读出放大器电源电压被提供给参考电位产生电路。当数据从存储单元读出到第一位线时，参考电位产生电路经由虚拟单元向第二位线提供与读出放大器电源电压的波动成正相关的波动的基准电位。

18. 发明申请

US20070109834A1 Ferroelectric memory to be tested by applying disturbance voltage to a plurality of ferroelectric capacitors at once in direction to weaken polarization, and method of testing the same 失效
标题翻译：通过在多个强电介质电容器上施加干扰电压以便弱化极化的方向进行测试的铁电存储器及其测试方法
公开(公告)号：US20070109834A1
公开(公告)日：2007-05-17
申请号：US11417154
申请日：2006-05-04
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C11/223 , G11C29/06 , G11C29/08 , G11C29/12005 , G11C2029/1204
摘要： A unit cell is formed by a ferroelectric capacitor and first MOS transistor, and a block is formed by connecting a plurality of unit cells in series. The gates of the first MOS transistors in the individual unit cells are connected to word lines, which are selectively driven by a word line driver on the basis of a row address signal. A plate line is connected to one terminal of the block, and driven by a plate line driver. A bit line is connected to the other terminal of the block via a second MOS transistor for block selection, and selected by a column decoder on the basis of a column address. A driver/controller controls the plate line driver and column decoder to apply a potential difference between the plate line and bit line, while a plurality of word lines are kept off.
摘要翻译：单元由铁电电容器和第一MOS晶体管形成，并且通过串联连接多个单元电池而形成块。单个单元电池中的第一MOS晶体管的栅极连接到字线，该字线由字线驱动器基于行地址信号选择性地驱动。板线连接到块的一个端子，并由板线驱动器驱动。位线通过用于块选择的第二MOS晶体管连接到块的另一端，并且由列解码器基于列地址选择。驱动器/控制器控制板线驱动器和列解码器以在板线和位线之间施加电位差，同时多个字线被保持关闭。

19. 发明申请

US20070058420A1 POWER SUPPLY VOLTAGE CONTROL CIRCUIT 失效
标题翻译：电源电压控制电路
公开(公告)号：US20070058420A1
公开(公告)日：2007-03-15
申请号：US11531163
申请日：2006-09-12
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G11C11/00
CPC分类号： G11C5/147 , G11C11/22
摘要： A power supply voltage control circuit supplying a power supply voltage to a memory cell array, including word lines extending along row direction, bit lines extending along column direction, plate lines extending along the row direction, and a plurality of unit cells disposed at intersections of word lines and bit lines, includes a word line control circuit for supplying a first voltage to the word lines; and a plate line control circuit for supplying a second voltage to the plate lines; and the power supply voltage control circuit provides an amount of current flow from the first voltage so as to keep the first voltage potential almost constant during increasing a value of the second voltage in a power-on sequence, firstly increasing a value of the higher voltage of two potential voltages: the first voltage and the second voltage capacitive coupled, and then increasing a value of the lower second voltage.
摘要翻译： 1.一种电源电压控制电路，其向存储单元阵列供给电源电压，所述电源电压包括沿着行方向延伸的字线，沿着列方向延伸的位线，沿着行方向延伸的板条，以及设置在字线和位线包括用于向字线提供第一电压的字线控制电路; 以及板线控制电路，用于向所述板线提供第二电压; 并且电源电压控制电路提供从第一电压的电流量，以便在增加通电序列中的第二电压的值时，保持第一电压电位几乎恒定，首先增加较高电压的值的两个电位电压：第一电压和第二电压电容耦合，然后增加较低的第二电压的值。

20. 发明授权

US07061788B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US07061788B2
公开(公告)日：2006-06-13
申请号：US11037109
申请日：2005-01-19
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A semiconductor storage device comprises first and second memory cells, each connected to the first pair of word line and bit line and a second pair of word line and bit line, a sense amplifier connected between the first and second bit lines, a first capacitor whose storage electrode being connected to the first bit line, a second capacitor whose storage electrode being connected to the second bit line, first and second wires respectively connected to the first and second plate electrodes of the first and second capacitors, wherein the first and second bit lines are in a complementary relation, and when “0” is read to the first bit line, the first capacitor has an operation to increase a potential of the first plate electrode through the first wire before the sense amplifier operates.
摘要翻译：半导体存储装置包括第一和第二存储单元，每个存储单元连接到第一对字线和位线，第二对字线和位线，连接在第一和第二位线之间的读出放大器，第一电容器，存储电极连接到第一位线，第二电容器，其存储电极连接到第二位线，第一和第二线分别连接到第一和第二电容器的第一和第二平板电极，其中第一和第二位线是互补关系的，并且当对第一位线读取“0”时，第一电容器具有在读出放大器操作之前通过第一引线增加第一平板电极的电位的操作。

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