专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US5802003A System for implementing write, initialization, and reset in a memory array using a single cell write port 失效
标题翻译：用于使用单个单元写入端口在存储器阵列中实现写入，初始化和复位的系统
公开(公告)号：US5802003A
公开(公告)日：1998-09-01
申请号：US575422
申请日：1995-12-20
申请人： Joseph Andrew Iadanza , Frank Ray Keyser, III , Ralph David Kilmoyer , Michael Joseph Laramie
发明人： Joseph Andrew Iadanza , Frank Ray Keyser, III , Ralph David Kilmoyer , Michael Joseph Laramie
IPC分类号： G11C11/41 , G11C8/16 , G11C7/00 , G11C8/00
CPC分类号： G11C8/16
摘要： A system is provided for providing functional, initialization and reset access to a plurality of memory cells of a memory array, using a single cell write port and a single cell read port. In addition to functional address and data buses, initialization address and data buses are provided. The invention is disclosed in association with a field-programmable memory array having multiple sub-arrays therein. The address units for each sub-array are provided to programmably provide address information to the wordlines of each sub-array from an initialization address bus or a functional address bus. Similarly, readhead and writehead circuits within each sub-array are also programmable to propagate data between initialization or functional data buses and the memory cells of the sub-array. The address units, readheads, and writeheads are all responsive to a dominant reset signal to reset the associated cells. An initialization select bus is disclosed for selecting a given sub-array of the multiple sub-arrays for the initialization function. A programming or configuration system for the field-programmable memory array is disclosed with additional units for operating the address and data buses, address units, readheads, writeheads, and the initialization buses.
摘要翻译：提供了一种系统，用于使用单个单元写入端口和单个单元读取端口来提供对存储器阵列的多个存储器单元的功能，初始化和复位访问。除了功能地址和数据总线之外，还提供了初始化地址和数据总线。与其中具有多个子阵列的现场可编程存储器阵列相关联地公开本发明。提供每个子阵列的地址单元以可编程地从初始化地址总线或功能地址总线向每个子阵列的字线提供地址信息。类似地，每个子阵列内的读头和写头电路也可编程，以在初始化或功能数据总线与子阵列的存储单元之间传播数据。地址单元，读取头和写头都响应于主要复位信号以复位相关联的单元。公开了用于选择用于初始化功能的多个子阵列的给定子阵列的初始化选择总线。公开了用于操作地址和数据总线，地址单元，读取头，写入头和初始化总线的附加单元的现场可编程存储器阵列的编程或配置系统。

12. 发明授权

US6075745A Field programmable memory array 有权
标题翻译：现场可编程存储阵列
公开(公告)号：US6075745A
公开(公告)日：2000-06-13
申请号：US190628
申请日：1998-11-12
申请人： Scott Whitney Gould , Joseph Andrew Iadanza , Frank Ray Keyser, III , Victor Paul Seidel , Terrance John Zittritsch
发明人： Scott Whitney Gould , Joseph Andrew Iadanza , Frank Ray Keyser, III , Victor Paul Seidel , Terrance John Zittritsch
IPC分类号： G06F5/10 , G06F7/78 , G11C5/00 , G11C7/00 , G11C7/10 , G11C7/12 , G11C8/00 , H03K19/177
CPC分类号： G06F7/785 , G06F5/10 , G11C7/1006 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C7/12 , G11C8/00 , H03K19/17704 , H03K19/1776
摘要： A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.
摘要翻译：提供具有多个子阵列的现场可编程存储器阵列。提供可编程地址解码器，可编程分层位线布置，可编程I / O布置等功能，以使阵列的部分能够编程成选定的模式。这些模式可以包括宽存储器，深存储器，FIFO，LIFO等。公开了本发明的实施例，其中现场可编程存储器阵列与现场可编程门阵列的可编程资源集成。

13. 发明授权

US6038192A Memory cells for field programmable memory array 有权
标题翻译：现场可编程存储器阵列的存储单元
公开(公告)号：US6038192A
公开(公告)日：2000-03-14
申请号：US189391
申请日：1998-11-10
申请人： Kim P. N. Clinton , Joseph Andrew Iadanza , Frank Ray Keyser, III , Victor Paul Seidel , Terrance John Zittritsch
发明人： Kim P. N. Clinton , Joseph Andrew Iadanza , Frank Ray Keyser, III , Victor Paul Seidel , Terrance John Zittritsch
IPC分类号： G06F5/10 , G06F7/78 , G11C5/00 , G11C7/00 , G11C7/10 , G11C7/12 , G11C8/00 , H03K19/177
CPC分类号： G06F7/785 , G06F5/10 , G11C7/1006 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C7/12 , G11C8/00 , H03K19/17704 , H03K19/1776
摘要： A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.
摘要翻译：提供具有多个子阵列的现场可编程存储器阵列。提供可编程地址解码器，可编程分层位线布置，可编程I / O布置等功能，以使阵列的部分能够编程成选定的模式。这些模式可以包括宽存储器，深存储器，FIFO，LIFO等。公开了本发明的实施例，其中现场可编程存储器阵列与现场可编程门阵列的可编程资源集成。

14. 发明授权

US6021513A Testable programmable gate array and associated LSSD/deterministic test methodology 失效
标题翻译：可测量可编程门阵列和相关的LSSD /确定性测试方法
公开(公告)号：US6021513A
公开(公告)日：2000-02-01
申请号：US181736
申请日：1998-10-28
申请人： Wayne Kevin Beebe , Sally Botala , Scott Whitney Gould , Frank Ray Keyser, III , Wendell Ray Larsen , Ronald Raymond Palmer , Brian Worth
发明人： Wayne Kevin Beebe , Sally Botala , Scott Whitney Gould , Frank Ray Keyser, III , Wendell Ray Larsen , Ronald Raymond Palmer , Brian Worth
IPC分类号： G01R31/317 , G01R31/28 , G01R31/3185 , G06F11/22 , H01L21/82
CPC分类号： G01R31/318519 , G01R31/318558
摘要： A programmable gate array includes test subsystems for testing various functional subsystems of the programmable gate array. A sequence of test methods, employing the test subsystems, test the functionality of the programmable gate array, taking into account the interdependencies of the various subsystems and accordingly enabling fault isolation therein.
摘要翻译：可编程门阵列包括用于测试可编程门阵列的各种功能子系统的测试子系统。采用测试子系统的一系列测试方法测试可编程门阵列的功能，考虑到各个子系统的相互依赖关系，从而使其中的故障隔离成为可能。

15. 发明授权

US5717346A Low skew multiplexer network and programmable array clock/reset application thereof 失效
标题翻译：低偏斜多路复用器网络及其可编程阵列时钟/复位应用
公开(公告)号：US5717346A
公开(公告)日：1998-02-10
申请号：US709074
申请日：1996-09-06
申请人： Scott Whitney Gould , Frederick Curtis Furtek , Frank Ray Keyser, III , Brian A. Worth , Terrance John Zittritsch
发明人： Scott Whitney Gould , Frederick Curtis Furtek , Frank Ray Keyser, III , Brian A. Worth , Terrance John Zittritsch
IPC分类号： G06F15/78 , G06F1/10 , H01L21/82 , H03K19/0175 , H03K19/173 , H03K19/177 , H03K19/00
CPC分类号： H03K19/1774 , H03K19/1737 , H03K19/17704
摘要： A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering and output driver sizing as a function of signal propagation distance.
摘要翻译：公开了一种用于可编程阵列中的时钟和复位信号分配的信号分配架构。该架构包括用于将时钟和复位信号分配给阵列的逻辑单元的单独网络。每个网络包括多个列复用器，用于从多个系统时钟或复位信号中选择列时钟或复位信号。在逻辑单元的每列中，定位了用于从多个列时钟或复位信号中选择扇区时钟或复位信号的扇区多路复用器。时钟和复位信号被施加到与给定扇区多路复用器相关联的每个逻辑单元的组合和顺序逻辑电路。时钟门电路与每个逻辑单元中的输出多路复用器协同控制。网络被设计为具有最小化信号偏移的特征，包括作为信号传播距离的函数的信号源缓冲，多路复用器信号缓冲和输出驱动器尺寸。

16. 发明授权

US5703498A Programmable array clock/reset resource 失效
标题翻译：可编程阵列时钟/复位资源
公开(公告)号：US5703498A
公开(公告)日：1997-12-30
申请号：US709060
申请日：1996-09-06
申请人： Scott Whitney Gould , Frederick Curtis Furtek , Frank Ray Keyser, III , Brian A. Worth , Terrance John Zittritsch
发明人： Scott Whitney Gould , Frederick Curtis Furtek , Frank Ray Keyser, III , Brian A. Worth , Terrance John Zittritsch
IPC分类号： G06F15/78 , G06F1/10 , H01L21/82 , H03K19/0175 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1774 , H03K19/1737 , H03K19/17704
摘要： A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering and output driver sizing as a function of signal propagation distance.
摘要翻译：公开了一种用于可编程阵列中的时钟和复位信号分配的信号分配架构。该架构包括用于将时钟和复位信号分配给阵列的逻辑单元的单独网络。每个网络包括多个列复用器，用于从多个系统时钟或复位信号中选择列时钟或复位信号。在逻辑单元的每列中，定位了用于从多个列时钟或复位信号中选择扇区时钟或复位信号的扇区多路复用器。时钟和复位信号被施加到与给定扇区多路复用器相关联的每个逻辑单元的组合和顺序逻辑电路。时钟门电路与每个逻辑单元中的输出多路复用器协同控制。网络被设计为具有最小化信号偏移的特征，包括作为信号传播距离的函数的信号源缓冲，多路复用器信号缓冲和输出驱动器尺寸。

17. 发明授权

US5652529A Programmable array clock/reset resource 失效
标题翻译：可编程阵列时钟/复位资源
公开(公告)号：US5652529A
公开(公告)日：1997-07-29
申请号：US459156
申请日：1995-06-02
申请人： Scott Whitney Gould , Frederick Curtis Furtek , Frank Ray Keyser, III , Brian A. Worth , Terrance John Zittritsch
发明人： Scott Whitney Gould , Frederick Curtis Furtek , Frank Ray Keyser, III , Brian A. Worth , Terrance John Zittritsch
IPC分类号： G06F15/78 , G06F1/10 , H01L21/82 , H03K19/0175 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1774 , H03K19/1737 , H03K19/17704
摘要： A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering, and output driver sizing as a function of signal propagation distance.
摘要翻译：公开了一种用于可编程阵列中的时钟和复位信号分配的信号分配架构。该架构包括用于将时钟和复位信号分配给阵列的逻辑单元的单独网络。每个网络包括多个列复用器，用于从多个系统时钟或复位信号中选择列时钟或复位信号。在逻辑单元的每列中，定位了用于从多个列时钟或复位信号中选择扇区时钟或复位信号的扇区多路复用器。时钟和复位信号被施加到与给定扇区多路复用器相关联的每个逻辑单元的组合和顺序逻辑电路。时钟门电路与每个逻辑单元中的输出多路复用器协同控制。网络被设计为具有最小化信号偏移的特征，包括信号源缓冲，多路复用器信号缓冲和作为信号传播距离的函数的输出驱动器尺寸。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式