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11. 发明申请

US20130119435A1 DIELECTRIC DUMMIFICATION FOR ENHANCED PLANARIZATION WITH SPIN-ON DIELECTRICS 审中-公开
标题翻译：具有旋转电介质的增强平面化的电介质
公开(公告)号：US20130119435A1
公开(公告)日：2013-05-16
申请号：US13296672
申请日：2011-11-15
申请人： Thomas Dungan
发明人： Thomas Dungan
IPC分类号： H01L29/737 , H01L23/52 , H01L21/768
CPC分类号： H01L21/76802 , H01L21/76819 , H01L29/737
摘要： An integrated device includes a lower layer pattern on a semiconductor substrate. The lower layer pattern includes a first region including first electrical devices and a second region including second electrical devices and electrically nonconductive dummy devices. A first device density of the first electrical devices in the first region is substantially greater than a second device density of the second electrical devices in the second region. A partially-planarizing dielectric layer is disposed on the lower layer pattern so as to cover the first electrical devices, the second electrical devices, and the electrically nonconductive dummy devices. The average height of the partially-planarizing dielectric layer in the first region is approximately the same as the average height in the second region. Through-holes are formed in the first region, and an electrically conductive material is disposed in the through-holes.
摘要翻译：集成器件包括半导体衬底上的下层图案。下层图案包括包括第一电气装置的第一区域和包括第二电气装置和非导电的虚设装置的第二区域。第一区域中的第一电气设备的第一器件密度基本上大于第二区域中的第二电子器件的第二器件密度。部分平坦化的介电层设置在下层图案上，以便覆盖第一电气装置，第二电气装置和非导电的虚设装置。第一区域中的部分平坦化介电层的平均高度与第二区域中的平均高度大致相同。在第一区域中形成通孔，并且在通孔中设置导电材料。

12. 发明申请

US20120182651A1 Shared Electrostatic Discharge Protection For Integrated Circuits, Integrated Circuit Assemblies And Methods For Protecting Input/Output Circuits 审中-公开
标题翻译：用于集成电路的共享静电放电保护，集成电路组件和用于保护输入/输出电路的方法
公开(公告)号：US20120182651A1
公开(公告)日：2012-07-19
申请号：US13009664
申请日：2011-01-19
申请人： Thomas Dungan , Phillip Nikkel
发明人： Thomas Dungan , Phillip Nikkel
IPC分类号： H02H9/00 , H01L23/52
CPC分类号： H01L27/0251 , H01L23/60 , H01L24/05 , H01L24/08 , H01L24/11 , H01L24/13 , H01L24/81 , H01L25/0657 , H01L2224/0401 , H01L2224/05572 , H01L2224/05666 , H01L2224/05684 , H01L2224/0801 , H01L2224/11462 , H01L2224/1147 , H01L2224/11912 , H01L2224/13022 , H01L2224/13147 , H01L2224/1411 , H01L2224/14515 , H01L2224/16145 , H01L2224/81193 , H01L2224/81815 , H01L2224/81931 , H01L2225/06513 , H01L2225/06537 , H01L2924/00013 , H01L2924/00014 , H01L2924/01029 , H01L2924/13034 , H01L2924/14 , H01L2924/01074 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552
摘要： A method for protecting input/output (I/O) circuits on an integrated circuit (IC) from electrostatic discharge (ESD) is disclosed. The method includes the steps of providing at least one protective device on a surface of a first semiconductor die and applying a conductive shorting layer over a select region of the surface to electrically couple at least one metallic stud to the at least one protective device. After bonding the IC die to a second IC die and/or testing one or more core circuits, the conductive shorting layer is removed to enable high-speed I/O connections arranged in the select region of the semiconductor die. An IC assembly includes first and second semiconductor dice. One of the dice includes a protective device along a surface. An electrically conductive shorting layer couples the protective device to a conductive element that is further coupled to I/O circuit elements.
摘要翻译：公开了一种用于保护集成电路（IC）上的输入/输出（I / O）电路免受静电放电（ESD）影响的方法。该方法包括以下步骤：在第一半导体管芯的表面上提供至少一个保护器件，并且在表面的选择区域上施加导电短路层，以将至少一个金属钉电耦合到至少一个保护器件。在将IC管芯连接到第二IC管芯和/或测试一个或多个核心电路之后，去除导电短路层，以实现布置在半导体管芯的选择区域中的高速I / O连接。 IC组件包括第一和第二半导体管芯。骰子之一包括沿表面的保护装置。导电短路层将保护装置耦合到进一步耦合到I / O电路元件的导电元件。

13. 发明申请

US20070262355A1 Pixel with asymmetric transfer gate channel doping 有权
标题翻译：具有不对称传输栅极通道掺杂的像素
公开(公告)号：US20070262355A1
公开(公告)日：2007-11-15
申请号：US11707848
申请日：2007-02-16
申请人： Chintamani Palsule , Changhoon Choi , Fredrick LaMaster , John Stanback , Thomas Dungan , Thomas Joy , Homayoon Haddad
发明人： Chintamani Palsule , Changhoon Choi , Fredrick LaMaster , John Stanback , Thomas Dungan , Thomas Joy , Homayoon Haddad
IPC分类号： H01L27/148
CPC分类号： H01L27/14643 , H01L27/14601 , H01L29/66659 , H01L31/035281
摘要： A pixel including a substrate of a first conductivity type and having a surface, a photodetector of a second conductivity type that is opposite the first conductivity type, a floating diffusion region of the second conductivity type, a transfer region between the photodetector and the floating diffusion, a gate positioned above the transfer region and partially overlapping the photodetector, and a pinning layer of the first conductivity type extending at least across the photodetector from the gate. A channel implant of the first conductivity type extending from between a midpoint of the transfer gate and the floating diffusion to at least across the photodiode and having a dopant concentration such that a dopant concentration of the transfer region is greater proximate to the photodetector than the floating diffusion, and wherein a peak dopant concentration of the channel implant is at a level and at a depth below the surface such that a partially-buried channel is formed in the transfer region between the photodiode and floating diffusion when the transfer gate is energized.
摘要翻译：包括具有第一导电类型并具有表面的衬底的像素，与第一导电类型相反的第二导电类型的光电检测器，第二导电类型的浮动扩散区域，光电检测器和浮动扩散区之间的传输区域位于所述转印区域上方并且部分地与所述光电检测器重叠的栅极以及至少从所述栅极延伸穿过所述光电检测器的所述第一导电类型的钉扎层。第一导电类型的沟道植入物从传输栅极的中点和浮动扩散延伸到至少跨越光电二极管并具有掺杂剂浓度，使得传输区域的掺杂剂浓度在接近光电检测器处比浮置扩散，并且其中沟道注入的峰值掺杂剂浓度处于表面以下的水平和深度，使得当传输栅极通电时，在光电二极管和浮动扩散之间的传输区域中形成部分埋置的沟道。

14. 发明授权

US06437379B1 Integrated circuit device providing isolation between adjacent regions 有权
公开(公告)号：US06437379B1
公开(公告)日：2002-08-20
申请号：US09863854
申请日：2001-05-22
申请人： Thomas Edward Kopley , Dietrich W. Vook , Thomas Dungan
发明人： Thomas Edward Kopley , Dietrich W. Vook , Thomas Dungan
IPC分类号： H01L31062
摘要： A fabrication method for providing isolation between adjacent regions of an integrated circuit includes providing a guard layer over field edges that are the interfaces between field oxide regions and diffusion regions in which dopant is introduced. The guard layer will inhibit introduction of dopant along the field-edge, so that a substantially dopant-free transition strip is formed. The transition strip inhibits current leakage from the active region to the field oxide region. In one embodiment, the active region is an active area diode, such as used to form an Active Pixel Sensor (APS) pixel. The guard layer is biased so as to further inhibit current leakage during circuit operation. In another embodiment, the method is used in the fabrication of transistors for APS pixels having an overlay photodiode structure.

15. 发明授权

US06417074B2 Method of manufacturing a structure for reducing leakage currents by providing isolation between adjacent regions of an integrated circuit 有权
标题翻译：通过在集成电路的相邻区域之间提供隔离来制造用于减少泄漏电流的结构的方法
公开(公告)号：US06417074B2
公开(公告)日：2002-07-09
申请号：US09863851
申请日：2001-05-22
申请人： Thomas Edward Kopley , Dietrich W Vook , Thomas Dungan
发明人： Thomas Edward Kopley , Dietrich W Vook , Thomas Dungan
IPC分类号： H01L2176
CPC分类号： H01L21/761 , H01L27/14603 , H01L27/14609 , H01L27/14689
摘要： A fabrication method for providing isolation between adjacent regions of an integrated circuit includes providing a guard layer over field edges that are the interfaces between field oxide regions and diffusion regions in which dopant is introduced. The guard layer will inhibit introduction of dopant along the field-edge, so that a substantially dopant-free transition strip is formed. The transition strip inhibits current leakage from the active region to the field oxide region. In one embodiment, the active region is an active area diode, such as used to form an Active Pixel Sensor (APS) pixel. The guard layer is biased so as to further inhibit current leakage during circuit operation. In another embodiment, the method is used in the fabrication of transistors for APS pixels having an overlay photodiode structure.
摘要翻译：用于在集成电路的相邻区域之间提供隔离的制造方法包括在场边缘上提供保护层，该边缘是场氧化物区域和引入掺杂剂的扩散区域之间的界面。保护层将抑制沿着场边缘引入掺杂剂，从而形成基本上无掺杂剂的过渡带。过渡条禁止从有源区到场氧化物区的电流泄漏。在一个实施例中，有源区域是有源区二极管，例如用于形成有源像素传感器（APS）像素。保护层被偏压，以便在电路操作期间进一步抑制电流泄漏。在另一个实施例中，该方法用于制造具有覆盖光电二极管结构的APS像素的晶体管。

16. 发明授权

US06350663B1 Method for reducing leakage currents of active area diodes and source/drain diffusions 有权
标题翻译：减少有源区二极管和源极/漏极扩散漏电流的方法
公开(公告)号：US06350663B1
公开(公告)日：2002-02-26
申请号：US09517635
申请日：2000-03-03
申请人： Thomas Edward Kopley , Dietrich W Vook , Thomas Dungan
发明人： Thomas Edward Kopley , Dietrich W Vook , Thomas Dungan
IPC分类号： H01L2176
CPC分类号： H01L21/761 , H01L27/14603 , H01L27/14609 , H01L27/14689
摘要： A fabrication method for providing isolation between adjacent regions of an integrated circuit includes providing a guard layer over field edges that are the interfaces between field oxide regions and diffusion regions in which dopant is introduced. The guard layer will inhibit introduction of dopant along the field-edge, so that a substantially dopant-free transition strip is formed. The transition strip inhibits current leakage from the active region to the field oxide region. In one embodiment, the active region is an active area diode, such as used to form an Active Pixel Sensor (APS) pixel. The guard layer is biased so as to further inhibit current leakage during circuit operation. In another embodiment, the method is used in the fabrication of transistors for APS pixels having an overlay photodiode structure.
摘要翻译：用于在集成电路的相邻区域之间提供隔离的制造方法包括在场边缘上提供保护层，该边缘是场氧化物区域和引入掺杂剂的扩散区域之间的界面。保护层将抑制沿着场边缘引入掺杂剂，从而形成基本上无掺杂剂的过渡带。过渡条禁止从有源区到场氧化物区的电流泄漏。在一个实施例中，有源区域是有源区二极管，例如用于形成有源像素传感器（APS）像素。保护层被偏压，以便在电路操作期间进一步抑制电流泄漏。在另一个实施例中，该方法用于制造具有覆盖光电二极管结构的APS像素的晶体管。

17. 发明授权

US5311391A Electrostatic discharge protection circuit with dynamic triggering 失效
标题翻译：具有动态触发功能的静电放电保护电路
公开(公告)号：US5311391A
公开(公告)日：1994-05-10
申请号：US57277
申请日：1993-05-04
申请人： Thomas Dungan , Eugene Coussens
发明人： Thomas Dungan , Eugene Coussens
IPC分类号： H01L23/60 , H01L21/822 , H01L27/04 , H01L27/06 , H02H9/04 , H03F1/52 , H02H9/00
CPC分类号： H02H9/046 , H01L2924/0002
摘要： Electrostatic discharge (ESD) protection circuitry having a string of diode-connected field-effect transistors (FETs) connected between a bus and ground plane for triggering a shunt element, such as a large n-channel FET, connected between the same or a different bus and the ground plane. The bus or buses are diode-connected through the base-emitter junction of pnp transistors to signal pads, as well as to a positive voltage power supply. The string of FETs turns on when the pad-to-ground voltage, and thus the bus-to-ground voltage, exceeds a threshold characteristic of an ESD event. The string acts as a voltage divider to bring a node between two of the FETs up to a voltage that will activate an n-channel trigger FET, which is part of a resistive-load inverter. This drives another inverter that in turn drives the shunt FET. When the voltage is pulled back down below the threshold voltage, the shunt FET continues to shunt current to the ground plane for the duration of the ESD event.
摘要翻译：静电放电（ESD）保护电路，其具有连接在总线和接地平面之间的二极管连接的场效应晶体管串，用于触发连接在相同或不同之间的诸如大型n沟道FET的分流元件公共汽车和地面飞机。总线或总线通过pnp晶体管的基极 - 发射极结到信号焊盘以及正电压电源进行二极管连接。当焊盘对地电压，从而总线对地电压超过ESD事件的阈值特性时，一串FET导通。该串用作分压器，以使两个FET之间的节点达到将激活作为电阻负载逆变器的一部分的n沟道触发FET的电压。这驱动另一个逆变器，继而驱动分流FET。当电压被拉回低于阈值电压时，在ESD事件的持续时间内，并联FET继续将电流分流到接地层。

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