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11. 发明授权

US07067434B2 Hydrogen free integration of high-k gate dielectrics 有权
标题翻译：高k栅极电介质的无氢结合
公开(公告)号：US07067434B2
公开(公告)日：2006-06-27
申请号：US10745449
申请日：2003-12-22
申请人： Luigi Colombo , James J. Chambers , Mark R. Visokay
发明人： Luigi Colombo , James J. Chambers , Mark R. Visokay
IPC分类号： H01L21/302
CPC分类号： H01L21/28194 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/31111 , H01L21/3144 , H01L21/3145 , H01L21/31608 , H01L21/3185 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6656 , H01L29/6659 , Y10S438/91 , Y10S438/954
摘要： The present invention pertains to forming a transistor in the absence of hydrogen, or in the presence of a significantly reduced amount of hydrogen. In this manner, a high-k material can be utilized to form a gate dielectric layer in the transistor and facilitate device scaling while mitigating defects that can be introduced into the high-k material by the presence of hydrogen and/or hydrogen containing compounds.
摘要翻译：本发明涉及在不存在氢的情况下形成晶体管，或者在显着减少量的氢的存在下。以这种方式，可以利用高k材料在晶体管中形成栅极电介质层，并且便于器件缩放，同时减轻可通过存在氢和/或含氢化合物引入高k材料的缺陷。

12. 发明授权

US06797599B2 Gate structure and method 有权
标题翻译：门结构和方法
公开(公告)号：US06797599B2
公开(公告)日：2004-09-28
申请号：US10232124
申请日：2002-08-30
申请人： Mark R. Visokay , Antonio L. P. Rotondaro , Luigi Colombo
发明人： Mark R. Visokay , Antonio L. P. Rotondaro , Luigi Colombo
IPC分类号： H01L213205
CPC分类号： H01L21/28185 , H01L21/28114 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/823857 , H01L29/42376 , H01L29/517 , H01L29/518 , H01L29/66545
摘要： A MOSFSET structure with high-k gate dielecttrics for silicon or metal gates with gate dielectric liquid-based oxidation surface treatments prior to gate material desposition and gate formation.
摘要翻译：一种具有高k栅极介质的MOSFSET结构，用于在栅极材料沉积和栅极形成之前的栅极介质液体氧化表面处理的硅或金属栅极。

13. 发明授权

US07135361B2 Method for fabricating transistor gate structures and gate dielectrics thereof 有权
标题翻译：制造晶体管栅极结构及其栅极电介质的方法
公开(公告)号：US07135361B2
公开(公告)日：2006-11-14
申请号：US10734708
申请日：2003-12-11
申请人： Mark R. Visokay , Luigi Colombo , James J. Chambers , Antonio L. P. Rotondaro , Haowen Bu
发明人： Mark R. Visokay , Luigi Colombo , James J. Chambers , Antonio L. P. Rotondaro , Haowen Bu
IPC分类号： H01L21/336
CPC分类号： H01L21/28185 , H01L21/02148 , H01L21/02271 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/28202 , H01L21/3144 , H01L21/3162 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L29/517 , H01L29/518
摘要： Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more oxidizing anneals to mitigate material defects, and to a nitridation process to introduce nitrogen into the gate dielectric. The annealing may be performed before and/or after the nitridation to mitigate deposition and/or nitridation defects and to densify the material while mitigating formation of unwanted low dielectric constant oxides at the interface between the gate dielectric and the semiconductor substrate.
摘要翻译：公开了用于处理沉积的栅极电介质材料的方法，其中沉积的电介质经受一个或多个非氧化退火以致密化材料，一个或多个氧化退火以减轻材料缺陷，以及氮化过程以将氮引入栅电介质。可以在氮化之前和/或之后进行退火以减轻沉积和/或氮化缺陷并致密材料，同时减轻在栅极电介质和半导体衬底之间的界面处形成不想要的低介电常数氧化物。

14. 发明授权

US07115530B2 Top surface roughness reduction of high-k dielectric materials using plasma based processes 有权
标题翻译：使用基于等离子体工艺的高k介电材料的顶表面粗糙度降低
公开(公告)号：US07115530B2
公开(公告)日：2006-10-03
申请号：US10726987
申请日：2003-12-03
申请人： Manuel A. Quevedo-Lopez , James J. Chambers , Luigi Colombo , Mark R. Visokay
发明人： Manuel A. Quevedo-Lopez , James J. Chambers , Luigi Colombo , Mark R. Visokay
IPC分类号： H01L21/31
CPC分类号： H01L21/0234 , C23C16/401 , C23C16/405 , C23C16/56 , H01L21/02175 , H01L21/02181 , H01L21/02194 , H01L21/3105 , H01L21/31053 , H01L21/3143 , H01L21/3144 , H01L21/31604 , H01L21/31645 , H01L21/31691
摘要： A system and method for manufacturing semiconductor devices with dielectric layers having a dielectric constant greater than silicon dioxide includes depositing a dielectric layer on a substrate and subjecting the dielectric layer to a plasma to reduce top surface roughness in the dielectric layer.
摘要翻译：具有介电常数大于二氧化硅的电介质层的半导体器件的系统和方法包括在基片上沉积电介质层并对介电层进行等离子体以减小电介质层中的顶表面粗糙度。

15. 发明授权

US07109077B2 Dual work function gate electrodes using doped polysilicon and a metal silicon germanium compound 有权
标题翻译：使用掺杂多晶硅和金属硅锗化合物的双功函数栅电极
公开(公告)号：US07109077B2
公开(公告)日：2006-09-19
申请号：US10301224
申请日：2002-11-21
申请人： Antonio L. P. Rotondaro , Mark R. Visokay , Luigi Colombo
发明人： Antonio L. P. Rotondaro , Mark R. Visokay , Luigi Colombo
IPC分类号： H01L21/8238 , H01L21/3205
CPC分类号： H01L21/28097 , H01L21/823842 , H01L29/4975
摘要： A dielectric layer (50) is formed over a semiconductor (10) that contains a first region (20) and a second region (30). A polysilicon layer is formed over the dielectric layer (50) and over the first region (20) and the second region (30). The polysilicon layer can comprise 0 to 50 atomic percent of germanium. A metal layer is formed over the polysilicon layer and one of the regions and reacted with the underlying polysilicon layer to form a metal silicide or a metal germano silicide. The polysilicon and metal silicide or germano silicide regions are etched to form transistor gate regions (60) and (90) respectively. If desired a cladding layer (100) can be formed above the metal gate structures.
摘要翻译：在包含第一区域（20）和第二区域（30）的半导体（10）上形成介电层（50）。在电介质层（50）上并在第一区域（20）和第二区域（30）之上形成多晶硅层。多晶硅层可以包含0至50原子％的锗。在多晶硅层和其中一个区域上形成金属层，并与下面的多晶硅层反应形成金属硅化物或金属锗化硅。蚀刻多晶硅和金属硅化物或锗硅化物区域以分别形成晶体管栅极区域（60）和（90）。如果需要，可以在金属栅极结构上方形成包覆层（100）。

16. 发明授权

US07105891B2 Gate structure and method 有权
标题翻译：门结构和方法
公开(公告)号：US07105891B2
公开(公告)日：2006-09-12
申请号：US10195271
申请日：2002-07-15
申请人： Mark R. Visokay , Antonio L. P. Rotondaro , Luigi Colombo
发明人： Mark R. Visokay , Antonio L. P. Rotondaro , Luigi Colombo
IPC分类号： H01L29/94
CPC分类号： H01L29/495 , H01L21/28079 , H01L21/823842
摘要： CMOS gate structure with metal gates having differing work functions by texture differences between NMOS and PMOS gates.
摘要翻译：具有金属栅极的CMOS栅极结构具有由NMOS和PMOS栅极之间的纹理差异而具有不同功函数。

17. 发明授权

US07098516B2 Refractory metal-based electrodes for work function setting in semiconductor devices 有权
$Refractory metal-based electrodes for work function setting in semiconductor devices$
标题翻译：用于半导体器件功能设置的耐火金属基电极
公开(公告)号：US07098516B2
公开(公告)日：2006-08-29
申请号：US10852523
申请日：2004-05-24
申请人： Luigi Colombo , James J. Chambers , Mark R. Visokay
发明人： Luigi Colombo , James J. Chambers , Mark R. Visokay
IPC分类号： H01L29/94
CPC分类号： H01L21/823842 , H01L29/4958
摘要： The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).
摘要翻译：本发明在一个实施例中提供一种栅极结构（100）。栅极结构包括栅极电介质（105）和栅极（110）。栅极电介质包括难熔金属并且位于半导体衬底（115）之上。半导体衬底具有导带和价带。栅极位于栅极电介质上方并且包括难熔金属。栅极具有与导带或价带对准的功函数。其他实施例包括替代栅极结构（200），形成用于半导体器件（301）的栅极结构（300）和双栅极集成电路（400）的方法。

18. 发明授权

US06770521B2 Method of making multiple work function gates by implanting metals with metallic alloying additives 有权
标题翻译：通过金属合金添加剂注入金属制作多功能门的方法
公开(公告)号：US06770521B2
公开(公告)日：2004-08-03
申请号：US10135725
申请日：2002-04-29
申请人： Mark R. Visokay , Antonio L. P. Rotondaro , Luigi Colombo
发明人： Mark R. Visokay , Antonio L. P. Rotondaro , Luigi Colombo
IPC分类号： H01L218238
CPC分类号： H01L21/823857 , H01L21/823842
摘要： A method of forming a first and second transistors with differing work function gates by differing metals with a second metal selectively implanted or diffused into a first metal.
摘要翻译：通过不同金属形成具有不同功函数栅极的第一和第二晶体管的方法，其中第二金属选择性地注入或扩散到第一金属中。

19. 发明授权

US06211034B1 Metal patterning with adhesive hardmask layer 失效
标题翻译：金属图案与粘合剂硬掩模层
公开(公告)号：US06211034B1
公开(公告)日：2001-04-03
申请号：US09059546
申请日：1998-04-13
申请人： Mark R. Visokay , Luigi Colombo , Paul McIntyre , Scott R. Summerfelt
发明人： Mark R. Visokay , Luigi Colombo , Paul McIntyre , Scott R. Summerfelt
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/32139 , H01L27/1085
摘要： An adherent hardmask structure and method of etching a bottom electrode in memory device capacitor structures that dispenses with the need for any adhesion promoter during the etching of the bottom electrode. By using silicon nitride as a hardmask 220, the processing is simplified and a more robust capacitor structure can be produced. Silicon nitride 220 has been shown to yield significantly enhanced adhesion to platinum 210, as compared to silicon oxide formed by any method. Since silicon nitride 220 is oxidation resistant, it advantageously resists any oxygen plasma that might be used in the etch chemistry. This etching process can be used during processing of high-k capacitor structures in DRAMs in the ≧256 Mbit generations.
摘要翻译：一种粘附硬掩模结构和蚀刻存储器件电容器结构中的底部电极的方法，其在底部电极的蚀刻期间省去了对任何粘附促进剂的需要。通过使用氮化硅作为硬掩模220，简化了处理，并且可以产生更坚固的电容器结构。与通过任何方法形成的氧化硅相比，已经显示氮化硅220产生显着增强的与铂210的粘合性。由于氮化硅220是抗氧化的，所以它有利地抵抗可能在蚀刻化学中使用的任何氧等离子体。这种蚀刻工艺可以在> = 256Mbit的DRAM中的高k电容器结构的处理期间使用。

20. 发明授权

US5972722A Adhesion promoting sacrificial etch stop layer in advanced capacitor structures 失效
标题翻译：先进的电容器结构中的粘附促进牺牲蚀刻停止层
公开(公告)号：US5972722A
公开(公告)日：1999-10-26
申请号：US60152
申请日：1998-04-14
申请人： Mark R. Visokay , Luigi Colombo , Paul McIntyre , Scott R. Summerfelt
发明人： Mark R. Visokay , Luigi Colombo , Paul McIntyre , Scott R. Summerfelt
IPC分类号： H01L21/02 , H01L21/311 , H01L21/8242 , H01G7/06
CPC分类号： H01L27/1085 , H01L21/31116 , H01L28/55 , H01L28/60
摘要： A high-k dielectric capacitor structure and fabrication method that incorporates an adhesion promoting etch stop layer 200 to promote adhesion of the bottom electrode 220 to the interlevel dielectric layer 210 and to provide a well controlled, repeatable and uniform recess prior to the dielectric 230 deposition. By using a sacrificial layer 200, for example silicon nitride (Si3N4), this layer can act as an etch stop during the recess etch to eliminate parasitic capacitance between adjacent capacitor cells A and B and can promote adhesion of the bottom electrode material 220 to the substrate 210.
摘要翻译：高k电介质电容器结构和制造方法，其包含粘附促进蚀刻停止层200以促进底部电极220粘附到层间电介质层210，并且在电介质230沉积之前提供良好控制的，可重复的和均匀的凹部。通过使用牺牲层200（例如氮化硅（Si 3 N 4）），该层可以在凹陷蚀刻期间用作蚀刻停止以消除相邻的电容器电池A和B之间的寄生电容，并且可以促进底部电极材料220与衬底210。

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