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11. 发明授权

US07382200B2 Type-II all-digital phase-locked loop (PLL) 有权
标题翻译： II型全数字锁相环（PLL）
公开(公告)号：US07382200B2
公开(公告)日：2008-06-03
申请号：US11464420
申请日：2006-08-14
申请人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad
发明人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad
IPC分类号： H03L7/00
CPC分类号： H03L7/1075 , H03F1/0211 , H03F1/3282 , H03L7/093 , H03L7/0991 , H03L7/107 , H03L2207/50
摘要： System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.
摘要翻译：用于提供具有快速信号采集模式的II型（和更高阶）锁相环（PLL）的系统和方法。优选实施例包括具有比例环路增益路径（比例环路增益电路1115）和积分环路增益模块（积分环路增益模块1120）的环路滤波器。在信号采集期间使用比例环路增益路径来提供较大的环路带宽，从而快速获取所需信号的信号。然后，在PLL的信号跟踪阶段期间，使用积分环路增益模块，并将其输出与比例环路增益路径的输出相结合，以提供所需信号的高阶滤波。可以测量和减去由于使用比例环路增益路径而可能存在的偏移量，以帮助改善信号跟踪稳定时间。

12. 发明授权

US07218904B2 Removing close-in interferers through a feedback loop 有权
标题翻译：通过反馈回路消除紧密的干扰源
公开(公告)号：US07218904B2
公开(公告)日：2007-05-15
申请号：US10280156
申请日：2002-10-25
申请人： Robert B. Staszewski , Khurram Muhammad , Dirk Leipold
发明人： Robert B. Staszewski , Khurram Muhammad , Dirk Leipold
IPC分类号： H04B1/06 , H03F1/26
CPC分类号： H04B1/28 , H04B1/1036
摘要： System and method for elimination of close-in interferers through feedback. A preferred embodiment comprises an interferer predictor (for example, interferer predictor 840) coupled to a digital output of a direct RF radio receiver (for example, radio receiver 800). The interferer predictor predicts the presence of interferers and feeds the information back to a sampling unit (for example, sampling unit 805) through a feedback circuit (for example, feedback unit 845) through the use of charge sharing. The interferers are then eliminated in the sampling unit. Additionally, the number and placement of zeroes in a filter in the sampling unit is increased and changed through the implementation of arbitrary-coefficient finite impulse response filters.
摘要翻译：通过反馈消除接近干扰的系统和方法。优选实施例包括耦合到直接RF无线电接收机（例如，无线电接收机800）的数字输出的干扰源预测器（例如，干扰源预测器840）。干扰源预测器预测干扰源的存在，并且通过使用电荷共享通过反馈电路（例如，反馈单元845）将信息反馈给采样单元（例如，采样单元805）。然后在采样单元中消除干扰源。另外，通过执行任意系数有限脉冲响应滤波器来增加和改变采样单元滤波器中的零数和位置。

13. 发明授权

US07519135B2 Direct radio frequency (RF) sampling with recursive filtering method 有权
标题翻译：直接射频（RF）采样采用递归滤波法
公开(公告)号：US07519135B2
公开(公告)日：2009-04-14
申请号：US10190867
申请日：2002-07-08
申请人： Robert B. Staszewski , Khurram Muhammad , Kenneth J. Maggio , Dirk Leipold
发明人： Robert B. Staszewski , Khurram Muhammad , Kenneth J. Maggio , Dirk Leipold
IPC分类号： H03K5/01
CPC分类号： H03D7/125 , H04B1/1036
摘要： A radio receiver 2000 with a sampling mixer 1100 for creating a discrete-time sample stream by directly sampling an RF current with history and rotating capacitors 1111 and 1112, wherein the accumulated charge on the rotating capacitors is read-out to produce a sample. The mixer provides immunity to noise glitches by predicting the occurrence of the glitch (or detecting a significant difference between observed and predicted samples) and creating corrected samples for the corrupted samples. These corrected samples can be created with special circuitry 1933 (digital) or in the mixer 1100 (analog).
摘要翻译：具有采样混合器1100的无线电接收机2000，用于通过用历史和旋转电容器1111和1112直接采样RF电流来产生离散时间采样流，其中读出旋转电容器上的累积电荷以产生样本。混合器通过预测毛刺的发生（或检测观察到的和预测的样品之间的显着差异）并为损坏的样品产生校正的样品来提供对噪声毛刺的免疫。这些校正样本可以用专用电路1933（数字）或混合器1100（模拟）来创建。

14. 发明申请

US20090196384A1 Direct Radio Frequency (RF) Sampling With Recursive Filtering Method 审中-公开
标题翻译：直接射频（RF）采样递归滤波方法
公开(公告)号：US20090196384A1
公开(公告)日：2009-08-06
申请号：US12334268
申请日：2008-12-12
申请人： Robert B. Staszewski , Khurram Muhammad , Kenneth J. Maggio , Dirk Leipold
发明人： Robert B. Staszewski , Khurram Muhammad , Kenneth J. Maggio , Dirk Leipold
IPC分类号： H03D1/04
CPC分类号： H03D7/125 , H04B1/1036
摘要： A radio receiver 2000 with a sampling mixer 1100 for creating a discrete-time sample stream by directly sampling an RF current with history and rotating capacitors 1111 and 1112, wherein the accumulated charge on the rotating capacitors is read-out to produce a sample. The mixer provides immunity to noise glitches by predicting the occurrence of the glitch (or detecting a significant difference between observed and predicted samples) and creating corrected samples for the corrupted samples. These corrected samples can be created with special circuitry 1933 (digital) or in the mixer 1100 (analog).
摘要翻译：具有采样混合器1100的无线电接收机2000，用于通过用历史和旋转电容器1111和1112直接采样RF电流来产生离散时间采样流，其中读出旋转电容器上的累积电荷以产生样本。混合器通过预测毛刺的发生（或检测观察到的和预测的样品之间的显着差异）并为损坏的样品产生校正的样品来提供对噪声毛刺的免疫。这些校正样本可以用专用电路1933（数字）或混合器1100（模拟）来创建。

15. 发明授权

US07463873B2 Wireless communications device having type-II all-digital phase-locked loop (PLL) 有权
标题翻译：具有II型全数字锁相环（PLL）的无线通信设备
公开(公告)号：US07463873B2
公开(公告)日：2008-12-09
申请号：US11122670
申请日：2005-05-04
申请人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad
发明人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad
IPC分类号： H03L7/093
CPC分类号： H03L7/1075 , H03F1/0211 , H03F1/3282 , H03L7/093 , H03L7/0991 , H03L7/107 , H03L2207/50
摘要： System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a wireless communication device having a loop filter with a proportional loop gain path (proportional loop gain circuit 1115 ) and an integral loop gain block (integral loop gain block 1120 ). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the intergral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.
摘要翻译：用于提供具有快速信号采集模式的II型（和更高阶）锁相环（PLL）的系统和方法。优选实施例包括具有带有比例环路增益路径（比例环路增益电路1115）和积分环路增益块（积分环路增益块1120）的环路滤波器的无线通信设备。在信号采集期间使用比例环路增益路径来提供较大的环路带宽，从而快速获取所需信号的信号。然后，在PLL的信号跟踪阶段期间，使用积分环路增益模块，并将其输出与比例环路增益路径的输出相结合，以提供所需信号的高阶滤波。可以测量和减去由于使用比例环路增益路径而可能存在的偏移量，以帮助改善信号跟踪稳定时间。

16. 发明授权

US07145399B2 Type-II all-digital phase-locked loop (PLL) 有权
标题翻译： II型全数字锁相环（PLL）
公开(公告)号：US07145399B2
公开(公告)日：2006-12-05
申请号：US10464957
申请日：2003-06-19
申请人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad
发明人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad
IPC分类号： H03D3/24
CPC分类号： H03L7/1075 , H03F1/0211 , H03F1/3282 , H03L7/093 , H03L7/0991 , H03L7/107 , H03L2207/50
摘要： System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.
摘要翻译：用于提供具有快速信号采集模式的II型（和更高阶）锁相环（PLL）的系统和方法。优选实施例包括具有比例环路增益路径（比例环路增益电路1115）和积分环路增益模块（积分环路增益模块1120）的环路滤波器。在信号采集期间使用比例环路增益路径来提供较大的环路带宽，从而快速获取所需信号的信号。然后，在PLL的信号跟踪阶段期间，使用积分环路增益模块，并将其输出与比例环路增益路径的输出相结合，以提供所需信号的高阶滤波。可以测量和减去由于使用比例环路增益路径而可能存在的偏移量，以帮助改善信号跟踪稳定时间。

17. 发明授权

US07405685B2 Negative contributive offset compensation in a transmit buffer utilizing inverse clocking 有权
标题翻译：使用反向时钟的发送缓冲器中的负贡献偏移补偿
公开(公告)号：US07405685B2
公开(公告)日：2008-07-29
申请号：US11178993
申请日：2005-07-11
申请人： Sameh S. Rezeq , Dirk Leipold , Robert B. Staszewski , Chih-Ming Hung
发明人： Sameh S. Rezeq , Dirk Leipold , Robert B. Staszewski , Chih-Ming Hung
IPC分类号： H03M3/00
CPC分类号： H03F1/0205 , H03F1/3241 , H03F2200/331 , H03F2200/375 , H03M3/356 , H03M3/50 , H03M7/3026 , H03M7/3037 , H04L27/368
摘要： A novel method and apparatus for a negative contributive offset compensation mechanism for a transmit buffer adapted to compensate for the positive offset generated by higher order sigma-delta modulators used to amplitude modulate the transmit buffer. The positive outputs from the sigma-delta modulator are processed differently than the negative outputs. The inverters associated with the negative outputs in the sigma-delta modulator are removed and the clock signal used to drive the transistors corresponding to the negative outputs is negated or shifted 180 degrees from the clock used to drive the transistors corresponding to the positive outputs. A non-inverted version of the clock is used with the positive outputs and an inverse clock is used with the negative outputs. Use of the inverse clock causes a negative contributive offset to be generated that is added on the second half cycle of each clock. The result is an offset compensated RF output signal having zero offset.
摘要翻译：一种用于发射缓冲器的负贡献偏移补偿机制的新颖方法和装置，适用于补偿由用于幅度调制发射缓冲器的高阶Σ-Δ调制器产生的正偏移。来自Σ-Δ调制器的正输出的处理方式与负输出不同。与Σ-Δ调制器中的负输出相关联的反相器被去除，并且用于驱动对应于负输出的晶体管的时钟信号与用于驱动对应于正输出的晶体管的时钟相反或偏移180度。时钟的非反相版本与正输出一起使用，反向时钟与负输出一起使用。使用逆时钟将产生在每个时钟的第二个半周期上添加的负贡献偏移。结果是具有零偏移的偏移补偿RF输出信号。

18. 发明授权

US07463869B2 Low noise high isolation transmit buffer gain control mechanism 有权
标题翻译：低噪声高隔离传输缓冲器增益控制机制
公开(公告)号：US07463869B2
公开(公告)日：2008-12-09
申请号：US11115815
申请日：2005-04-26
申请人： Chih-Ming Hung , Francis P. Cruise , Dirk Leipold , Robert B. Staszewski
发明人： Chih-Ming Hung , Francis P. Cruise , Dirk Leipold , Robert B. Staszewski
IPC分类号： H04B1/04
CPC分类号： H04B1/0483 , H03F1/3241 , H03F1/3294 , H03F3/191 , H03F2200/331
摘要： A novel apparatus for a low noise, high isolation, all digital transmit buffer gain control mechanism. The gain control scheme is presented in the context of an all digital direct digital-to-RF amplitude converter (DRAC), which efficiently combines the traditional transmit chain functions of upconversion, I and Q combining, D/A conversion, filtering, buffering and RF output amplitude control into a single circuit. The transmit buffer is constructed as an array of NMOS switches. The control logic for each NMOS switch comprises a pass-gate type AND gate whose inputs are the phase modulated output of an all digital PLL and the amplitude control word from a digital control block. Power control is accomplished by recognizing the impairments suffered by a pseudo class E pre-power amplifier (PPA) when implemented in a CMOS process. Firstly, the NMOS switches of the array have significant on resistance and thus can only draw a limited current from the an RF choke when the input waveform is high. The significant on resistance of the NMOS switches is exploited in the DRAC circuit to introduce power control of the transmitted waveform and permits a fully digital method of controlling the RF output power.
摘要翻译：一种低噪声，高隔离，全数字发送缓冲增益控制机制的新型设备。增益控制方案在全数字直接数/频幅度转换器（DRAC）的上下文中呈现，该转换器有效地结合了上变频，I和Q组合，D / A转换，滤波，缓冲和 RF输出幅度控制成单个电路。发送缓冲器构造为NMOS开关阵列。每个NMOS开关的控制逻辑包括一个通门型AND门，其输入是全数字PLL的相位调制输出和来自数字控制块的幅度控制字。通过在CMOS工艺中实现时，通过识别伪E类预功率放大器（PPA）所遭受的损伤来实现功率控制。首先，阵列的NMOS开关具有大的导通电阻，因此当输入波形为高时，只能从RF扼流圈画出有限的电流。在DRAC电路中利用NMOS开关的重要导通电阻来引入发射波形的功率控制，并允许控制RF输出功率的全数字方法。

19. 发明授权

US07647192B2 Active removal of aliasing frequencies in a decimating structure by changing a decimation ratio in time and space 有权
标题翻译：通过在时间和空间上改变抽取比例，在抽取结构中主动去除混叠频率
公开(公告)号：US07647192B2
公开(公告)日：2010-01-12
申请号：US10924297
申请日：2004-08-23
申请人： Khurram Muhammad , Robert B. Staszewski , Gennady Feygin
发明人： Khurram Muhammad , Robert B. Staszewski , Gennady Feygin
IPC分类号： G06F19/00
CPC分类号： H03D7/125 , H04B1/1036
摘要： When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer 800 with capacitor banks 811 and 812 that are controlled by a digital control unit 820 with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.
摘要翻译：当采样流被抽取时，来自期望频带外部的频率分量被混叠成所需频带，导致信息的干扰和丢失。不同的抽取率导致不同的频率混叠成所需的频带。具有电容器组811和812的电流模式采样混频器800能够以不同的抽取率对能够集成和抽取RF电流的数字控制单元820进行控制，能够以不同的抽取率来测量频谱。然后分析测量的频谱以检测混叠到期望频带中的干扰源的存在。然后可以消除或避免干扰源。

20. 发明授权

US07466777B2 Active removal of aliasing frequencies in a decimating structure by changing a decimation ratio in time and space 有权
标题翻译：通过在时间和空间上改变抽取比例，在抽取结构中主动去除混叠频率
公开(公告)号：US07466777B2
公开(公告)日：2008-12-16
申请号：US10924159
申请日：2004-08-23
申请人： Khurram Muhammad , Robert B. Staszewski , Gennady Feygin
发明人： Khurram Muhammad , Robert B. Staszewski , Gennady Feygin
IPC分类号： H03D1/04
CPC分类号： H03D7/125 , H04B1/1036
摘要： When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer 800 with capacitor banks 811 and 812 that are controlled by a digital control unit 820 with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.
摘要翻译：当采样流被抽取时，来自期望频带外部的频率分量被混叠成所需频带，导致信息的干扰和丢失。不同的抽取率导致不同的频率混叠成所需的频带。具有电容器组811和812的电流模式采样混频器800能够以不同的抽取率对能够集成和抽取RF电流的数字控制单元820进行控制，能够以不同的抽取率来测量频谱。然后分析测量的频谱以检测混叠到期望频带中的干扰源的存在。然后可以消除或避免干扰源。

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