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11. 发明授权

US08530284B2 Method of forming a bi-directional transistor with by-pass path 有权
标题翻译：用旁通路径形成双向晶体管的方法
公开(公告)号：US08530284B2
公开(公告)日：2013-09-10
申请号：US13324682
申请日：2011-12-13
申请人： Francine Y. Robb , Stephen P. Robb
发明人： Francine Y. Robb , Stephen P. Robb
IPC分类号： H01L21/332
CPC分类号： H03K17/063 , H01L21/823487 , H01L21/823885 , H01L27/088 , H01L27/0922 , H03K17/687 , H03K2217/0018
摘要： In one embodiment, a transistor is formed to have a first current flow path to selectively conduct current in both directions through the transistor and to have a second current flow path to selectively conduct current in one direction.
摘要翻译：在一个实施例中，晶体管被形成为具有第一电流流动路径，以选择性地在两个方向上导通电流通过晶体管，并且具有第二电流流动路径以选择性地在一个方向上导通电流。

12. 发明授权

US08207035B2 Method of forming an integrated power device and structure 有权
标题翻译：形成集成电力装置和结构的方法
公开(公告)号：US08207035B2
公开(公告)日：2012-06-26
申请号：US12696816
申请日：2010-01-29
申请人： Francine Y. Robb , Stephen P. Robb , Prasad Venkatraman , Zia Hossain
发明人： Francine Y. Robb , Stephen P. Robb , Prasad Venkatraman , Zia Hossain
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/823487 , H01L21/823885 , H01L27/088 , H01L27/0922 , H01L29/0878 , H01L29/66734
摘要： In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.
摘要翻译：在一个实施例中，在具有其它晶体管的半导体衬底上形成垂直功率晶体管。垂直功率晶体管下面的半导体层的一部分被掺杂以为垂直功率晶体管提供低导通电阻。

13. 发明授权

US08039359B2 Method of forming low capacitance ESD device and structure therefor 有权
标题翻译：低容量ESD器件的形成方法及其结构
公开(公告)号：US08039359B2
公开(公告)日：2011-10-18
申请号：US12395076
申请日：2009-02-27
申请人： Thomas Keena , Ki Chang , Francine Y. Robb , Mingjiao Liu , Ali Salih , John Michael Parsey, Jr. , George Chang
发明人： Thomas Keena , Ki Chang , Francine Y. Robb , Mingjiao Liu , Ali Salih , John Michael Parsey, Jr. , George Chang
IPC分类号： H01L21/76 , H01L23/62
CPC分类号： H01L29/8613 , H01L27/0255 , H01L29/8618 , Y10S257/929 , Y10S438/966 , Y10S438/983
摘要： In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.
摘要翻译：在一个实施例中，ESD器件使用ESD器件内深度的高掺杂P和N区域形成具有受控击穿电压的齐纳二极管。

14. 发明申请

US20100237409A1 SEMICONDUCTOR COMPONENT 有权
标题翻译：半导体元件
公开(公告)号：US20100237409A1
公开(公告)日：2010-09-23
申请号：US12790987
申请日：2010-06-01
申请人： Prasad Venkatraman , Gordon M. Grivna , Francine Y. Robb , George Chang , Carroll Casteel
发明人： Prasad Venkatraman , Gordon M. Grivna , Francine Y. Robb , George Chang , Carroll Casteel
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0696 , H01L29/41766 , H01L29/4236 , H01L29/42376 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material.
摘要翻译：能够抑制寄生双极型晶体管的形成的半导体元件和使用减少数量的掩模步骤来制造半导体元件的方法。提供具有P型导电性区域的N型导电性的半导体材料。在P型导电性区域形成N型导电性的掺杂区域。沟槽形成在半导体材料中并延伸通过N型和P型导电性的区域。由半导体材料形成场氧化物，使得沟槽的部分在场氧化物的下方延伸。场氧化物在源区的形成中用作注入掩模。主体接触区域由半导体材料形成，并且形成与源区和身体区域接触的电导体。形成与半导体材料的背面接触的电导体。

15. 发明授权

US07538395B2 Method of forming low capacitance ESD device and structure therefor 有权
标题翻译：低容量ESD器件的形成方法及其结构
公开(公告)号：US07538395B2
公开(公告)日：2009-05-26
申请号：US11859570
申请日：2007-09-21
申请人： Thomas Keena , Ki Chang , Francine Y. Robb , Mingjiao Liu , Ali Salih , John Michael Parsey, Jr. , George Chang
发明人： Thomas Keena , Ki Chang , Francine Y. Robb , Mingjiao Liu , Ali Salih , John Michael Parsey, Jr. , George Chang
IPC分类号： H01L23/62 , G11C11/36 , H01L21/00
CPC分类号： H01L29/8613 , H01L27/0255 , H01L29/8618 , Y10S257/929 , Y10S438/966 , Y10S438/983
摘要： In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.
摘要翻译：在一个实施例中，ESD器件使用ESD器件内深度的高掺杂P和N区域形成具有受控击穿电压的齐纳二极管。

16. 发明授权

US07297603B2 Bi-directional transistor and method therefor 有权
标题翻译：双向晶体管及其方法
公开(公告)号：US07297603B2
公开(公告)日：2007-11-20
申请号：US11093381
申请日：2005-03-31
申请人： Stephen P. Robb , Francine Y. Robb , Robert F. Hightower
发明人： Stephen P. Robb , Francine Y. Robb , Robert F. Hightower
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/086 , H01L29/0878 , H01L29/7803 , H01L29/7835 , H03K3/3565 , H03K17/063 , H03K17/687
摘要： In one embodiment, a transistor is formed to conduct current in both directions through the transistor.
摘要翻译：在一个实施例中，形成晶体管以在两个方向上通过晶体管导通电流。

17. 发明授权

US07030447B2 Low voltage transient voltage suppressor 有权
标题翻译：低压瞬变电压抑制器
公开(公告)号：US07030447B2
公开(公告)日：2006-04-18
申请号：US10620259
申请日：2003-07-15
申请人： Francine Y. Robb , Jeffrey Pearse , David M. Heminger , Stephen P. Robb
发明人： Francine Y. Robb , Jeffrey Pearse , David M. Heminger , Stephen P. Robb
IPC分类号： H01L23/62
CPC分类号： H01L29/7816 , H01L24/05 , H01L27/0623 , H01L29/41741 , H01L29/7801 , H01L29/7802 , H01L29/7813 , H01L2224/04042 , H01L2224/48091 , H01L2924/1305 , H01L2924/13055 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A method of providing a Transient Voltage Suppression (TVS) device is described utilizing a Metal Oxide Semiconductor (MOS) structure and an Insulated Gate Bipolar Transistor (IGBT) structure. The MOS based TVS devices offer reduced leakage current with reduced clamp voltages between 0.5 and 5 volts. Trench MOS based TVS device (72) provides an enhanced gain operation, while device (88) provides a top side drain contact. The high gain MOS based TVS devices provide increased control over clamp voltage variation.
摘要翻译：使用金属氧化物半导体（MOS）结构和绝缘栅双极晶体管（IGBT）结构来描述提供瞬态电压抑制（TVS）器件的方法。基于MOS的TVS器件提供减少的漏电流，钳位电压在0.5和5伏之间。基于沟槽MOS的TVS设备（72）提供增强的增益操作，而设备（88）提供顶侧漏极接触。基于高增益MOS的TVS器件可以提高对钳位电压变化的控制。

18. 发明授权

US4529860A Plasma etching of organic materials 失效
标题翻译：有机材料的等离子体蚀刻
公开(公告)号：US4529860A
公开(公告)日：1985-07-16
申请号：US403995
申请日：1982-08-02
申请人： Francine Y. Robb
发明人： Francine Y. Robb
IPC分类号： C08J7/00 , H01L21/302 , H01L21/3065 , H01L21/311 , B23K9/00
CPC分类号： H01L21/31138 , H01L21/311
摘要： A method is provided for anisotropically etching organic material to reduce mask undercutting. The layer of organic material to be patterned, with an overlying patterning mask is provided on a substrate. The substrate with the layer of organic material on it is placed on the powered electrode within a plasma reactor. A hydrogen plasma is generated in the reactor at a pressure between about 13.3 Pa and about 53 Pa. The organic layer which is not protected by the etch mask is etched by the hydrogen plasma. At these pressures the organic layer is removed by a process of ion assisted etching in which the hydrogen plasma chemically reacts with the organic material and the reaction is enhanced by ionic bombardment of the plasma species. Because the substrate and the organic material are placed on the powered electrode, the plasma ions impact the surface of the organic layer in a direction substantially perpendicular to the surface of the layer thus providing anisotropy to the etch.
摘要翻译：提供了一种用于各向异性蚀刻有机材料以减少掩模底切的方法。在基板上设置有图案化的有机材料层，具有上覆图案掩模。其上具有有机材料层的衬底被放置在等离子体反应器内的动力电极上。在反应器中在约13.3Pa至约53Pa之间的压力下产生氢等离子体，用氢等离子体蚀刻未被蚀刻掩模保护的有机层。在这些压力下，通过离子辅助蚀刻的过程去除有机层，其中氢等离子体与有机材料发生化学反应，并且通过等离子体物质的离子轰击增强反应。因为衬底和有机材料被放置在动力电极上，等离子体离子在基本上垂直于层的表面的方向上冲击有机层的表面，从而提供蚀刻的各向异性。

19. 发明申请

US20130248982A1 SEMICONDUCTOR DEVICE WITH ENHANCED MOBILITY AND METHOD 有权
公开(公告)号：US20130248982A1
公开(公告)日：2013-09-26
申请号：US13895197
申请日：2013-05-15
申请人： Gordon M. Grivna , Zia Hossain , Kirk K. Huang , Balaji Padmanabhan , Francine Y. Robb , Prasad Venkatraman
发明人： Gordon M. Grivna , Zia Hossain , Kirk K. Huang , Balaji Padmanabhan , Francine Y. Robb , Prasad Venkatraman
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7845 , H01L29/0869 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/42376 , H01L29/456 , H01L29/66666 , H01L29/66727 , H01L29/66734 , H01L29/7811 , H01L29/7813 , H01L29/7827 , H01L29/7842 , H01L29/7848
摘要： In one embodiment, a vertical insulated-gate field effect transistor includes a feature embedded within a control electrode. The feature is placed within the control electrode to induce stress within predetermined regions of the transistor.

20. 发明授权

US08101969B2 Bi-directional transistor with by-pass path and method therefor 有权
标题翻译：具有旁路的双向晶体管及其方法
公开(公告)号：US08101969B2
公开(公告)日：2012-01-24
申请号：US13023255
申请日：2011-02-08
申请人： Francine Y. Robb , Stephen P. Robb
发明人： Francine Y. Robb , Stephen P. Robb
IPC分类号： H01L29/66
CPC分类号： H03K17/063 , H01L21/823487 , H01L21/823885 , H01L27/088 , H01L27/0922 , H03K17/687 , H03K2217/0018
摘要： In one embodiment, a transistor is formed to have a first current flow path to selectively conduct current in both directions through the transistor and to have a second current flow path to selectively conduct current in one direction.
摘要翻译：在一个实施例中，晶体管被形成为具有第一电流流动路径，以选择性地在两个方向上导通电流通过晶体管，并且具有第二电流流动路径以选择性地在一个方向上导通电流。

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