专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20090310400A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090310400A1
公开(公告)日：2009-12-17
申请号：US12545379
申请日：2009-08-21
申请人： Riichiro Takemura , Takayuki Kawahara , Kenchi Ito , Hiromasa Takahashi
发明人： Riichiro Takemura , Takayuki Kawahara , Kenchi Ito , Hiromasa Takahashi
IPC分类号： G11C11/02
CPC分类号： G11C11/16 , G11C8/08 , G11C11/1675 , H01L27/228
摘要： In MRAM using a spin-transfer torque switching, a sufficient writing operation with a small memory cell is realized, and a reading current is enlarged while a reading disturbance is suppressed. In the case where the free layer of the tunnel magneto-resistance element is located on the side of the bit line, using a PMOS transistor, and in the case where the fixed layer of the tunnel magneto-resistance element is located on the side of the bit line, using an NMOS transistor, an anti-parallel writing in a source grounding operation is performed. The reading and writing operation margin is improved by performing a reading operation in an anti-parallel writing direction.
摘要翻译：在使用自旋转移转矩切换的MRAM中，实现了具有小存储单元的充分的写入操作，并且在读取干扰被抑制的同时增加读取电流。在隧道磁阻元件的自由层位于位线一侧的情况下，使用PMOS晶体管，并且在隧道磁阻元件的固定层位于使用NMOS晶体管的位线执行源极接地操作中的反并联写入。通过执行反并行写入方向的读取操作来提高读取和写入操作余量。

12. 发明授权

US07224629B2 Memory device having high speed sense amplifier comprising pull-up circuit and pull-down circuits with different drivability for each 有权
标题翻译：具有高速读出放大器的存储器件包括每个具有不同驱动能力的上拉电路和下拉电路
公开(公告)号：US07224629B2
公开(公告)日：2007-05-29
申请号：US11071351
申请日：2005-03-04
申请人： Satoru Akiyama , Riichiro Takemura , Takayuki Kawahara , Tomonori Sekiguchi
发明人： Satoru Akiyama , Riichiro Takemura , Takayuki Kawahara , Tomonori Sekiguchi
IPC分类号： G11C7/02
CPC分类号： G11C11/4091 , G11C7/065 , G11C2207/065 , H01L27/10897
摘要： A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pulldown circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.
摘要翻译：构造读出放大器以减少存储器读取操作中的故障的发生，并因此由于读出放大器随着进一步的封闭而增加偏移而降低了芯片产量。读出放大器电路由多个下拉电路和上拉电路构成，并且多个下拉电路之一中的晶体管具有常数，例如通道长度或通道宽度大于另一个下拉电路中的晶体管。首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。

13. 发明申请

US20060198183A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20060198183A1
公开(公告)日：2006-09-07
申请号：US11337648
申请日：2006-01-24
申请人： Takayuki Kawahara , Kenichi Osada , Riichiro Takemura
发明人： Takayuki Kawahara , Kenichi Osada , Riichiro Takemura
IPC分类号： G11C11/00
CPC分类号： G11C29/50 , G11C13/0004 , G11C29/50016 , G11C2213/79
摘要： With a semiconductor device using a phase change material, in particular, an increase in the number of circuit elements associated with a testing function is checked to the minimum, and an easier test on the semiconductor device is implemented. When a retention test and so forth are conducted on a phase change element, for example, a generated voltage VS1 of a set bit-line voltage power supply, VG_set, provided originally for use in a set operation, is used as a voltage to be applied to the phase change element, and timing when the voltage VS1 is applied to the phase change element is generated by a read/test timing generation circuit TG_rd_test, provided originally to execute a read operation of the phase change element. By so doing, it becomes possible to check an increase in the number of circuit elements, and to conduct the retention test accelerated on a voltage basis with ease.
摘要翻译：对于使用相变材料的半导体器件，特别地，将与测试功能相关联的电路元件的数量的增加最小化，并且实现对半导体器件的更容易的测试。当在相变元件上进行保持测试等时，例如，原来用于设定操作的设定位线电压电源VG_set的发电电压VS 1被用作电压应用于相变元件，并且通过最初为执行相变元件的读取操作而提供的读取/测试定时产生电路TG_rd_test产生电压VS1施加到相变元件的定时。通过这样做，可以检查电路元件的数量的增加，并且容易地在基于电压的基础上进行加速的保持测试。

14. 发明申请

US20060062055A1 Semiconductor memory 失效
公开(公告)号：US20060062055A1
公开(公告)日：2006-03-23
申请号：US11268471
申请日：2005-11-08
申请人： Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata , Kazushige Ayukawa , Takayuki Kawahara
发明人： Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata , Kazushige Ayukawa , Takayuki Kawahara
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C5/025 , G11C7/02 , G11C7/1006 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C11/405 , G11C11/4096 , G11C2207/107
摘要： A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.

15. 发明授权

US06894912B2 Semiconductor memory 失效
公开(公告)号：US06894912B2
公开(公告)日：2005-05-17
申请号：US10760402
申请日：2004-01-21
申请人： Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata , Kazushige Ayukawa , Takayuki Kawahara
发明人： Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata , Kazushige Ayukawa , Takayuki Kawahara
IPC分类号： G11C11/407 , G11C7/10 , G11C11/401 , G11C11/404 , G11C11/409 , G11C11/4096 , G11C15/00 , G11C8/00
CPC分类号： G11C7/1051 , G11C5/025 , G11C7/02 , G11C7/1006 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C11/405 , G11C11/4096 , G11C2207/107
摘要： A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.

16. 发明授权

US06721194B2 Semiconductor memory 有权
公开(公告)号：US06721194B2
公开(公告)日：2004-04-13
申请号：US10287678
申请日：2002-11-05
申请人： Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata , Kazushige Ayukawa , Takayuki Kawahara
发明人： Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata , Kazushige Ayukawa , Takayuki Kawahara
IPC分类号： G11C1500
CPC分类号： G11C7/1051 , G11C5/025 , G11C7/02 , G11C7/1006 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C11/405 , G11C11/4096 , G11C2207/107
摘要： A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.

17. 发明授权

US08427864B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US08427864B2
公开(公告)日：2013-04-23
申请号：US13375751
申请日：2010-06-02
申请人： Takayuki Kawahara , Kiyoo Itoh , Riichiro Takemura , Kenchi Ito
发明人： Takayuki Kawahara , Kiyoo Itoh , Riichiro Takemura , Kenchi Ito
IPC分类号： G11C11/00
CPC分类号： H01L43/08 , G11C11/161 , G11C11/1675 , H01L27/228
摘要： To write information on a memory cell of SPRAM formed of an MOS transistor and a tunnel magnetoresistive element, the memory cell is supplied with a current in a direction opposite to a direction of a current required for writing the information on the memory cell, and then, the memory cell is supplied with a current required for writing. In this manner, even when the same information is sequentially written on the memory cell, since the currents in the two directions are caused to flow in pairs in the tunnel magnetoresistive element of the memory cell each time information is rewritten, deterioration of a film that forms the tunnel magnetoresistive element can be suppressed. Therefore, reliability of the SPRAM can be improved.
摘要翻译：为了在由MOS晶体管和隧道磁阻元件形成的SPRAM的存储单元上写入信息，向存储单元提供与在存储单元上写入信息所需的电流方向相反的方向的电流，然后，为存储单元提供写入所需的电流。以这种方式，即使当相同的信息被顺序地写入存储单元时，由于每当信息被重写时，两个方向上的电流成对地在存储单元的隧道磁阻元件中成对流动，所以，可以抑制隧道磁阻元件的形成。因此，可以提高SPRAM的可靠性。

18. 发明申请

US20130051134A1 SEMICONDUCTOR RECORDING DEVICE 失效
标题翻译：半导体记录装置
公开(公告)号：US20130051134A1
公开(公告)日：2013-02-28
申请号：US13643880
申请日：2011-04-05
申请人： Takayuki Kawahara , Riichiro Takemura , Takashi Ishigaki , Kiyoo Itoh
发明人： Takayuki Kawahara , Riichiro Takemura , Takashi Ishigaki , Kiyoo Itoh
IPC分类号： G11C11/16
CPC分类号： H01L27/228 , G11C7/1006 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1697 , G11C11/5607
摘要： The disclosed semiconductor recording device achieves multi-valued reading and writing using a spin-injection magnetization-reversal tunneling magnetoresistive element (TMR element). A first current that has at least the same value as that of the element requiring the highest current to reverse the magnetization thereof among a plurality of TMR elements is, in the direction that causes reversal to either a parallel state or an anti-parallel state, applied to a memory cell having the plurality of TMR elements, and then a second current which is in the reverse direction from the first current and of which only the value needed to reverse the magnetoresistance state of at least one TMR element excluding the element requiring the maximum current among the plurality of TMR elements is applied to each, and multi-valued writing is performed.
摘要翻译：所公开的半导体记录装置使用自旋注入磁化 - 反转隧道磁阻元件（TMR元件）实现多值读取和写入。与在多个TMR元件之间需要最大电流以使其磁化反转的元件至少具有相同值的第一电流在引起反向并联状态或反并联状态的方向上，应用于具有多个TMR元件的存储单元，然后施加与第一电流相反方向的第二电流，并且其中只有反转至少一个TMR元件的磁阻状态所需的值，除了需要多个TMR元件中的最大电流被施加到每个，并且执行多值写入。

19. 发明申请

US20130033928A1 SEMICONDUCTOR STORAGE DEVICE AND DATA PROCESSING METHOD 有权
标题翻译：半导体存储器件和数据处理方法
公开(公告)号：US20130033928A1
公开(公告)日：2013-02-07
申请号：US13576913
申请日：2010-02-02
申请人： Takayuki Kawahara , Riichiro Takemura , Kazuo Ono , Nobuaki Kohinata
发明人： Takayuki Kawahara , Riichiro Takemura , Kazuo Ono , Nobuaki Kohinata
IPC分类号： G11C11/16
CPC分类号： G11C11/15 , G11C11/16 , G11C11/1653 , G11C11/1657 , G11C11/1675 , G11C11/1693
摘要： Since a nonvolatile RAM allows random reading and writing operations, an erasing mode is unnecessary. From the system side, however, it is desirable to have the erasing mode because of its nonvolatile characteristic. Moreover, the erasing operation is desirably carried out at high speed with low power consumption. Therefore, memory cell arrays COA and DTA containing a plurality of memory cells MC each having a magnetoresistive element are provided, a series of data is written to the memory cell arrays COA and DTA, and at the time of erasing, an erasing operation is carried out by writing predetermined data only to the memory cell array COA.
摘要翻译：由于非易失性RAM允许随机读取和写入操作，因此不需要擦除模式。然而，从系统侧，由于其非易失性特性，期望具有擦除模式。此外，擦除操作期望以低功耗高速进行。因此，提供了包含具有磁阻元件的多个存储单元MC的存储单元阵列COA和DTA，将一系列数据写入存储单元阵列COA和DTA，并且在擦除时，进行擦除操作通过将预定数据仅写入存储单元阵列COA来实现。

20. 发明申请

US20120081952A1 SEMICONDUCTOR STORAGE DEVICE 失效
标题翻译：半导体存储设备
公开(公告)号：US20120081952A1
公开(公告)日：2012-04-05
申请号：US13375751
申请日：2010-06-02
申请人： Takayuki Kawahara , Kiyoo Itoh , Riichiro Takemura , Kenchi Ito
发明人： Takayuki Kawahara , Kiyoo Itoh , Riichiro Takemura , Kenchi Ito
IPC分类号： G11C11/16
CPC分类号： H01L43/08 , G11C11/161 , G11C11/1675 , H01L27/228
摘要： To write information on a memory cell of SPRAM formed of an MOS transistor and a tunnel magnetoresistive element, the memory cell is supplied with a current in a direction opposite to a direction of a current required for writing the information on the memory cell, and then, the memory cell is supplied with a current required for writing. In this manner, even when the same information is sequentially written on the memory cell, since the currents in the two directions are caused to flow in pairs in the tunnel magnetoresistive element of the memory cell each time information is rewritten, deterioration of a film that forms the tunnel magnetoresistive element can be suppressed. Therefore, reliability of the SPRAM can be improved.
摘要翻译：为了在由MOS晶体管和隧道磁阻元件形成的SPRAM的存储单元上写入信息，向存储单元提供与在存储单元上写入信息所需的电流方向相反的方向的电流，然后，为存储单元提供写入所需的电流。以这种方式，即使当相同的信息被顺序地写入存储单元时，由于每当信息被重写时，两个方向上的电流成对地在存储单元的隧道磁阻元件中成对流动，所以，可以抑制隧道磁阻元件的形成。因此，可以提高SPRAM的可靠性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式