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11. 发明授权

US07790581B2 Semiconductor substrate with multiple crystallographic orientations 有权
标题翻译：具有多个晶体取向的半导体衬底
公开(公告)号：US07790581B2
公开(公告)日：2010-09-07
申请号：US11306713
申请日：2006-01-09
申请人： Byeong Y. Kim , Xiaomeng Chen , Woo-Hyeong Lee , Huilong Zhu
发明人： Byeong Y. Kim , Xiaomeng Chen , Woo-Hyeong Lee , Huilong Zhu
IPC分类号： H01L21/20 , H01L21/36 , H01L21/00
CPC分类号： H01L29/1083 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L29/045 , H01L29/0649 , H01L29/78 , H01L29/7848 , H01L29/7849 , H01L29/78603 , H01L29/78654 , H01L29/78687
摘要： A pair of semiconductor structures and a method for fabricating a semiconductor structure each utilize a semiconductor substrate having a first crystallographic orientation, and a dielectric layer located thereupon. The method provides for epitaxially growing a semiconductor layer on the semiconductor substrate to encapsulate the dielectric layer. The method also provides for patterning the semiconductor layer to yield a semiconductor structure that comprises a bulk semiconductor structure and a semiconductor-on-insulator structure, or alternatively a patterned semiconductor layer that straddles the dielectric layer and contacts the semiconductor substrate.
摘要翻译：一对半导体结构和半导体结构的制造方法各自使用具有第一晶体取向的半导体衬底和位于其上的电介质层。该方法提供了在半导体衬底上外延生长半导体层以封装介电层。该方法还提供了图案化半导体层以产生包括体半导体结构和绝缘体上半导体结构的半导体结构，或者替代地跨越电介质层并接触半导体衬底的图案化半导体层。

12. 发明申请

US20080268609A1 STACKING FAULT REDUCTION IN EPITAXIALLY GROWN SILICON 失效
标题翻译：封装在外延硅中的故障减少
公开(公告)号：US20080268609A1
公开(公告)日：2008-10-30
申请号：US12131214
申请日：2008-06-02
申请人： Yun-Yu Wang , Linda Black , Judson R. Holt , Woo-Hyeong Lee , Scott Luning , Christopher D. Sheraw
发明人： Yun-Yu Wang , Linda Black , Judson R. Holt , Woo-Hyeong Lee , Scott Luning , Christopher D. Sheraw
IPC分类号： H01L21/76
CPC分类号： H01L21/02639 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02609 , H01L21/84
摘要： Methods are disclosed for providing stacking fault reduced epitaxially grown silicon for use in hybrid surface orientation structures. In one embodiment, a method includes depositing a silicon nitride liner over a silicon oxide liner in an opening, etching to remove the silicon oxide liner and silicon nitride liner on a lower surface of the opening, undercutting the silicon nitride liner adjacent to the lower surface, and epitaxially growing silicon in the opening. The silicon is substantially reduced of stacking faults because of the negative slope created by the undercut.
摘要翻译：公开了用于提供用于混合表面取向结构的堆垛层错缺陷外延生长的硅的方法。在一个实施例中，一种方法包括在开口中的氧化硅衬垫上沉积氮化硅衬垫，蚀刻以除去开口的下表面上的氧化硅衬垫和氮化硅衬垫，将邻近下表面的氮化硅衬垫并且在开口中外延生长硅。由于底切产生的负斜率，硅片堆积层错误大大减少。

13. 发明申请

US20070269963A1 STRAINED HOT (HYBRID ORIENTATION TECHNOLOGY) MOSFETs 有权
标题翻译：应变热（混合方向技术）MOSFET
公开(公告)号：US20070269963A1
公开(公告)日：2007-11-22
申请号：US11419312
申请日：2006-05-19
申请人： Kangguo Cheng , Woo-Hyeong Lee , Huilong Zhu
发明人： Kangguo Cheng , Woo-Hyeong Lee , Huilong Zhu
IPC分类号： H01L21/20
CPC分类号： H01L21/823878 , H01L21/187 , H01L21/2007 , H01L21/823807 , H01L21/84 , H01L29/045 , H01L29/1054 , H01L29/78
摘要： A strained HOT MOSFET fabrication method. The MOSFET fabrication method includes providing a semiconductor structure which includes (a) a first semiconductor layer having a first crystallographic orientation, (b) a buried insulating layer on top of the first semiconductor layer, (c) a second semiconductor layer on top of the buried oxide layer. The second semiconductor layer has a second crystallographic orientation different from the first crystallographic orientation. The method further includes forming a third semiconductor layer on top of the first semiconductor layer which has the first crystallographic orientation. The method further includes forming a fourth semiconductor layer on top of the third semiconductor layer. The fourth semiconductor layer (a) comprises a different material than that of the third semiconductor layer, and (b) has the first crystallographic orientation.
摘要翻译：应变HOT MOSFET制造方法。 MOSFET制造方法包括提供半导体结构，其包括：（a）具有第一晶体取向的第一半导体层，（b）在第一半导体层的顶部上的掩埋绝缘层，（c）第二半导体层，掩埋氧化层。第二半导体层具有不同于第一晶体取向的第二晶体取向。该方法还包括在具有第一晶体取向的第一半导体层的顶部上形成第三半导体层。该方法还包括在第三半导体层的顶部上形成第四半导体层。第四半导体层（a）包括与第三半导体层不同的材料，（b）具有第一晶体取向。

14. 发明授权

US07893493B2 Stacking fault reduction in epitaxially grown silicon 有权
标题翻译：堆积外延生长硅中的断层减少
公开(公告)号：US07893493B2
公开(公告)日：2011-02-22
申请号：US11456326
申请日：2006-07-10
申请人： Yun-Yu Wang , Linda Black , Judson R. Holt , Woo-Hyeong Lee , Scott Luning , Christopher D. Sheraw
发明人： Yun-Yu Wang , Linda Black , Judson R. Holt , Woo-Hyeong Lee , Scott Luning , Christopher D. Sheraw
IPC分类号： H01L27/12 , H01L21/302 , H01L21/461
CPC分类号： H01L21/02639 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02609 , H01L21/84
摘要： An intermediate hybrid surface orientation structure may include a silicon-on-insulator (SOI) substrate adhered to a bulk silicon substrate, the silicon of the SOI substrate having a different surface orientation than that of the bulk silicon substrate, and a reachthrough region extending through the SOI substrate to the bulk silicon substrate, the reachthrough region including a silicon nitride liner over a silicon oxide liner and a silicon epitaxially grown from the bulk silicon substrate, the epitaxially grown silicon extending into an undercut into the silicon oxide liner under the silicon nitride liner, wherein the epitaxially grown silicon is substantially stacking fault free.
摘要翻译：中间混合表面取向结构可以包括粘附到体硅衬底上的绝缘体上硅（SOI）衬底，SOI衬底的硅具有与体硅衬底不同的表面取向，并且穿透区域延伸穿过 SOI衬底到体硅衬底，穿透区域包括在氧化硅衬底上的氮化硅衬垫和从体硅衬底外延生长的硅，外延生长的硅延伸到底切到氮化硅之下的氧化硅衬底中衬垫，其中外延生长的硅基本上是无层错的。

15. 发明授权

US07674720B2 Stacking fault reduction in epitaxially grown silicon 失效
标题翻译：堆积外延生长硅中的断层减少
公开(公告)号：US07674720B2
公开(公告)日：2010-03-09
申请号：US12131214
申请日：2008-06-02
申请人： Yun-Yu Wang , Linda Black , Judson R. Holt , Woo-Hyeong Lee , Scott Luning , Christopher D. Sheraw
发明人： Yun-Yu Wang , Linda Black , Judson R. Holt , Woo-Hyeong Lee , Scott Luning , Christopher D. Sheraw
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/02639 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02609 , H01L21/84
摘要： Methods are disclosed for providing stacking fault reduced epitaxially grown silicon for use in hybrid surface orientation structures. In one embodiment, a method includes depositing a silicon nitride liner over a silicon oxide liner in an opening, etching to remove the silicon oxide liner and silicon nitride liner on a lower surface of the opening, undercutting the silicon nitride liner adjacent to the lower surface, and epitaxially growing silicon in the opening. The silicon is substantially reduced of stacking faults because of the negative slope created by the undercut.
摘要翻译：公开了用于提供用于混合表面取向结构的堆叠故障减少的外延生长的硅的方法。在一个实施例中，一种方法包括在开口中的氧化硅衬垫上沉积氮化硅衬垫，蚀刻以除去开口的下表面上的氧化硅衬垫和氮化硅衬垫，将邻近下表面的氮化硅衬垫并且在开口中外延生长硅。由于底切产生的负斜率，硅片堆积层错误大大减少。

16. 发明授权

US07514370B2 Compressive nitride film and method of manufacturing thereof 有权
标题翻译：压缩性氮化物膜及其制造方法
公开(公告)号：US07514370B2
公开(公告)日：2009-04-07
申请号：US11419217
申请日：2006-05-19
申请人： Daewon Yang , Woo-Hyeong Lee , Tai-chi Su , Yun-Yu Wang
发明人： Daewon Yang , Woo-Hyeong Lee , Tai-chi Su , Yun-Yu Wang
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/02274 , C23C16/345 , C23C16/505 , H01L21/0217 , H01L21/3185 , H01L21/76829 , H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cm2 and 5.0 W/cm2; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.
摘要翻译：本发明的实施例提供一种通过高密度等离子体沉积工艺形成在衬底上产生的多个p型场效应晶体管栅极结构的压应力氮化物膜的形成方法。实施例包括使用至少硅烷，氩和氮的源气体产生填充有高密度等离子体的环境; 在0.8W / cm 2至5.0W / cm 2之间的范围内将衬底偏置为变化密度的高频功率; 以及将所述高密度等离子体沉积到所述多个栅极结构以形成所述压应力氮化物膜。

17. 发明申请

US20080185592A1 SEMICONDUCTOR SUBSTRATE WITH MULTIPLE CRYSTALLOGRAPHIC ORIENTATIONS 有权
标题翻译：具有多个晶体取向的半导体衬底
公开(公告)号：US20080185592A1
公开(公告)日：2008-08-07
申请号：US11306713
申请日：2006-01-09
申请人： Byeong Y. Kim , Xiaomeng Chen , Woo-Hyeong Lee , Huilong Zhu
发明人： Byeong Y. Kim , Xiaomeng Chen , Woo-Hyeong Lee , Huilong Zhu
IPC分类号： H01L29/04 , H01L21/20
CPC分类号： H01L29/1083 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L29/045 , H01L29/0649 , H01L29/78 , H01L29/7848 , H01L29/7849 , H01L29/78603 , H01L29/78654 , H01L29/78687
摘要： A pair of semiconductor structures and a method for fabricating a semiconductor structure each utilize a semiconductor substrate having a first crystallographic orientation, and a dielectric layer located thereupon. The method provides for epitaxially growing a semiconductor layer on the semiconductor substrate to encapsulate the dielectric layer. The method also provides for patterning the semiconductor layer to yield a semiconductor structure that comprises a bulk semiconductor structure and a semiconductor-on-insulator structure, or alternatively a patterned semiconductor layer that straddles the dielectric layer and contacts the semiconductor substrate.
摘要翻译：一对半导体结构和半导体结构的制造方法各自使用具有第一晶体取向的半导体衬底和位于其上的电介质层。该方法提供了在半导体衬底上外延生长半导体层以封装介电层。该方法还提供了图案化半导体层以产生包括体半导体结构和绝缘体上半导体结构的半导体结构，或者替代地跨越电介质层并接触半导体衬底的图案化半导体层。

18. 发明授权

US07232774B2 Polycrystalline silicon layer with nano-grain structure and method of manufacture 失效
标题翻译：具有纳米晶粒结构的多晶硅层及其制造方法
公开(公告)号：US07232774B2
公开(公告)日：2007-06-19
申请号：US10707878
申请日：2004-01-20
申请人： Ashima B. Chakravarti , Bruce B. Doris , Romany Ghali , Oleg G. Gluschenkov , Michael A. Gribelyuk , Woo-Hyeong Lee , Anita Madan
发明人： Ashima B. Chakravarti , Bruce B. Doris , Romany Ghali , Oleg G. Gluschenkov , Michael A. Gribelyuk , Woo-Hyeong Lee , Anita Madan
IPC分类号： H01L21/00
CPC分类号： C23C16/24 , C23C16/46 , H01L21/28035 , H01L21/32055 , H01L29/4925
摘要： A method of forming polycrystalline silicon with ultra-small grain sizes employs a differential heating of the upper and lower sides of the substrate of a CVD apparatus, in which the lower side of the substrate receives considerably more power than the upper side, preferable more than 75% of the power; and in which the substrate is maintained during deposition at a temperature more than 50° C. above the 550° C. crystallization temperature of silicon.
摘要翻译：形成超小晶粒尺寸的多晶硅的方法采用CVD装置的衬底的上侧和下侧的差分加热，其中衬底的下侧比上侧受到明显更多的功率，优选大于 75％的权力; 并且其中在超过550℃的硅结晶温度超过50℃的温度下在沉积期间保持基底。

19. 发明授权

US07851376B2 Compressive nitride film and method of manufacturing thereof 有权
标题翻译：压缩性氮化物膜及其制造方法
公开(公告)号：US07851376B2
公开(公告)日：2010-12-14
申请号：US12364088
申请日：2009-02-02
申请人： Daewon Yang , Woo-Hyeong Lee , Tai-chi Su , Yun-Yu Wang
发明人： Daewon Yang , Woo-Hyeong Lee , Tai-chi Su , Yun-Yu Wang
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/02274 , C23C16/345 , C23C16/505 , H01L21/0217 , H01L21/3185 , H01L21/76829 , H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cm2 and 5.0 W/cm2; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.
摘要翻译：本发明的实施例提供一种通过高密度等离子体沉积工艺形成在衬底上产生的多个p型场效应晶体管栅极结构的压应力氮化物膜的形成方法。实施例包括使用至少硅烷，氩和氮的源气体产生填充有高密度等离子体的环境; 在0.8W / cm 2至5.0W / cm 2之间的范围内将衬底偏置为变化密度的高频功率; 以及将所述高密度等离子体沉积到所述多个栅极结构以形成所述压应力氮化物膜。

20. 发明申请

US20090137109A1 COMPRESSIVE NITRIDE FILM AND METHOD OF MANUFACTURING THEREOF 有权
标题翻译：压电式薄膜及其制造方法
公开(公告)号：US20090137109A1
公开(公告)日：2009-05-28
申请号：US12364088
申请日：2009-02-02
申请人： Daewon Yang , Woo-Hyeong Lee , Tai-chi Su , Yun-Yu Wang
发明人： Daewon Yang , Woo-Hyeong Lee , Tai-chi Su , Yun-Yu Wang
IPC分类号： H01L21/71
CPC分类号： H01L21/02274 , C23C16/345 , C23C16/505 , H01L21/0217 , H01L21/3185 , H01L21/76829 , H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cm2 and 5.0 W/cm2; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.
摘要翻译：本发明的实施例提供一种通过高密度等离子体沉积工艺形成在衬底上产生的多个p型场效应晶体管栅极结构的压应力氮化物膜的形成方法。实施例包括使用至少硅烷，氩和氮的源气体产生填充有高密度等离子体的环境; 在0.8W / cm 2至5.0W / cm 2之间的范围内将衬底偏置为变化密度的高频功率; 以及将所述高密度等离子体沉积到所述多个栅极结构以形成所述压应力氮化物膜。

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