专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07169711B1 Method of using carbon spacers for critical dimension (CD) reduction 失效
标题翻译：使用碳间隔物进行临界尺寸（CD）还原的方法
公开(公告)号：US07169711B1
公开(公告)日：2007-01-30
申请号：US10170984
申请日：2002-06-13
申请人： Christopher F. Lyons , Philip A. Fisher , Richard J. Huang , Cyrus E. Tabery
发明人： Christopher F. Lyons , Philip A. Fisher , Richard J. Huang , Cyrus E. Tabery
IPC分类号： H01L21/302
CPC分类号： H01L21/3086 , H01L21/0337
摘要： A method of using carbon spacers for critical dimension reduction can include providing a patterned photoresist layer above a substrate where the patterned photoresist layer has an aperture with a first width, depositing a carbon film over the photoresist layer and etching the deposited carbon film to form spacers on lateral side walls of the aperture of the patterned photoresist layer, etching the substrate using the formed spacers and patterned photoresist layer as a pattern to form a trench having a second width, and removing the patterned photoresist layer and formed spacers using an oxidizing etch.
摘要翻译：使用碳间隔物进行临界尺寸减小的方法可以包括在基底上提供图案化的光致抗蚀剂层，其中图案化的光致抗蚀剂层具有第一宽度的孔，在光致抗蚀剂层上沉积碳膜并蚀刻沉积的碳膜以形成间隔物在图案化光致抗蚀剂层的孔的侧壁上，使用所形成的间隔物和图案化的光致抗蚀剂层作为图案蚀刻衬底，以形成具有第二宽度的沟槽，并使用氧化蚀刻去除图案化的光致抗蚀剂层和形成的间隔物。

12. 发明授权

US07141502B1 Slurry-less polishing for removal of excess interconnect material during fabrication of a silicon integrated circuit 有权
标题翻译：在硅集成电路的制造期间，用于去除多余互连材料的无浆抛光
公开(公告)号：US07141502B1
公开(公告)日：2006-11-28
申请号：US10673597
申请日：2003-09-29
申请人： James J. Xie , Kashmir S. Sahota , Richard J. Huang
发明人： James J. Xie , Kashmir S. Sahota , Richard J. Huang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/7684 , B24B37/042 , H01L21/3212
摘要： A method for Chemical-Mechanical Polishing utilizes a two step process. The first step utilizes a slurry with abrasive particles which become embedded into a conditioned polishing pad having small cavities in the surface. During the second step the slurry flow is discontinued and the final polishing is performed using the embedded small abrasive particles. Using this method dishing has been reduced considerably, and has enabled the fabrication of a Damascene metal gate NMOSFET fabricated with Atomic Layer Deposition (ALD).
摘要翻译：化学机械抛光方法采用两步法。第一步使用具有磨料颗粒的浆料，该磨料颗粒嵌入到表面上具有小空腔的调理抛光垫中。在第二步骤期间，浆料流动停止，并且使用嵌入的小磨料颗粒进行最终抛光。使用该方法，凹陷已经显着减少，并且已经能够制造用原子层沉积（ALD）制造的镶嵌金属栅极NMOSFET。

13. 发明授权

US06673684B1 Use of diamond as a hard mask material 有权
标题翻译：使用金刚石作为硬面罩材料
公开(公告)号：US06673684B1
公开(公告)日：2004-01-06
申请号：US10335726
申请日：2003-01-02
申请人： Richard J. Huang , Philip A. Fisher , Cyrus E. Tabery
发明人： Richard J. Huang , Philip A. Fisher , Cyrus E. Tabery
IPC分类号： H01L21336
CPC分类号： H01L21/32139
摘要： A method for producing an integrated circuit includes providing a diamond layer above a layer of conductive material. A cap layer is provided above the diamond layer and patterned to form a cap feature. The diamond layer is patterned according to the cap feature to form a mask, and at least a portion of the layer of conductive material is removed according to the mask.
摘要翻译：一种用于制造集成电路的方法包括在导电材料层之上提供金刚石层。盖层设置在金刚石层之上并图案化以形成盖特征。根据盖特征对金刚石层进行图案化以形成掩模，并且根据掩模去除导电材料层的至少一部分。

14. 发明授权

US06653202B1 Method of shallow trench isolation (STI) formation using amorphous carbon 有权
标题翻译：使用无定形碳的浅沟槽隔离（STI）形成方法
公开(公告)号：US06653202B1
公开(公告)日：2003-11-25
申请号：US10347064
申请日：2003-01-17
申请人： Philip A. Fisher , Richard J. Huang
发明人： Philip A. Fisher , Richard J. Huang
IPC分类号： H01L21762
CPC分类号： H01L21/31053 , H01L21/3081 , H01L21/76232
摘要： An exemplary embodiment relates to a method of shallow trench isolation (STI) formation using amorphous carbon as a sacrificial polish stop layer. The method can include polishing a silicon dioxide layer located above a wafer, polishing portions of the silicon dioxide layer located in a field area and portions of an amorphous carbon layer located in an active area. Portions of the amorphous carbon layer are polished down to a hard polish stop layer. The method can also include ashing away residual amorphous carbon from the amorphous carbon layer.
摘要翻译：示例性实施例涉及使用无定形碳作为牺牲抛光停止层的浅沟槽隔离（STI）形成方法。该方法可以包括抛光位于晶片上方的二氧化硅层，抛光位于场区域中的二氧化硅层的部分和位于有源区域中的无定形碳层的部分。无定形碳层的一部分被抛光到硬抛光停止层。该方法还可以包括从无定形碳层中去除残留的无定形碳。

15. 发明授权

US06596631B1 Method of forming copper interconnect capping layers with improved interface and adhesion 有权
标题翻译：形成具有改善界面和粘合性的铜互连封盖层的方法
公开(公告)号：US06596631B1
公开(公告)日：2003-07-22
申请号：US09626455
申请日：2000-07-26
申请人： Minh Van Ngo , Hartmut Ruelke , Lothar Mergili , Joerg Hohage , Lu You , Robert A. Huertas , Richard J. Huang
发明人： Minh Van Ngo , Hartmut Ruelke , Lothar Mergili , Joerg Hohage , Lu You , Robert A. Huertas , Richard J. Huang
IPC分类号： H01L244
CPC分类号： H01L21/76883 , H01L21/76834 , Y10S438/913
摘要： The integrity of the interface and adhesion between a barrier or capping layer and a Cu or Cu alloy interconnect member is significantly enhanced by delaying and/or slowly ramping up the introduction of silane to deposit a silicon nitride capping layer after treating the exposed planarized surface of the Cu or Cu alloy with an ammonia-containing plasma. Other embodiments include purging the reaction chamber with nitrogen at elevated temperature to remove residual gases prior to introducing the wafer for plasma treatment.
摘要翻译：通过在处理暴露的平坦化表面之后延迟和/或缓慢地升高硅烷的引入以沉积氮化硅覆盖层来显着增强界面的完整性和阻挡层或覆盖层与Cu或Cu合金互连构件之间的粘合性具有含氨等离子体的Cu或Cu合金。其他实施方案包括在升高的温度下用氮气吹扫反应室以在引入用于等离子体处理的晶片之前去除残留气体。

16. 发明授权

US06329718B1 Method for reducing stress-induced voids for 0.25m&mgr; and smaller semiconductor chip technology by annealing interconnect lines and using low bias voltage and low interlayer dielectric deposition rate and semiconductor chip made thereby 失效
标题翻译：通过退火互连线和使用低偏压和低层间电介质沉积速率减少应力诱发的0.25μm及更小的半导体芯片技术的空穴的方法，由此制成半导体芯片
公开(公告)号：US06329718B1
公开(公告)日：2001-12-11
申请号：US09105775
申请日：1998-06-26
申请人： Minh Van Ngo , Paul R. Besser , Matthew Buynoski , John Caffall , Nick MacCrae , Richard J. Huang , Khanh Tran
发明人： Minh Van Ngo , Paul R. Besser , Matthew Buynoski , John Caffall , Nick MacCrae , Richard J. Huang , Khanh Tran
IPC分类号： H01L2348
CPC分类号： H01L21/7685 , H01L21/76837 , H01L21/76858 , H01L21/76885 , H01L23/53223 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A method for making 0.25 micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature, and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.
摘要翻译：用于制造0.25微米半导体芯片的方法包括在线之间沉积层间电介质（ILD）之前退火金属互连线。在退火期间，形成铝和钛的合金，其随后容积收缩，收缩被铝吸收。因为合金在ILD沉积之前反应，所以当铝试图吸收合金的收缩时，铝不受ILD的约束。因此，互连线中不希望的空隙形成的可能性降低。在随后的ILD间隙填充沉积过程中，通过使用相对低的偏置功率来降低气相沉积温度，并且通过使用相对较低的源气体沉积流速来减少互连线上的流动引起的压缩应力，仍然进一步降低了不希望的空隙形成的可能性在ILD形成期间。

17. 发明授权

US06291329B1 Protective oxide buffer layer for ARC removal 有权
标题翻译：用于ARC去除的保护性氧化物缓冲层
公开(公告)号：US06291329B1
公开(公告)日：2001-09-18
申请号：US09371921
申请日：1999-08-11
申请人： Richard J. Huang , Lewis Shen
发明人： Richard J. Huang , Lewis Shen
IPC分类号： H01L213205
CPC分类号： H01L21/32139 , H01L21/3145 , H01L21/3185
摘要： An oxide buffer layer is formed between an underlying silicon layer and overlying ARC to prevent damage to the silicon layer when removing the ARC. Embodiments include depositing a silicon oxide buffer layer on an amorphous or polycrystalline silicon layer by PCVD, LPCVD or high temperature CVD, forming a SiON or Si-rich SiN ARC on the silicon oxide buffer layer, forming a photoresist mask on the ARC, patterning the underlying silicon layer to form a conductive line or gate electrode, stripping the photoresist mask and then stripping the ARC with hot phosphoric acid while the silicon oxide buffer layer protects the underlying silicon feature from pitting.
摘要翻译：在下面的硅层和上覆的ARC之间形成氧化物缓冲层，以防止在去除ARC时损坏硅层。实施例包括通过PCVD，LPCVD或高温CVD在非晶或多晶硅层上沉积硅氧化物缓冲层，在氧化硅缓冲层上形成SiON或富Si SiN SiN ARC，在ARC上形成光刻胶掩模，底层硅层以形成导电线或栅电极，剥离光致抗蚀剂掩模，然后用热磷酸剥离ARC，而氧化硅缓冲层保护下面的硅特征免于点蚀。

18. 发明授权

US06252303B1 Intergration of low-K SiOF as inter-layer dielectric 有权
标题翻译：低K SiOF作为层间电介质的集成
公开(公告)号：US06252303B1
公开(公告)日：2001-06-26
申请号：US09203572
申请日：1998-12-02
申请人： Richard J. Huang
发明人： Richard J. Huang
IPC分类号： H01L2352
CPC分类号： H01L21/76807 , H01L21/02131 , H01L21/02274 , H01L21/02332 , H01L21/0234 , H01L21/02362 , H01L21/31629 , H01L21/76801 , H01L21/76814 , H01L21/76826 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L21/76837 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device formed on a substrate includes at least one metal stack formed on the substrate. A fluorosilicate glass layer is formed on the at least one metal stack, where the fluorosilicate glass layer acts as an interlayer dielectric for the semiconductor device. The fluorosilicate glass layer includes a fluorine-depleted layer at a top portion of the fluorosilicate glass layer that is further away from the substrate. The fluorine-depleted layer is formed by treating the fluorosilicate glass layer with a hydrogen plasma, such as an H2/N2 plasma. The fluorine-depleted layer lessens a likelihood of fluorine atoms in the fluorosilicate glass layer from moving into and thereby corrupting a conducting layer formed above the fluorosilicate glass layer.
摘要翻译：形成在基板上的半导体器件包括形成在基板上的至少一个金属堆叠。在至少一个金属叠层上形成氟硅酸盐玻璃层，其中氟硅酸盐玻璃层用作半导体器件的层间电介质。氟硅酸盐玻璃层包括位于氟硅酸盐玻璃层的远离衬底的顶部的氟耗尽层。通过用诸如H 2 / N 2等离子体的氢等离子体处理氟硅酸盐玻璃层来形成氟耗层。氟耗层降低了氟硅酸盐玻璃层中的氟原子的迁移，从而腐蚀在氟硅酸盐玻璃层上形成的导电层的可能性。

19. 发明授权

US06200913B1 Cure process for manufacture of low dielectric constant interlevel dielectric layers 有权
标题翻译：用于制造低介电常数层间电介质层的固化工艺
公开(公告)号：US06200913B1
公开(公告)日：2001-03-13
申请号：US09191040
申请日：1998-11-12
申请人： Lu You , Simon S. Chan , John Iacoponi , Richard J. Huang , Robin Cheung
发明人： Lu You , Simon S. Chan , John Iacoponi , Richard J. Huang , Robin Cheung
IPC分类号： H01L21324
CPC分类号： H01L21/02134 , H01L21/02282 , H01L21/31058 , H01L21/3124
摘要： This invention comprises improvements in the ways in which spin-on dielectric layers are cured. A semiconductor wafer is coated with a precursor for a spin-on dielectric material, and after the solution is thinned and evened, the wafer is placed in a curing oven, optionally containing an inert gas, and pre-heated to a temperature below which excessive thermomechanical stresses and/or oxidation are not created in the semiconductor wafer. The temperature within the curing oven is then raised to a curing temperature, and thereafter the temperature is slowly lowered to prevent the formation of stress cracks and the loss of dielectric function of the thin film. The curing method of this invention is useful for the manufacture of semiconductor devices employing a variety of spin-on materials.
摘要翻译：本发明包括改进旋涂电介质层固化的方式。半导体晶片被涂覆有用于旋涂电介质材料的前体，并且在溶液变薄并均匀之后，将晶片放置在固化炉中，任选地包含惰性气体，并预热到低于该温度的温度在半导体晶片中不产生热机械应力和/或氧化。然后将固化炉内的温度升高至固化温度，然后缓慢降低温度，以防止形成应力裂纹和薄膜的介电功能的损失。本发明的固化方法可用于制造采用各种旋涂材料的半导体器件。

20. 发明授权

US6166427A Integration of low-K SiOF as inter-layer dielectric for AL-gapfill application 有权
标题翻译：将低K SiOF作为层间电介质的集成应用于AL间隙填充
公开(公告)号：US6166427A
公开(公告)日：2000-12-26
申请号：US231649
申请日：1998-01-15
申请人： Richard J. Huang , John A. Iacoponi
发明人： Richard J. Huang , John A. Iacoponi
IPC分类号： C23C16/40 , H01L21/316 , H01L21/768 , H01L23/532 , H01L23/58 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02131 , C23C16/401 , H01L21/02274 , H01L21/02332 , H01L21/02362 , H01L21/31629 , H01L21/76801 , H01L21/76814 , H01L21/76826 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L21/76835 , H01L21/76837 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for producing a dielectric layer in a semiconductor product includes two steps. The first step is forming a fluorinated layer (e.g. SiOF or fluorosilicate glass ("FSG")) which includes a material formed in part with fluorine. The second step is forming a fill layer (e.g. SiO.sub.2) above the fluorinated layer. The fill layer is substantially free of materials formed in part with fluorine. A top surface of the fill layer can be planarized. Surface treatments and oxide caps can be applied to the planarized surface to form fluorine barriers if part of the fluorinated layer is exposed to higher layers. Such a method, and a semiconductor device or integrated circuit manufactured according to the method, allow the dielectric constant of an inter-layer dielectric ("ILD") to be lowered while also minimizing the complexity and expense of the manufacturing process.
摘要翻译：半导体产品中的介电层的制造方法包括两个步骤。第一步是形成氟化层（例如SiOF或氟硅酸盐玻璃（“FSG”），其包括部分由氟形成的材料。第二步是在氟化层之上形成填充层（例如SiO 2）。填充层基本上不含部分由氟形成的材料。填充层的顶表面可以被平坦化。如果氟化层的一部分暴露于较高层，则表面处理和氧化物盖可以施加到平坦化表面以形成氟阻挡层。这样的方法以及根据该方法制造的半导体器件或集成电路能够降低层间电介质（“ILD”）的介电常数，同时也使制造工艺的复杂性和费用最小化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式