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11. 发明授权

US07746683B2 NOR and NAND memory arrangement of resistive memory elements 有权
标题翻译： NOR和NAND存储器布置的电阻存储器元件
公开(公告)号：US07746683B2
公开(公告)日：2010-06-29
申请号：US11737236
申请日：2007-04-19
申请人： Kurt Hoffmann , Christine Dehm , Recai Sezi , Andreas Walter
发明人： Kurt Hoffmann , Christine Dehm , Recai Sezi , Andreas Walter
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , B82Y10/00 , G11C13/0004 , G11C13/0014 , G11C13/0016 , G11C13/0019 , G11C2213/15 , G11C2213/75 , G11C2213/79
摘要： A memory arrangement includes: a first line for applying a reference voltage, a second line for applying an operating voltage, and a plurality of resistive memory elements, each element includes a resistive memory cell and a MOS memory cell selection transistor. A NOR memory arrangement is configured with each memory element including the resistive memory cell and selection transistor connected in series with the transistor connected to the first line, and the memory cell connected to the second line. A NAND memory arrangement is configured with a series of resistive memory elements forming a chain with each memory element including the resistive memory cell and selection transistor connected in parallel. The chain is connected to the first line disposed on a side of the memory cells facing the selection transistors and the second line disposed on a side of the memory cells which is remote from the selection transistors.
摘要翻译：存储器装置包括：用于施加参考电压的第一线，用于施加工作电压的第二线和多个电阻性存储器元件，每个元件包括电阻存储器单元和MOS存储单元选择晶体管。 NOR存储器配置配置有每个存储器元件，其包括与连接到第一线路的晶体管串联连接的电阻存储器单元和选择晶体管，以及连接到第二线路的存储器单元。 NAND存储器配置配置有一系列形成链的电阻存储元件，每个存储元件包括并联连接的电阻存储单元和选择晶体管。链条连接到布置在面向选择晶体管的存储单元的一侧上的第一行，而第二行设置在远离选择晶体管的存储单元的一侧。

12. 发明授权

US06844581B2 Storage capacitor and associated contact-making structure and a method for fabricating the storage capacitor and the contact-making structure 有权
标题翻译：存储电容器和相关联的接触结构以及用于制造存储电容器和接触构造结构的方法
公开(公告)号：US06844581B2
公开(公告)日：2005-01-18
申请号：US10012168
申请日：2001-10-26
申请人： Arkalgud Sitaram , Christine Dehm , Carlos Mazuré-Espejo
发明人： Arkalgud Sitaram , Christine Dehm , Carlos Mazuré-Espejo
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L21/8246 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/7687 , H01L27/10855 , H01L27/11507 , H01L28/55 , H01L28/75
摘要： A storage capacitor, in particular a ferroelectric or paraelectric storage capacitor, and an associated contact-making structure are formed in such a way that the storage capacitor has a first electrode layer, a second electrode layer and a dielectric, ferroelectric or paraelectric capacitor intermediate layer. Proceeding from the plane of the surface of the insulation layer, the storage capacitor extends at least partly into the interior of the via contact and is electrically connected to the via contact.
摘要翻译：存储电容器，特别是铁电或顺电存储电容器以及相关联的接触构造结构形成为使得存储电容器具有第一电极层，第二电极层和电介质，铁电或对中电容器中间层。从绝缘层表面的平面开始，存储电容器至少部分地延伸到通孔接触件的内部并与通孔接触件电连接。

13. 发明授权

US06664158B2 Ferroelectric memory configuration and a method for producing the configuration 有权
公开(公告)号：US06664158B2
公开(公告)日：2003-12-16
申请号：US10034931
申请日：2001-11-21
申请人： Christine Dehm , Heinz Hönigschmid , Thomas Röhr
发明人： Christine Dehm , Heinz Hönigschmid , Thomas Röhr
IPC分类号： H01L218242
CPC分类号： H01L27/11502 , H01L27/11507
摘要： An integrated ferroelectric memory configuration and a method for producing the integrated ferroelectric memory configuration, in which memory cells are arranged using the stacking principle, and both capacitor electrodes, which are located one above the other, of each memory cell are directly electrically connected by means of contact plugs to corresponding source and drain regions of an associated selection transistor in the substrate. Contact plugs for the contact connection to the upper capacitor electrodes are produced from above the configuration.

14. 发明授权

US06337239B1 Layer configuration with a material layer and a diffusion barrier which blocks diffusing material components and process for producing a diffusion barrier 有权
标题翻译：具有阻挡扩散材料成分的材料层和扩散阻挡层的层结构和用于产生扩散阻挡层的工艺
公开(公告)号：US06337239B1
公开(公告)日：2002-01-08
申请号：US09391720
申请日：1999-09-08
申请人： Christine Dehm , Carlos Mazure-Espejo
发明人： Christine Dehm , Carlos Mazure-Espejo
IPC分类号： H01L218242
CPC分类号： H01L27/11502 , H01L21/28568 , H01L27/11507 , H01L28/55 , H01L28/75
摘要： A layer configuration includes a material layer and a diffusion barrier which blocks diffusing material components. The barrier is disposed in the vicinity of a layer boundary of the material layer and is formed predominantly in grain boundaries of the material layer. A process for producing a diffusion barrier is also provided.
摘要翻译：层构造包括阻挡扩散材料成分的材料层和扩散阻挡层。阻挡层设置在材料层的层边界附近并且主要形成在材料层的晶界中。还提供了制造扩散阻挡层的方法。

15. 发明授权

US06228701B1 Apparatus and method for minimizing diffusion in stacked capacitors formed on silicon plugs 失效
标题翻译：用于最小化在硅插头上形成的堆叠电容器中的扩散的装置和方法
公开(公告)号：US06228701B1
公开(公告)日：2001-05-08
申请号：US08994275
申请日：1997-12-19
申请人： Christine Dehm , Stephen K. Loh , Carlos Mazuré
发明人： Christine Dehm , Stephen K. Loh , Carlos Mazuré
IPC分类号： H01L218242
CPC分类号： H01L28/75 , H01L27/10855 , Y10S438/922
摘要： Methods and apparatus for fabricating stacked capacitor structures, which include barrier layers, are disclosed. According to one aspect of the present invention, a method for reducing outdiffusion within an integrated circuit includes forming a gate oxide layer over a substrate, and further forming a silicon plug over a portion of the gate oxide layer. A silicon dioxide layer is then formed over the gate oxide layer, and is arranged around the silicon plug. A first barrier film is formed over the silicon plug, and a dielectric layer is formed over the silicon dioxide layer. In one embodiment, forming the first barrier film includes forming a first oxide layer over the silicon plug, nitridizing the first oxide layer, and etching the nitridized first oxide layer.
摘要翻译：公开了用于制造包括阻挡层的叠层电容器结构的方法和装置。根据本发明的一个方面，一种用于减小集成电路内的扩散扩散的方法包括：在衬底上形成栅极氧化层，并进一步在栅极氧化物层的一部分上形成硅插头。然后在栅极氧化物层上形成二氧化硅层，并且布置在硅插头周围。在硅塞上形成第一阻挡膜，并且在二氧化硅层上形成电介质层。在一个实施例中，形成第一阻挡膜包括在硅插塞上形成第一氧化物层，对第一氧化物层进行氮化，以及蚀刻氮化的第一氧化物层。

16. 发明授权

US5998253A Method of forming a dopant outdiffusion control structure including selectively grown silicon nitride in a trench capacitor of a DRAM cell 失效
标题翻译：在DRAM单元的沟槽电容器中形成包括选择性地生长的氮化硅的掺杂剂扩散扩散控制结构的方法
公开(公告)号：US5998253A
公开(公告)日：1999-12-07
申请号：US993743
申请日：1997-12-19
申请人： Stephen K. Loh , Christine Dehm , Christopher C. Parks
发明人： Stephen K. Loh , Christine Dehm , Christopher C. Parks
IPC分类号： H01L29/78 , H01L21/28 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L29/49 , H01L21/70
CPC分类号： H01L21/8238 , H01L21/28061 , H01L29/4916 , H01L29/4933
摘要： A method for controlling dopant outdiffusion within an integrated circuit is disclosed. The method includes providing a substrate, forming a trench in the substrate, and forming a first doped layer in the trench. The first doped layer has a first dopant concentration. The method further includes forming a dopant diffusion control structure above the first doped layer. The dopant diffusion control structure includes silicon nitride (Si.sub.x N.sub.y) disposed in grain boundaries of the first doped layer. The method also includes forming a second layer above the dopant diffusion control structure. The second layer has a second dopant concentration lower than the first dopant concentration. Forming the dopant diffusion control structure includes, in one example, forming a first oxide layer over the first doped silicon layer, nitridizing the first oxide layer, thereby forming an oxynitride (SiO.sub.x N.sub.y) layer and causing the silicon nitride to migrate into the grain boundaries, and removing the oxynitride layer, thereby exposing the silicon nitride at the grain boundaries at an interface of the first doped layer.
摘要翻译：公开了一种用于控制集成电路内的掺杂物扩散扩散的方法。该方法包括提供衬底，在衬底中形成沟槽，以及在沟槽中形成第一掺杂层。第一掺杂层具有第一掺杂浓度。该方法还包括在第一掺杂层之上形成掺杂剂扩散控制结构。掺杂剂扩散控制结构包括设置在第一掺杂层的晶界中的氮化硅（SixNy）。该方法还包括在掺杂剂扩散控制结构上方形成第二层。第二层具有低于第一掺杂剂浓度的第二掺杂剂浓度。在一个示例中，形成掺杂剂扩散控制结构包括在第一掺杂硅层上形成第一氧化物层，对第一氧化物层进行氮化，从而形成氧氮化物（SiO x N y）层并使氮化硅迁移到晶界，并去除氧氮化物层，从而在第一掺杂层的界面处的晶界暴露氮化硅。

17. 发明申请

US20080099756A1 Semiconductor Memory with Organic Selection Transistor 审中-公开
标题翻译：半导体存储器与有机选择晶体管
公开(公告)号：US20080099756A1
公开(公告)日：2008-05-01
申请号：US11597446
申请日：2005-05-30
申请人： Hagen Klauk , Marcus Halik , Ute Zschieschang , Guenter Schmid , Christine Dehm
发明人： Hagen Klauk , Marcus Halik , Ute Zschieschang , Guenter Schmid , Christine Dehm
IPC分类号： H01L51/00
CPC分类号： G11C13/0014 , B82Y10/00 , G11C2213/79 , H01L27/283 , H01L51/0508 , H01L51/0512 , H01L51/0595
摘要： An integrated semiconductor memory with a cell array is disclosed. In one embodiment the memory includes a multiplicity of memory cells arranged in rows and columns. In at least one memory cell, an organic selection transistor is integrated in a stack arrangement above an organic storage element.
摘要翻译：公开了一种具有单元阵列的集成半导体存储器。在一个实施例中，存储器包括以行和列排列的多个存储单元。在至少一个存储单元中，有机选择晶体管集成在有机存储元件上方的堆叠布置中。

18. 发明申请

US20070242496A1 NOR and NAND Memory Arrangement of Resistive Memory Elements 有权
标题翻译： NOR和NAND内存排列的电阻式存储元件
公开(公告)号：US20070242496A1
公开(公告)日：2007-10-18
申请号：US11737236
申请日：2007-04-19
申请人： Kurt Hoffmann , Christine Dehm , Recai Sezi , Andreas Walter
发明人： Kurt Hoffmann , Christine Dehm , Recai Sezi , Andreas Walter
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , B82Y10/00 , G11C13/0004 , G11C13/0014 , G11C13/0016 , G11C13/0019 , G11C2213/15 , G11C2213/75 , G11C2213/79
摘要： A memory arrangement includes: a first line for applying a reference voltage, a second line for applying an operating voltage, and a plurality of resistive memory elements, each element includes a resistive memory cell and a MOS memory cell selection transistor. A NOR memory arrangement is configured with each memory element including the resistive memory cell and selection transistor connected in series with the transistor connected to the first line, and the memory cell connected to the second line. A NAND memory arrangement is configured with a series of resistive memory elements forming a chain with each memory element including the resistive memory cell and selection transistor connected in parallel. The chain is connected to the first line disposed on a side of the memory cells facing the selection transistors and the second line disposed on a side of the memory cells which is remote from the selection transistors.
摘要翻译：存储器装置包括：用于施加参考电压的第一线，用于施加工作电压的第二线和多个电阻性存储器元件，每个元件包括电阻存储器单元和MOS存储单元选择晶体管。 NOR存储器配置配置有每个存储器元件，其包括与连接到第一线路的晶体管串联连接的电阻存储器单元和选择晶体管，以及连接到第二线路的存储器单元。 NAND存储器配置配置有一系列形成链的电阻存储元件，每个存储元件包括并联连接的电阻存储单元和选择晶体管。链条连接到布置在面向选择晶体管的存储单元的一侧上的第一行，而第二行设置在远离选择晶体管的存储单元的一侧。

19. 发明授权

US07115897B2 Semiconductor circuit configuration and semiconductor memory device 失效
公开(公告)号：US07115897B2
公开(公告)日：2006-10-03
申请号：US10395455
申请日：2003-03-24
申请人： Günter Schmid , Marcus Halik , Hagen Klauk , Christine Dehm , Thomas Haneder , Thomas Mikolajick
发明人： Günter Schmid , Marcus Halik , Hagen Klauk , Christine Dehm , Thomas Haneder , Thomas Mikolajick
IPC分类号： H01L29/08 , H01L29/10 , H01L29/76
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0016 , H01L21/823807 , H01L27/0629 , H01L27/28 , H01L28/55
摘要： A semiconductor circuit configuration has at least one pair of complementary operating field-effect transistors in which each transistor has a gate region, first and second source/drain regions and also a channel region with or made of an organic semiconductor material that is provided in between. It is furthermore provided that the gate regions are formed such that they are electrically coupled to one another via a capacitor configuration.

20. 发明授权

US06958501B2 Contact-making structure for a ferroelectric storage capacitor and method for fabricating the structure 失效
标题翻译：用于铁电存储电容器的接触构造和用于制造该结构的方法
公开(公告)号：US06958501B2
公开(公告)日：2005-10-25
申请号：US10012164
申请日：2001-10-26
申请人： Arkalgud Sitaram , Christine Dehm , Carlos Mazuré-Espejo
发明人： Arkalgud Sitaram , Christine Dehm , Carlos Mazuré-Espejo
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8246 , H01L27/115 , H01L29/76
CPC分类号： H01L21/7687 , H01L21/76877 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/60
摘要： A continuous contact hole is formed in an insulation layer that separates a storage capacitor from a switching transistor. All except a section of the contact hole is filled with poly-Si. A conductive, oxidizable interlayer and a conductive oxygen barrier layer are deposited on the Poly-Si in the remaining section of the contact hole such that the interlayer is completely surrounded by the poly-Si of the contact hole, the insulation layer, and the barrier layer.
摘要翻译：在保持电容器与开关晶体管分离的绝缘层中形成连续的接触孔。除了接触孔的一部分之外，所有的都被多晶硅填充。在接触孔的剩余部分中的多晶硅上沉积导电可氧化中间层和导电氧阻挡层，使得中间层被接触孔，绝缘层和屏障的多晶硅完全包围层。

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