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11. 发明授权

US4630239A Chip select speed-up circuit for a memory 失效
标题翻译：一个存储器的片选加速电路
公开(公告)号：US4630239A
公开(公告)日：1986-12-16
申请号：US750638
申请日：1985-07-01
申请人： Paul A. Reed , Stephen T. Flannagan
发明人： Paul A. Reed , Stephen T. Flannagan
IPC分类号： G11C11/41 , G11C8/00 , G11C8/18 , G11C11/40
CPC分类号： G11C8/18
摘要： A memory circuit is provided which has a select and a deselect mode. The memory circuit, as part of its technique for quickly accessing data, includes circuitry for generating a pulse in response to detecting an address transition. When the memory circuit switches from the deselect mode to the select mode, these appears to be an address transition even when there is not an address transition. In order to prevent a delay associated with interpreting such false transition as an actual transition, the detection of address transitions is suppressed for a predetermined delay time following the transition from the select to deselect modes.
摘要翻译：提供了具有选择和取消选择模式的存储器电路。存储电路作为其用于快速访问数据的技术的一部分，包括响应于检测到地址转换而产生脉冲的电路。当存储器电路从取消选择模式切换到选择模式时，即使没有地址转换，这些也是地址转换。为了防止与解释与实际转变相关的这种虚假转变相关联的延迟，在从选择模式转换到取消选择模式之后，预定的延迟时间抑制了地址转换的检测。

12. 发明授权

US6044036A Buffer circuit, memory device, and integrated circuit for receiving digital signals 失效
标题翻译：缓冲电路，存储器件和用于接收数字信号的集成电路
公开(公告)号：US6044036A
公开(公告)日：2000-03-28
申请号：US78159
申请日：1998-05-13
申请人： Stephen T. Flannagan , William R. Weier
发明人： Stephen T. Flannagan , William R. Weier
IPC分类号： G11C7/10 , G11C8/06 , H03K17/041 , G11C8/00
CPC分类号： H03K17/04106 , G11C7/1051 , G11C7/1078 , G11C8/06
摘要： A buffer circuit (60) that includes a current source (74) having an output, the current source to provide a substantially constant current, a first differential amplifier (62), and a second differential amplifier (66). The current from current source 74 is shared by the first (62) and second (64) differential amplifiers.
摘要翻译：一种缓冲电路（60），包括具有输出的电流源（74），用于提供基本恒定电流的电流源，第一差分放大器（62）和第二差分放大器（66）。来自电流源74的电流由第一（62）和第二（64）差分放大器共用。

13. 发明授权

US5426381A Latching ECL to CMOS input buffer circuit 失效
标题翻译：将ECL锁存到CMOS输入缓冲电路
公开(公告)号：US5426381A
公开(公告)日：1995-06-20
申请号：US247819
申请日：1994-05-23
申请人： Stephen T. Flannagan , Lawrence F. Childs
发明人： Stephen T. Flannagan , Lawrence F. Childs
IPC分类号： H03K3/356 , H03K19/01
CPC分类号： H03K3/35606 , H03K3/356034 , H03K3/356113
摘要： A latching ECL to CMOS input buffer (20) has an input buffer (21) for receiving an ECL input signal, a CMOS latch (35), and driver circuits (55, 65). Transmission gates (31, 32) are used to couple the input buffer (21) to the latch (35) in response to a CMOS clock signal being a logic low. The driver circuits (55, 65) are coupled to transmission gates (31, 32). While the clock signal is a logic low, input nodes of the first and second driver circuits (55, 65) are precharged to a relatively high voltage in order to isolate the input signal from the first and second driver circuits (55, 65). The latch (35) both latches the logic state of the ECL input signal and converts the ECL input signal to CMOS logic levels. This allows an input signal to be latched and level converted within a relatively short period of time.
摘要翻译： CMOS输入缓冲器（20）的锁存ECL具有用于接收ECL输入信号的输入缓冲器（21），CMOS锁存器（35）和驱动器电路（55,65）。响应于CMOS时钟信号为逻辑低，传输门（31,32）用于将输入缓冲器（21）耦合到锁存器（35）。驱动电路（55,65）耦合到传输门（31,32）。当时钟信号为逻辑低电平时，第一和第二驱动电路（55,65）的输入节点被预充电到较高的电压，以隔离来自第一和第二驱动电路（55,65）的输入信号。锁存器（35）都锁存ECL输入信号的逻辑状态，并将ECL输入信号转换为CMOS逻辑电平。这允许输入信号在相对短的时间段内被锁存和电平转换。

14. 发明授权

US4807198A Memory input buffer with hysteresis and dc margin 失效
标题翻译：具有滞后和直流裕度的存储器输入缓冲器
公开(公告)号：US4807198A
公开(公告)日：1989-02-21
申请号：US138103
申请日：1987-12-28
申请人： Stephen T. Flannagan , Peter H. Voss
发明人： Stephen T. Flannagan , Peter H. Voss
IPC分类号： G11C8/06 , G11C11/40 , G11C13/00
CPC分类号： G11C8/06
摘要： A memory has input buffer circuit which provides high immunity to problems associated with address float while providing high speed for both decoder selection and for transition detection. The input buffer circuit includes a pair of input NOR gates which provides for independent signal paths to a cross-coupled latch. Independent hysteresis circuits are provided to each signal path between the two NOR gates and the cross-coupled latch. This allows for independently selecting the amount of dc margin and hysteresis so that the use of hysteresis does not adversely effect dc margin.
摘要翻译：存储器具有输入缓冲电路，其对与地址浮动相关的问题提供高抗扰性，同时为解码器选择和转换检测提供高速度。输入缓冲器电路包括一对输入NOR门，其提供到交叉耦合锁存器的独立信号路径。独立的滞后电路被提供给两个或非门和交叉耦合的锁存器之间的每个信号路径。这允许独立地选择直流余量和滞后量，使得滞后的使用不会不利地影响直流裕度。

15. 发明授权

US4763303A Write-drive data controller 失效
标题翻译：写驱动数据控制器
公开(公告)号：US4763303A
公开(公告)日：1988-08-09
申请号：US832607
申请日：1986-02-24
申请人： Stephen T. Flannagan
发明人： Stephen T. Flannagan
IPC分类号： G11C7/10 , G11C7/00 , G11C11/34
CPC分类号： G11C7/1093 , G11C7/1078 , G11C7/1087
摘要： A write drive data control circuit for controlling the transmission of data to a memory array includes data input means for receiving complimentary data signals which are then transmitted to output circuits. The valid data is latched and the input circuits disabled. The output circuits remain enabled so as to pass the latched data to the memory array. After a predetermined period of time, the output circuits are disabled. In this manner, both the data set up time and data hold time may be independently optimized.
摘要翻译：用于控制向存储器阵列传输数据的写入驱动数据控制电路包括用于接收随后传送到输出电路的互补数据信号的数据输入装置。锁存有效数据，并禁用输入电路。输出电路保持使能，以便将锁存的数据传送到存储器阵列。在预定的时间段之后，输出电路被禁用。以这种方式，可以独立地优化数据建立时间和数据保持时间。

16. 发明授权

US4716302A Identity circuit for an integrated circuit using a fuse and transistor enabled by a power-on reset signal 失效
标题翻译：使用通过上电复位信号使能的保险丝和晶体管的集成电路的标识电路
公开(公告)号：US4716302A
公开(公告)日：1987-12-29
申请号：US945253
申请日：1986-12-22
申请人： Stephen T. Flannagan , Lawrence J. Day , Barry A. Simon
发明人： Stephen T. Flannagan , Lawrence J. Day , Barry A. Simon
IPC分类号： H03K17/18
CPC分类号： H03K17/18 , H01L2223/5444
摘要： An integrated circuit has an identifying circuit coupled to an input. The input has ESD protection. The identifying circuit has a fuse which is in one of two possible states to provide the identifying information. A power on reset circuit provides a pulse in response to application of power to the integrated circuit. A current path between a power supply terminal and the input is provided in response to the power on reset pulse when the fuse is in one state. This current path is blocked when the fuse is in the other state. A user is thus provided with identifying information by the presence or absence of a current path at the input at the time when power is applied.
摘要翻译：集成电路具有耦合到输入的识别电路。输入有ESD保护。识别电路具有处于两种可能状态之一以提供识别信息的熔丝。上电复位电路响应于向集成电路施加电力而提供脉冲。当保险丝处于一个状态时，响应于上电复位脉冲提供电源端子和输入端之间的电流通路。当保险丝处于另一状态时，该电流路径被阻塞。因此，通过在施加电力时在输入端存在或不存在当前路径，向用户提供识别信息。

17. 发明授权

US4453237A Multiple bit output dynamic random-access memory 失效
标题翻译：多位输出动态随机存取存储器
公开(公告)号：US4453237A
公开(公告)日：1984-06-05
申请号：US483772
申请日：1983-04-11
申请人： Edmund A. Reese , Dieter W. Spaderna , Stephen T. Flannagan
发明人： Edmund A. Reese , Dieter W. Spaderna , Stephen T. Flannagan
IPC分类号： G11C11/406 , G11C11/56 , G11C29/00 , G11C29/02 , G11C11/40
CPC分类号： G11C29/80 , G11C11/406 , G11C11/565 , G11C29/02 , G11C7/04
摘要： A dynamic MOS random-access memory is described which includes a circuit for permitting checking of the on chip refresh counter. The memory also includes a refresh generator, the frequency of which automatically varies to compensate for temperature variations. Other innovations include an arbitration circuit, a hidden refresh function and unique accessing of redundant lines.
摘要翻译：描述了一种动态MOS随机存取存储器，其包括用于允许检查片上刷新计数器的电路。存储器还包括刷新发生器，其频率自动变化以补偿温度变化。其他创新包括仲裁电路，隐藏刷新功能和冗余线路的独特访问。

18. 发明授权

US5256917A ECL logic gate with voltage protection 失效
标题翻译： ECL逻辑门电压保护
公开(公告)号：US5256917A
公开(公告)日：1993-10-26
申请号：US863623
申请日：1992-04-03
申请人： Stephen T. Flannagan , John D. Porter
发明人： Stephen T. Flannagan , John D. Porter
IPC分类号： H03K19/003 , H03K19/086 , H03K19/0175
CPC分类号： H03K19/086 , H03K19/00307
摘要： An ECL logic gate (70) includes a voltage protection clamp (60) for protecting a first bipolar transistor (58) from being too heavily reverse biased when an input signal A.sub.IN is pulled to V.sub.SS. The ECL logic gate (70) includes an emitter-follower input stage and a differential amplifier stage. A voltage protection clamp (60) includes a second transistor (52) and a resistor (53) and acts to divide the amount of reverse bias on the first bipolar transistor (58) between a third transistor (51) and the first transistor (58), thereby bringing the reverse bias voltage on the first transistor (58) within acceptable levels to prevent degradation of the first transistor (58).
摘要翻译： ECL逻辑门（70）包括电压保护钳位（60），用于当输入信号AIN被拉到VSS时，用于保护第一双极晶体管（58）不被过大的反向偏置。 ECL逻辑门（70）包括射极跟随器输入级和差分放大级。电压保护夹具（60）包括第二晶体管（52）和电阻器（53），并且用于将第一晶体管（51）和第一晶体管（58）之间的第一双极晶体管（58）上的反向偏置量），从而使第一晶体管（58）上的反向偏置电压达到可接受的水平以防止第一晶体管（58）的劣化。

19. 发明授权

US5059829A Logic level shifting circuit with minimal delay 失效
标题翻译：具有最小延迟的逻辑电平移位电路
公开(公告)号：US5059829A
公开(公告)日：1991-10-22
申请号：US577178
申请日：1990-09-04
申请人： Stephen T. Flannagan , Tai-Sheng Feng
发明人： Stephen T. Flannagan , Tai-Sheng Feng
IPC分类号： H03K19/00 , H03K19/013 , H03K19/0175
CPC分类号： H03K19/0016 , H03K19/0136 , H03K19/017527
摘要： A circuit enabling the conversion of a set of ECL and a set of CMOS logic levels has a differential amplifier, two emitter followers, a current switching circuit, and a level shifting circuit. The differential amplifier provides a common mode input to two emitter followers which switch very rapidly using ECL voltage levels. High operational speed is accomplished by providing a relaxation current during logic high-to-low voltage transients. The current switching circuit conserves power consumption by switching off the relaxation current during logic low-to-high transients, during which time the emitter followers switch sufficiently fast. The level shifting circuit converts the set of ECL logic voltage levels to a set of CMOS voltage levels and the CMOS output voltage is used to control the current switching circuit without introducing a switching delay time.
摘要翻译：能够转换一组ECL和一组CMOS逻辑电平的电路具有差分放大器，两个发射极跟随器，电流切换电路和电平移位电路。差分放大器为使用ECL电压电平非常快速地切换的两个发射极跟随器提供了一个共模输入。通过在逻辑高电压到低电压瞬变期间提供松弛电流来实现高运行速度。电流开关电路通过在逻辑低电平至高瞬态期间关断松弛电流来节省功耗，在此期间发射极跟随器足够快地切换。电平移位电路将ECL逻辑电压电平的集合转换为一组CMOS电压电平，并且CMOS输出电压用于控制电流开关电路而不引入开关延迟时间。

20. 发明授权

US5043602A High speed logic circuit with reduced quiescent current 失效
标题翻译：具有降低静态电流的高速逻辑电路
公开(公告)号：US5043602A
公开(公告)日：1991-08-27
申请号：US498530
申请日：1990-03-26
申请人： Stephen T. Flannagan
发明人： Stephen T. Flannagan
IPC分类号： H03K19/01 , H03K17/042 , H03K17/66 , H03K19/00 , H03K19/08 , H03K19/086
CPC分类号： H03K17/04213 , H03K17/667 , H03K19/001
摘要： A high speed logic circuit with reduced quiescent current receives a plurality of input signals and performs a predetermined logic operation on the plurality of input signals. The predetermined logic operation may be, for example, a comparison of true and complement input signals, or a logical AND of two input signals. In response to the predetermined logic operation, first and second bipolar transistors coupled between first and second power supply voltage terminals are alternately made conductive to provide an output signal therebetween at ECL levels. A biasing portion ensures a proper voltage on a base of the second bipolar transistor. A current portion draws current from the base of the second bipolar transistor until the voltage of the output signal reaches a logic low voltage, and then makes the second transistor nonconductive, keeping the quiescent current of the circuit to a minimum.
摘要翻译：具有降低的静态电流的高速逻辑电路接收多个输入信号并对多个输入信号执行预定的逻辑运算。预定的逻辑运算可以是例如真和补输入信号的比较，或两个输入信号的逻辑与。响应于预定的逻辑操作，耦合在第一和第二电源电压端子之间的第一和第二双极晶体管交替地导通，以在ECL电平之间提供输出信号。偏置部分确保在第二双极晶体管的基极上的适当电压。电流部分从第二双极晶体管的基极吸取电流，直到输出信号的电压达到逻辑低电压，然后使第二晶体管不导通，使电路的静态电流保持最小。

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