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11. 发明授权

US08373221B2 Nanocluster charge storage device 有权
标题翻译：纳米簇电荷存储装置
公开(公告)号：US08373221B2
公开(公告)日：2013-02-12
申请号：US11964309
申请日：2007-12-26
申请人： Robert F. Steimle , Ramachandran Muralidhar , Bruce E. White
发明人： Robert F. Steimle , Ramachandran Muralidhar , Bruce E. White
IPC分类号： H01L29/792
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/823462 , H01L27/11526 , H01L27/11546 , H01L27/11573
摘要： An integrated circuit and method of forming an integrated circuit having a memory portion minimizes an amount of oxidation of nanocluster storage elements in the memory portion. A first region of the integrated circuit has non-memory devices, each having a control electrode or gate formed of a single conductive layer of material. A second region of the integrated circuit has a plurality of memory cells, each having a control electrode of at least two conductive layers of material that are positioned one overlying another. The at least two conductive layers are at substantially a same electrical potential when operational and form a single gate electrode. In one form each memory cell gate has two polysilicon layers overlying a nanocluster storage layer.
摘要翻译：集成电路和形成具有存储器部分的集成电路的方法使存储器部分中的纳米簇存储元件的氧化量最小化。集成电路的第一区域具有非存储器件，每个都具有由单个导电材料层形成的控制电极或栅极。集成电路的第二区域具有多个存储单元，每个存储单元具有至少两个彼此重叠的导电材料层的控制电极。当操作并且形成单个栅电极时，至少两个导电层处于基本相同的电势。在一种形式中，每个存储单元栅极具有覆盖在纳米团簇存储层上的两个多晶硅层。

12. 发明授权

US06964902B2 Method for removing nanoclusters from selected regions 失效
公开(公告)号：US06964902B2
公开(公告)日：2005-11-15
申请号：US10787510
申请日：2004-02-26
申请人： Robert F. Steimle , Jane A. Yater , Gowrishankar L. Chindalore , Craig T. Swift , Steven G. H. Anderson , Ramachandran Muralidhar
发明人： Robert F. Steimle , Jane A. Yater , Gowrishankar L. Chindalore , Craig T. Swift , Steven G. H. Anderson , Ramachandran Muralidhar
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/336 , H01L21/44 , H01L21/8247 , H01L27/105 , H01L29/792
CPC分类号： H01L21/32135 , B82Y10/00 , H01L21/28273 , H01L21/32134 , H01L27/105 , H01L27/11521 , H01L27/11526
摘要： Nanoclusters are blanket deposited on an integrated circuit and then removed from regions where the nanoclusters are not desired. A sacrificial layer is formed in those regions where the nanoclusters are not desired prior to the blanket deposition. The nanoclusters and the sacrificial layer are then removed. In one form, the sacrificial layer includes a deposited nitride containing or oxide containing layer. Alternatively, the sacrificial layer includes at least one of a pad oxide or a pad nitride layer previously used to form isolation regions in the substrate. Nanocluster devices and non-nanocluster devices may then be integrated onto the same integrated circuit. The use of a sacrificial layer protects underlying layers thereby preventing the degradation of performance of the subsequently formed non-nanocluster devices.

13. 发明授权

US06903967B2 Memory with charge storage locations and adjacent gate structures 有权
标题翻译：具有电荷存储位置和相邻门结构的存储器
公开(公告)号：US06903967B2
公开(公告)日：2005-06-07
申请号：US10443908
申请日：2003-05-22
申请人： Leo Mathew , Robert F. Steimle , Ramachandran Muralidhar
发明人： Leo Mathew , Robert F. Steimle , Ramachandran Muralidhar
IPC分类号： G11C11/34 , G11C16/04 , H01L21/28 , H01L21/336 , H01L29/788 , H01L29/792
CPC分类号： B82Y10/00 , G11C16/0458 , G11C16/0475 , G11C2216/06 , H01L21/28273 , H01L29/66818 , H01L29/66825 , H01L29/785 , H01L29/7855 , H01L29/7887 , H01L29/7923
摘要： A memory having gate structures adjacent opposing sidewalls of a semiconductor structure including a channel region and a plurality of charge storage locations between the gate structures and the opposing sidewalls. The channel region is located between two current terminal regions, which in one example serve as the source/drain regions. A memory cell can be implemented in an array of memory cells wherein one gate structure is coupled to one word line and the other gate structure is coupled to another word line. In one example, each cell includes four charge storage locations, each for storing one bit of data.
摘要翻译：一种存储器，其具有邻近半导体结构的相对侧壁的栅极结构，该半导体结构包括沟道区和栅极结构与相对侧壁之间的多个电荷存储位置。沟道区域位于两个电流端子区域之间，在一个示例中，该区域用作源极/漏极区域。存储器单元可以在存储单元的阵列中实现，其中一个栅极结构耦合到一个字线，而另一个栅极结构耦合到另一个字线。在一个示例中，每个单元包括四个电荷存储位置，每个用于存储一位数据。

14. 发明申请

US20090111229A1 METHOD OF FORMING A SPLIT GATE NON-VOLATILE MEMORY CELL 有权
标题翻译：形成分离栅非挥发性记忆细胞的方法
公开(公告)号：US20090111229A1
公开(公告)日：2009-04-30
申请号：US11931376
申请日：2007-10-31
申请人： Robert F. Steimle , Gowrishankar L. Chindalore , Matthew T. Herrick
发明人： Robert F. Steimle , Gowrishankar L. Chindalore , Matthew T. Herrick
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/42348 , H01L29/66825 , H01L29/66833
摘要： A method forms a split gate memory cell by providing a semiconductor substrate and forming an overlying select gate. The select gate has a predetermined height and is electrically insulated from the semiconductor substrate. A charge storing layer is subsequently formed overlying and adjacent to the select gate. A control gate is subsequently formed adjacent to and separated from the select gate by the charge storing layer. The charge storing layer is also positioned between the control gate and the semiconductor substrate. The control gate initially has a height greater than the predetermined height of the select gate. The control gate is recessed to a control gate height that is less than the predetermined height of the select gate. A source and a drain are formed in the semiconductor substrate.
摘要翻译：一种方法通过提供半导体衬底并形成覆盖选择栅极形成分离栅极存储单元。选择栅极具有预定的高度并且与半导体衬底电绝缘。随后形成电荷存储层，覆盖并邻近选择栅极。随后通过电荷存储层形成与选择栅极相邻并分离的控制栅极。电荷存储层也位于控制栅极和半导体衬底之间。控制门最初具有高于选择门的预定高度的高度。控制栅极凹入到小于选择栅极的预定高度的控制栅极高度。源极和漏极形成在半导体衬底中。

15. 发明授权

US07192876B2 Transistor with independent gate structures 有权
标题翻译：具有独立门结构的晶体管
公开(公告)号：US07192876B2
公开(公告)日：2007-03-20
申请号：US10443375
申请日：2003-05-22
申请人： Leo Mathew , Robert F. Steimle , Ramachandran Muralidhar
发明人： Leo Mathew , Robert F. Steimle , Ramachandran Muralidhar
IPC分类号： H01L21/308
CPC分类号： H01L29/785 , G11C16/0458 , G11C16/0475 , H01L27/115 , H01L27/11521 , H01L29/66795 , H01L29/66818 , H01L29/7881 , H01L29/7887 , H01L29/792 , H01L29/7923
摘要： A method of making a transistor with independent gate structures. The gate structures are each adjacent to sidewalls of a semiconductor structure. The method includes depositing at least one conformal layer that includes a layer of gate material over a semiconductor structure that includes the channel region. A planar layer is formed over the wafer. The planar layer has a top surface below the top surface of the rat least one conformal layer at a location over the substrate. The at least one conformal layers are etched to remove the gate material over the semiconductor structure.
摘要翻译：制造具有独立栅极结构的晶体管的方法。栅极结构各自与半导体结构的侧壁相邻。该方法包括在包括沟道区域的半导体结构上沉积包括栅极材料层的至少一个共形层。在晶片上形成平面层。平面层在衬底上方的位置处具有在大致最小一个共形层的顶表面下方的顶表面。蚀刻至少一个共形层以去除半导体结构上的栅极材料。

16. 发明授权

US07361543B2 Method of forming a nanocluster charge storage device 有权
标题翻译：形成纳米团簇电荷存储装置的方法
公开(公告)号：US07361543B2
公开(公告)日：2008-04-22
申请号：US10987047
申请日：2004-11-12
申请人： Robert F. Steimle , Ramachandran Muralidhar , Bruce E. White
发明人： Robert F. Steimle , Ramachandran Muralidhar , Bruce E. White
IPC分类号： H01L21/336
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/823462 , H01L27/11526 , H01L27/11546 , H01L27/11573
摘要： An integrated circuit and method of forming an integrated circuit having a memory portion minimizes an amount of oxidation of nanocluster storage elements in the memory portion. A first region of the integrated circuit has non-memory devices, each having a control electrode or gate formed of a single conductive layer of material. A second region of the integrated circuit has a plurality of memory cells, each having a control electrode of at least two conductive layers of material that are positioned one overlying another. The at least two conductive layers are at substantially a same electrical potential when operational and form a single gate electrode. In one form each memory cell gate has two polysilicon layers overlying a nanocluster storage layer.
摘要翻译：集成电路和形成具有存储器部分的集成电路的方法使存储器部分中的纳米簇存储元件的氧化量最小化。集成电路的第一区域具有非存储器件，每个都具有由单个导电材料层形成的控制电极或栅极。集成电路的第二区域具有多个存储单元，每个存储单元具有至少两个彼此重叠的导电材料层的控制电极。当操作并且形成单个栅电极时，至少两个导电层处于基本相同的电势。在一种形式中，每个存储单元栅极具有覆盖在纳米团簇存储层上的两个多晶硅层。

17. 发明授权

US07183159B2 Method of forming an integrated circuit having nanocluster devices and non-nanocluster devices 有权
标题翻译：形成具有纳米簇装置和非纳米团簇装置的集成电路的方法
公开(公告)号：US07183159B2
公开(公告)日：2007-02-27
申请号：US11035913
申请日：2005-01-14
申请人： Rajesh A. Rao , Robert F. Steimle
发明人： Rajesh A. Rao , Robert F. Steimle
IPC分类号： H01L21/336
CPC分类号： H01L27/11546 , B82Y10/00 , H01L21/823462 , H01L27/088 , H01L27/105 , H01L27/11526 , H01L29/785 , Y10S438/962 , Y10S977/774 , Y10S977/943
摘要： An integrated circuit is formed by identifying multiple regions, each having transistors that have a gate oxide thickness that differs between the multiple regions. One of the regions includes transistors having a nanocluster layer and another of the regions includes transistors with a thin gate oxide used for logic functions. Formation of the gate oxides of the transistors is sequenced based upon the gate oxide thickness and function of the transistors. Thin gate oxides for at least one region of transistors are formed after the formation of gate oxides for the region including the transistors having the nanocluster layer.
摘要翻译：通过识别多个区域形成集成电路，每个区域具有在多个区域之间具有不同栅极氧化物厚度的晶体管。一个区域包括具有纳米团簇层的晶体管，另一个区域包括用于逻辑功能的具有薄栅极氧化物的晶体管。基于晶体管的栅极氧化物厚度和功能对晶体管的栅氧化物的形成进行排序。在用于包括具有纳米团簇层的晶体管的区域的栅极氧化物的形成之后，形成晶体管的至少一个区域的薄栅氧化物。

18. 发明授权

US07700439B2 Silicided nonvolatile memory and method of making same 有权
标题翻译：硅化非易失性存储器及其制造方法
公开(公告)号：US07700439B2
公开(公告)日：2010-04-20
申请号：US11376410
申请日：2006-03-15
申请人： Erwin J. Prinz , Ko-Min Chang , Robert F. Steimle
发明人： Erwin J. Prinz , Ko-Min Chang , Robert F. Steimle
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , B82Y10/00 , H01L21/28273 , H01L27/115
摘要： A memory device is formed on a semiconductor substrate. A select gate electrode and a control gate electrode are formed adjacent to one another. One of either the select gate electrode or the control gate electrodes is recessed with respect to the other. The recess allows for a manufacturable process with which to form silicided surfaces on both the select gate electrode and the control gate electrode.
摘要翻译：存储器件形成在半导体衬底上。选择栅电极和控制栅电极彼此相邻地形成。选择栅极电极或控制栅电极中的一个相对于另一个凹陷。该凹槽允许用于在选择栅极电极和控制栅极电极上形成硅化物表面的可制造工艺。

19. 发明授权

US07579243B2 Split gate memory cell method 有权
标题翻译：分闸存储单元法
公开(公告)号：US07579243B2
公开(公告)日：2009-08-25
申请号：US11535345
申请日：2006-09-26
申请人： Sung-Taeg Kang , Rode R. Mora , Robert F. Steimle
发明人： Sung-Taeg Kang , Rode R. Mora , Robert F. Steimle
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L21/28132 , B82Y10/00 , H01L21/28273 , H01L21/823425 , H01L21/823468 , H01L29/66484 , H01L29/665 , H01L29/66825 , H01L29/7831 , H01L29/7833 , H01L29/7881
摘要： Split gate memory cell formation includes forming a sacrificial layer over a substrate. The sacrificial layer is patterned to form a sacrificial structure with a first sidewall and a second sidewall. A layer of nanocrystals is formed over the substrate. A first layer of polysilicon is deposited over the substrate. An anisotropic etch on the first polysilicon layer forms a first polysilicon sidewall spacer adjacent the first sidewall and a second polysilicon sidewall spacer adjacent the second sidewall. Removal of the sacrificial structure leaves the first sidewall spacer and the second sidewall spacer. A second layer of polysilicon is deposited over the first and second sidewall spacers and the substrate. An anisotropic etch on the second layer of polysilicon forms a third sidewall spacer adjacent to a first side of the first sidewall spacer and a fourth sidewall spacer adjacent to a first side of the second sidewall spacer.
摘要翻译：分离栅极存储单元形成包括在衬底上形成牺牲层。牺牲层被图案化以形成具有第一侧壁和第二侧壁的牺牲结构。在衬底上形成一层纳米晶体。在衬底上沉积第一层多晶硅。在第一多晶硅层上的各向异性蚀刻形成邻近第一侧壁的第一多晶硅侧壁间隔物和邻近第二侧壁的第二多晶硅侧壁间隔物。去除牺牲结构离开第一侧壁间隔物和第二侧壁间隔物。第二层多晶硅沉积在第一和第二侧壁间隔物和基底上。在第二多晶硅层上的各向异性蚀刻形成与第一侧壁间隔物的第一侧相邻的第三侧壁间隔物和邻近第二侧壁间隔物的第一侧的第四侧壁间隔物。

20. 发明申请

US20080076221A1 SPLIT GATE MEMORY CELL METHOD 有权
标题翻译：分离栅存储单元方法
公开(公告)号：US20080076221A1
公开(公告)日：2008-03-27
申请号：US11535345
申请日：2006-09-26
申请人： Sung-Taeg Kang , Rode R. Mora , Robert F. Steimle
发明人： Sung-Taeg Kang , Rode R. Mora , Robert F. Steimle
IPC分类号： H01L21/336
CPC分类号： H01L21/28132 , B82Y10/00 , H01L21/28273 , H01L21/823425 , H01L21/823468 , H01L29/66484 , H01L29/665 , H01L29/66825 , H01L29/7831 , H01L29/7833 , H01L29/7881
摘要： Split gate memory cell formation includes forming a sacrificial layer over a substrate. The sacrificial layer is patterned to form a sacrificial structure with a first sidewall and a second sidewall. A layer of nanocrystals is formed over the substrate. A first layer of polysilicon is deposited over the substrate. An anisotropic etch on the first polysilicon layer forms a first polysilicon sidewall spacer adjacent the first sidewall and a second polysilicon sidewall spacer adjacent the second sidewall. Removal of the sacrificial structure leaves the first sidewall spacer and the second sidewall spacer. A second layer of polysilicon is deposited over the first and second sidewall spacers and the substrate. An anisotropic etch on the second layer of polysilicon forms a third sidewall spacer adjacent to a first side of the first sidewall spacer and a fourth sidewall spacer adjacent to a first side of the second sidewall spacer.
摘要翻译：分离栅极存储单元形成包括在衬底上形成牺牲层。牺牲层被图案化以形成具有第一侧壁和第二侧壁的牺牲结构。在衬底上形成一层纳米晶体。在衬底上沉积第一层多晶硅。在第一多晶硅层上的各向异性蚀刻形成邻近第一侧壁的第一多晶硅侧壁间隔物和邻近第二侧壁的第二多晶硅侧壁间隔物。去除牺牲结构离开第一侧壁间隔物和第二侧壁间隔物。第二层多晶硅沉积在第一和第二侧壁间隔物和基底上。在第二多晶硅层上的各向异性蚀刻形成与第一侧壁间隔物的第一侧相邻的第三侧壁间隔物和邻近第二侧壁间隔物的第一侧的第四侧壁间隔物。

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