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11. 发明授权

US07981731B2 Method of forming a high impedance antifuse 有权
标题翻译：形成高阻抗反熔丝的方法
公开(公告)号：US07981731B2
公开(公告)日：2011-07-19
申请号：US11482688
申请日：2006-07-07
申请人： John A. Fifield , Russell J. Houghton , William R. Tonti
发明人： John A. Fifield , Russell J. Houghton , William R. Tonti
IPC分类号： H01L21/82
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , Y10S438/957 , H01L2924/00
摘要： A programmable element that has a first diode having an electrode and a first insulator disposed between the substrate and said electrode of said first device, said first insulator having a first value of a given characteristic, and an FET having an electrode and a second insulator disposed between the substrate and said electrode of said second device, said second insulator having a second value of said given characteristic that is different from said first value. The electrodes of the diode and the FET are coupled to one another, and a source of programming energy is coupled to the diode to cause it to permanently decrease in resistivity when programmed. The programmed state of the diode is indicated by a current in the FET, which is read by a sense latch. Thus a small resistance change in the diode translates to a large signal gain/change in the latch. This allows the diode to be programmed at lower voltages.
摘要翻译：一种可编程元件，其具有第一二极管，其具有电极和布置在所述基板和所述第一器件的所述电极之间的第一绝缘体，所述第一绝缘体具有给定特性的第一值，以及具有电极和设置在所述第二绝缘体中的第二绝缘体的FET 在所述基板和所述第二装置的所述电极之间，所述第二绝缘体具有与所述第一值不同的所述给定特性的第二值。二极管和FET的电极彼此耦合，并且编程能量源耦合到二极管，以使其在编程时永久地降低电阻率。二极管的编程状态由FET中的电流表示，该电流由读出锁存器读取。因此，二极管中的小电阻变化转换为锁存器中的大信号增益/变化。这允许二极管在较低的电压下被编程。

12. 发明授权

US06388305B1 Electrically programmable antifuses and methods for forming the same 有权
标题翻译：电子可编程反熔丝及其形成方法
公开(公告)号：US06388305B1
公开(公告)日：2002-05-14
申请号：US09466495
申请日：1999-12-17
申请人： Claude L. Bertin , Erik L. Hedberg , Russell J. Houghton , Max G. Levy , Rick L. Mohler , William R. Tonti , Wayne M. Trickle
发明人： Claude L. Bertin , Erik L. Hedberg , Russell J. Houghton , Max G. Levy , Rick L. Mohler , William R. Tonti , Wayne M. Trickle
IPC分类号： H01L2900
CPC分类号： H01L21/763 , H01L23/5252 , H01L27/10861 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A first one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer beneath a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the first layer. The trench comprises an interior surface, a dielectric material lining the interior surface and a conductive material filling the lined trench. The first logic element is configured so that a predetermined voltage or higher applied between the conductive material and the first layer causes a breakdown within a region of the trench. A second one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer formed in a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the first layer. The trench comprises an interior surface, a first dielectric material lining the interior surface and a second dielectric material filling the lined trench. The second logic element further comprises a dielectric layer formed over a portion of the first layer and contacting the first dielectric material lining the trench at a merge location; and an electrode extending over a portion of both the dielectric layer and the filled trench. The second logic element is configured so that a predetermined voltage or higher applied between the electrode and the first layer causes a breakdown near the merge location.
摘要翻译：首先，电压可编程逻辑元件设置在第一导电类型的半导体衬底中，该第一导电类型的半导体衬底包括在衬底的表面下面的第一层，第一层具有第二导电类型; 以及通过表面形成并穿过第一层的沟槽。沟槽包括内表面，衬在内表面的电介质材料和填充衬里沟槽的导电材料。第一逻辑元件被配置为使得施加在导电材料和第一层之间的预定电压或更高的电压导致沟槽区域内的击穿。第二次，电压可编程逻辑元件设置在第一导电类型的半导体衬底中，该半导体衬底包括形成在衬底的表面中的第一层，第一层具有第二导电类型; 以及通过表面形成并穿过第一层的沟槽。沟槽包括内表面，衬在内表面的第一电介质材料和填充衬里沟槽的第二电介质材料。第二逻辑元件还包括形成在第一层的一部分上并且在合并位置处接触衬套在沟槽上的第一介电材料的电介质层; 以及在电介质层和填充沟槽的一部分上延伸的电极。第二逻辑元件被配置为使得施加在电极和第一层之间的预定电压或更高的电压导致合并位置附近的击穿。

13. 发明授权

US07098083B2 High impedance antifuse 失效
标题翻译：高阻抗反熔丝
公开(公告)号：US07098083B2
公开(公告)日：2006-08-29
申请号：US10652534
申请日：2003-08-29
申请人： John A. Fifield , Russell J. Houghton , William R. Tonti
发明人： John A. Fifield , Russell J. Houghton , William R. Tonti
IPC分类号： H01L21/82
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , Y10S438/957 , H01L2924/00
摘要： A programmable element that has a first diode having an electrode and a first insulator disposed between the substrate and said electrode of said first device, said first insulator having a first value of a given characteristic, and an FET having an electrode and a second insulator disposed between the substrate and said electrode of said second device, said second insulator having a second value of said given characteristic that is different from said first value. The electrodes of the diode and the FET are coupled to one another, and a source of programming energy is coupled to the diode to cause it to permanently decrease in resistivity when programmed. The programmed state of the diode is indicated by a current in the FET, which is read by a sense latch. Thus a small resistance change in the diode translates to a large signal gain/change in the latch. This allows the diode to be programmed at lower voltages.
摘要翻译：一种可编程元件，其具有第一二极管，其具有电极和设置在所述基板和所述第一器件的所述电极之间的第一绝缘体，所述第一绝缘体具有给定特性的第一值，以及设置有电极和第二绝缘体的FET 在所述基板和所述第二装置的所述电极之间，所述第二绝缘体具有与所述第一值不同的所述给定特性的第二值。二极管和FET的电极彼此耦合，并且编程能量源耦合到二极管，以使其在编程时永久地降低电阻率。二极管的编程状态由FET中的电流表示，该电流由读出锁存器读取。因此，二极管中的小电阻变化转换为锁存器中的大信号增益/变化。这允许二极管在较低的电压下被编程。

14. 发明授权

US06222395B1 Single-ended semiconductor receiver with built in threshold voltage difference 失效
标题翻译：单端半导体接收器内置阈值电压差
公开(公告)号：US06222395B1
公开(公告)日：2001-04-24
申请号：US09225112
申请日：1999-01-04
申请人： Claude L. Bertin , Russell J. Houghton , William R. Tonti
发明人： Claude L. Bertin , Russell J. Houghton , William R. Tonti
IPC分类号： G05F110
CPC分类号： G05F3/205
摘要： A differential receiver for sensing small input voltage swings by using a built in reference voltage obtained by a difference in threshold voltage between a differential pair of closely spaced transistors. The difference in threshold voltage can be produced by different values of ion implantation of the gates of the transistor pair with the same material, or by dosages using different materials. The difference in threshold voltage can also be obtained by using different transistor channel lengths. The threshold voltages can also be modulated by the control of the transistor substrate voltages using a voltage control substrate means.
摘要翻译：一种差分接收器，用于通过使用通过差分对间隔晶体管之间的阈值电压差而获得的内置参考电压来感测小输入电压摆幅。阈值电压的差异可以通过使用相同材料的晶体管对的栅极的离子注入的不同值，或通过使用不同材料的剂量来产生。也可以通过使用不同的晶体管沟道长度来获得阈值电压的差异。也可以通过使用电压控制衬底装置控制晶体管衬底电压来调制阈值电压。

15. 发明授权

US06177807B1 High frequency valid data strobe 失效
标题翻译：高频有效数据选通
公开(公告)号：US06177807B1
公开(公告)日：2001-01-23
申请号：US09322465
申请日：1999-05-28
申请人： Claude L. Bertin , John A. Fifield , Erik L. Hedberg , Russell J. Houghton , William R. Tonti
发明人： Claude L. Bertin , John A. Fifield , Erik L. Hedberg , Russell J. Houghton , William R. Tonti
IPC分类号： G03K1716
CPC分类号： G06F13/4086 , H03K5/06 , H04L25/0298
摘要： A processor with a memory send/received control circuit including a bus drive circuit and a detector circuit connected via control bus line to the control input of the memory. A data input line, or output line, or data input/output line is connected between the processor and the memory. A transmission line stub having a length that is incrementally variable is connected to the memory control input side of the control line 14. The impedance Z0 of the transmission line stub is equal to that of the control line and is open circuited at the end which results in voltage doubling to achieve high speed synchronization between control signals and data signals and to ensure valid data at high clock rates.
摘要翻译：具有存储器发送/接收控制电路的处理器，包括总线驱动电路和经由控制总线连接到存储器的控制输入端的检测器电路。数据输入线或输出线或数据输入/输出线连接在处理器和存储器之间。具有递增可变长度的传输线短截线连接到控制线14的存储器控制输入侧。传输线短截线的阻抗Z0等于控制线的阻抗Z0，并在结束时开路在电压倍增以实现控制信号和数据信号之间的高速同步，并确保在高时钟速率下的有效数据。

16. 发明授权

US5909400A Three device BICMOS gain cell 失效
标题翻译：三器件BICMOS增益单元
公开(公告)号：US5909400A
公开(公告)日：1999-06-01
申请号：US917630
申请日：1997-08-22
申请人： Claude Louis Bertin , John Atkinson Fifield , Russell J. Houghton , Christopher P. Miller , William R. Tonti
发明人： Claude Louis Bertin , John Atkinson Fifield , Russell J. Houghton , Christopher P. Miller , William R. Tonti
IPC分类号： G11C11/405 , G11C11/406 , G11C11/34
CPC分类号： G11C11/406 , G11C11/405
摘要： A nondestructive read, three device BICMOS gain cell for a DRAM memory having two FETs and one bipolar device. The gain cell has an improved access time (less latency), can operate for longer periods of time before a refresh operation is required, requires a smaller storage capacitance than a traditional DRAM cell, and can be produced commercially at lower costs than are presently available. In a preferred embodiment, the gain cell comprises an n channel metal oxide semiconductor field effect write transistor having its gate connected to a write word line WLw. Its drain is connected to a storage node Vs having a storage capacitance Cs associated therewith, and its source is connected to a write bit line BLw. An n channel metal oxide semiconductor field effect read transistor has its gate connected to the storage node Vs and its source connected to a read word line WLr. A PNP transistor has its base connected to the drain of the read transistor and its emitter connected to a read bit line BLr. A second embodiment is constructed with p channel FETs and an NPN transistor.
摘要翻译：具有两个FET和一个双极器件的DRAM存储器的非破坏性读取，三器件BICMOS增益单元。增益单元具有改进的访问时间（更低的延迟），可以在需要刷新操作之前更长时间地操作，需要比传统DRAM单元更小的存储电容，并且可以以比目前可用的更低的成本在商业上生产。在优选实施例中，增益单元包括其栅极连接到写入字线WLw的n沟道金属氧化物半导体场效应写入晶体管。其漏极连接到具有与其相关联的存储电容Cs的存储节点Vs，并且其源极连接到写入位线BLw。 n沟道金属氧化物半导体场效应读取晶体管的栅极连接到存储节点Vs，其源极连接到读取字线WLr。 PNP晶体管的基极连接到读晶体管的漏极，其发射极连接到读位线BLr。第二实施例由p沟道FET和NPN晶体管构成。

17. 发明授权

US06369606B1 Mixed threshold voltage CMOS logic device and method of manufacture therefor 失效
标题翻译：混合阈值电压CMOS逻辑器件及其制造方法
公开(公告)号：US06369606B1
公开(公告)日：2002-04-09
申请号：US09670945
申请日：2000-09-27
申请人： Russell J. Houghton , William R. Tonti , Thomas Vogelsang , Adam B. Wilson
发明人： Russell J. Houghton , William R. Tonti , Thomas Vogelsang , Adam B. Wilson
IPC分类号： H03K1923
CPC分类号： H03K19/0948 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H03K19/0963
摘要： A logic circuit implementing a logic function and method of manufacture thereof. The logic circuit includes a series connection of two or more CMOS devices, at least one CMOS device having a threshold voltage at an input lower than a threshold voltage at an input of another of the CMOS devices. The CMOS logic circuit exhibits enhanced switching speed for logic operations and reduced leakage current when operating in an off-state. A logic family is built around the series connection of two or more devices having mixed voltage threshold inputs for enhanced switching speed and reduced off-current leakage.
摘要翻译：实现逻辑功能的逻辑电路及其制造方法。逻辑电路包括两个或更多个CMOS器件的串联连接，至少一个CMOS器件在另一个CMOS器件的输入处具有低于阈值电压的输入处的阈值电压。 CMOS逻辑电路表现出增强的逻辑运算开关速度，并且在关断状态下运行时具有降低的漏电流。逻辑系列是围绕具有混合电压阈值输入的两个或多个器件的串联连接构成的，以提高开关速度和减少的漏电流。

18. 发明授权

US06580650B2 DRAM word line voltage control to insure full cell writeback level 有权
标题翻译： DRAM字线电压控制，以确保全单元回写级别
公开(公告)号：US06580650B2
公开(公告)日：2003-06-17
申请号：US09810325
申请日：2001-03-16
申请人： Wayne F. Ellis , Russell J. Houghton , Mark D. Jacunski , Thomas M. Maffitt , William R. Tonti
发明人： Wayne F. Ellis , Russell J. Houghton , Mark D. Jacunski , Thomas M. Maffitt , William R. Tonti
IPC分类号： G11C700
CPC分类号： G11C11/4085 , G11C8/08
摘要： A DC analog circuit which monitors a DRAM sample cell access device and outputs a DC reference voltage to the word line voltage regulation system. The resulting output voltage Vpp from the word line voltage regulation system will then vary in accordance with the cell access device parametrics so as to guarantee a full high level will always be written into the DRAM cell.
摘要翻译： DC模拟电路，用于监视DRAM采样单元存取装置，并将直流参考电压输出到字线电压调节系统。然后，来自字线电压调节系统的结果输出电压Vpp将根据信元接入设备参数而变化，以保证将始终向DRAM单元写入一个完整的高电平。

19. 发明授权

US06574763B1 Method and apparatus for semiconductor integrated circuit testing and burn-in 失效
标题翻译：用于半导体集成电路测试和老化的方法和装置
公开(公告)号：US06574763B1
公开(公告)日：2003-06-03
申请号：US09473886
申请日：1999-12-28
申请人： Claude L. Bertin , Erik L. Hedberg , Russell J. Houghton , William R. Tonti
发明人： Claude L. Bertin , Erik L. Hedberg , Russell J. Houghton , William R. Tonti
IPC分类号： G01R3128
CPC分类号： G01R31/287
摘要： A burn-in process is provided for a memory array having redundant bits and addressable storage locations. The burn-in process includes the steps of raising the temperature of the memory array to a pre-determined temperature, testing all bits in the array, detecting faulty bits and operable bits, replacing faulty bits with redundant operable bits, correcting any defects in the array in-situ, and lowering the temperature of the memory array to ambient temperature to complete the burn-in process. An apparatus for carrying out the above process is provided that includes a test circuit for generating a test pattern and for applying the test pattern to the memory array so as to test all bits within the memory array. A comparison circuit, coupled to the test circuit and adapted to couple to the memory array, compares an actual response and an expected response of the memory array to the test pattern and detects faulty and operable bits based thereon. A failed address buffer register, coupled to the comparison circuit and to the test circuit, stores an address of each addressable storage location that has a faulty bit. Sparing control logic, coupled to the failed address buffer register and adapted to couple to the memory array, reads out each address stored by the failed address buffer register and replaces each faulty bit with a redundant operable bit.
摘要翻译：为具有冗余位和可寻址存储位置的存储器阵列提供老化过程。老化过程包括以下步骤：将存储器阵列的温度升高到预定温度，测试阵列中的所有位，检测故障位和可操作位，用冗余的可操作位代替故障位，校正在阵列原位，并将存储器阵列的温度降低到环境温度以完成老化过程。提供了一种用于执行上述处理的装置，其包括用于生成测试图案并将测试图案应用于存储器阵列的测试电路，以便测试存储器阵列内的所有位。耦合到测试电路并且适于耦合到存储器阵列的比较电路将存储器阵列的实际响应和预期响应与测试模式进行比较，并基于此检测故障和可操作的位。耦合到比较电路和测试电路的故障地址缓冲寄存器存储具有错误位的每个可寻址存储位置的地址。冗余控制逻辑耦合到故障地址缓冲寄存器并适于耦合到存储器阵列，读出由故障地址缓冲寄存器存储的每个地址，并用冗余可操作位替换每个故障位。

20. 发明授权

US06268748B1 Module with low leakage driver circuits and method of operation 失效
标题翻译：具有低泄漏驱动电路的模块和操作方法
公开(公告)号：US06268748B1
公开(公告)日：2001-07-31
申请号：US09073517
申请日：1998-05-06
申请人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Christopher P. Miller , William R. Tonti
发明人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Christopher P. Miller , William R. Tonti
IPC分类号： G03K19094
CPC分类号： G11C7/1069 , G11C7/1051 , H03K19/0016 , H03K19/09429
摘要： An electronic semiconductor module, either memory or logic, having a driver circuit which includes a multiplicity of driver transistors, together with circuitry for simultaneously applying a first positive bias to a first select number of driver transistors to activate them to an operational state, a second positive bias to a second select number of driver transistors to place them in readiness for activation, and a negative bias to the remaining driver transistors to place them in a fully inactive state thereby reducing noise in the driver circuit. The first positive bias is greater than the transistor threshold voltage, preferably greater than two volts, the second positive bias is less than the threshold voltage, preferably less than one volt, and the negative bias is in the order of minus 0.3 volt. A method of reducing noise in the electronic semiconductor module is also described and includes the applying of a positive bias to a first select number of the transistors to activate them while simultaneously applying a second positive bias to a second select number of the transistors to ready them for activation, and a negative voltage to the remaining transistors to place each in a inactive condition.
摘要翻译：一种电子半导体模块，无论是存储器还是逻辑，具有包括多个驱动器晶体管的驱动器电路，以及用于同时向第一选择数量的驱动器晶体管施加第一正偏置以将其激活到操作状态的电路，第二对第二选择数量的驱动器晶体管施加正偏置以使它们准备激活，以及对其余驱动器晶体管的负偏置以将它们置于完全无效状态，从而降低驱动器电路中的噪声。第一正偏压大于晶体管阈值电压，优选大于2伏，第二正偏压小于阈值电压，优选小于1伏特，负偏压为零下0.3伏。还描述了降低电子半导体模块中的噪声的方法，并且包括将正偏压施加到第一选择数量的晶体管以激活它们，同时向第二选择数量的晶体管施加第二正偏置以准备它们用于激活，并且向剩余晶体管施加负电压以使其处于非活动状态。

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