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11. 发明专利

JP2002208856A PLL CIRCUIT AND RADIO COMMUNICATION TERMINAL DEVICE 失效
公开(公告)号：JP2002208856A
公开(公告)日：2002-07-26
申请号：JP2001083973
申请日：2001-03-23
申请人： HITACHI LTD , TTP COMMUNICATIONS LTD
发明人： YAMAWAKI DAIZO , TANAKA SATOSHI , HAYASHI NORIO , WATANABE KAZUO , HENSHAW BOB
IPC分类号： H03L7/093 , H03L7/07 , H03L7/08 , H03L7/085 , H03L7/10 , H04B1/40 , H04L27/152
摘要： PROBLEM TO BE SOLVED: To provide a PLL circuit which can make convergence at a high speed and convert an IF signal into an RF signal and a radio communication terminal device using the PLL circuit. SOLUTION: An LPF 103 charging constant current source 101, a discharging constant current source 200 and a high-speed charging constant current source 201 are connected to an output of a current output type phase comparator of the PLL circuit. In the case where the convergence frequency of the PLL circuit is low, an input voltage of a VCO 104 is increased from 0 V, so as to be converged by using the constant current source 101. Meanwhile, in the case where the convergence frequency is high, the input voltage is temporarily increased to the maximum voltage by using the constant current source 201. Thereafter, the input voltage is gradually dropped from the maximum voltage, so as to be converged by using the constant current source 200. By selecting above operation by the convergence frequency, it is possible to shorten the maximum convergence time of the PLL circuit.

12. 发明公开

EP1115205A4 PLL CIRCUIT AND RADIO COMMUNICATION TERMINAL USING PLL 失效转让
标题翻译： PLL-SCHALTUNG UND FUNKBETRIEBENESKOMMUNIKATIONSSENDEGERÄTMIT EINER PHASENREGELSCHLEIFE
公开(公告)号：EP1115205A4
公开(公告)日：2004-03-24
申请号：EP99943334
申请日：1999-09-14
申请人： HITACHI LTD , TTP COMMUNICATIONS LTD
发明人： YAMAWAKI TAIZO , ENDO TAKEFUMI , WATANABE KAZUO , HORI KAZUAKI , HILDERSLEY JULIAN
IPC分类号： H03L7/10 , H03D13/00 , H03L7/00 , H03L7/08 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/107 , H03L7/16 , H03L7/18 , H04B1/3822 , H04B1/40 , H04L7/033
CPC分类号： H03L7/10 , H03D13/007 , H03L7/08 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/16 , H03L2207/12 , H04B1/406
摘要： A PLL circuit requiring only one LPF is provided to decrease the mounting area and the number of pins and simplify its design, whereas the prior art PLL circuit requires an n number of LPFs. The PLL circuit comprises a variable-gain phase comparator (1), a mixer (2), LPPs (3), n VCOs (4-1 - 4-n), n couplers (5-1 - 5-n), and a control circuit (6) for performing the ON/OFF control of the VCO operation, and the phase difference conversion gain of the variable-gain phase comparator (1) is variable. The control circuit (6) carries out the ON/OFF control of the operation of the VCOs (4-1 - 4-n), and one of the VCOs (4-1 - 4-n) operates depending on a desired operation frequency band, while other VCOs are off. The phase difference conversion gain can be varied depending on the sensitivity of the VCOs (4-1 - 4-n), resulting in the required number of LPFs reduced to one.
摘要翻译：提供了PLL电路和使用PLL电路的无线通信终端装置。在PLL电路中，已经需要的n个LPF的数量减少到仅一个LPF，使得PLL电路可以减少安装面积和引脚数量，并且可以简化其设计。根据本发明的PLL电路包括可变增益相位比较器1，混频器2，LPF 3，n个VCO 4-1至4n，n个耦合器5-1至5-n，以及控制电路6，用于控制VCO的操作的开/关。可变增益相位比较器1是能够改变相位差增益的相位比较器。通过控制电路6，根据期望的工作频带来操作VCO 4-1至4n和VCO 4-1至4-n中的一个的操作的导通/截止; 其他VCO被控制为关闭状态。相位差转换增益根据VCO 4-1至4-n的灵敏度而变化，从而可将PLL电路所需的LPF数减少到仅一个。

13. 发明专利

DE60041784D1 未知
公开(公告)号：DE60041784D1
公开(公告)日：2009-04-23
申请号：DE60041784
申请日：2000-01-11
申请人： TTP COMMUNICATIONS LTD , HITACHI LTD
发明人： YAMAWAKI TAIZO , TANAKA SATOSHI , KOKUBO MASARU , WATANABE KAZUO , KASAHARA MASUMI , HORI KAZUAKI , HILDERSLEY JULIAN
IPC分类号： H04B1/04 , H03C3/09 , H03D7/00 , H03D7/16 , H03L7/18 , H03L7/185 , H03L7/23 , H04B1/38 , H04L25/03 , H04L27/12
摘要： A transmitter in which the problem of unwanted spurious signals due to harmonics of the output signal from a frequency synthesizer and due to mixture of harmonics of the output signal from a crystal oscillator into a VCO and which facilitates the design of circuits and mounting boards, and a terminal using the transmitter are disclosed. In the transmitter, the relationship between the output frequency of a frequency converting circuit (5) comprising a PLL and the output frequencies of frequency synthesizers (1, 2) is stored. By controlling the output frequencies of the frequency synthesizers inputted to the frequency converting circuit (5) according to the relationship, the unwanted spurious signal is suppressed. Thus, even if an unwanted spurious signal is included in the output of the transmitter because of the crosstalk between circuits and boards, the spurious signal can be suppressed, thereby shortening the time to re-design circuits and boards and reducing the r e-designing cost.

14. 发明专利

NO318601B1 未知
公开(公告)号：NO318601B1
公开(公告)日：2005-04-18
申请号：NO980399
申请日：1998-01-29
申请人： HITACHI LTD , TTP COMMUNICATIONS LTD
发明人： YAMAWAKI TAIZO , KOKUBO MASARU , FURUYA TOMIO , WATANABE KAZUO , HILDERSLEY JULIAN
IPC分类号： H03L7/085 , H03L7/093 , H03L7/10 , H03L7/183 , H03L7/185 , H04B1/3822 , H04B1/40
摘要： A phase-locked loop circuit includes a current output type phase comparator (1) for converting a phase difference of a first signal (fIN) and a second signal (fREF) into a current signal to be produced, a low pass filter (4) for filtering the current signal of the current output type phase comparator (1) to produce an output signal, a voltage controlled oscillator (5) for producing a signal having a frequency (fRF) corresponding to the output signal of the low pass filter (4) and a frequency converter (7) for frequency-converting the output signal of the voltage controlled oscillator (5) to produce a second signal. A current source (2) is provided for supplying a current which is added to the current signal produced by the phase comparator (1), and the resulting sum current is supplied to an input of the low-pass filter (4). Furthermore a reset switch (3) applies a reset voltage to the voltage controlled oscillator (5) for cancelling a phase-locked state of the phase-lock loop circuit. The phase-locked loop may be used in a transmittor section of a radio communication apparatus, such as a portable terminal of a mobile communication system, to provide for a short frequency settling time and low output noise without broadening of the band of the PLL.

15. 发明专利

AU2003289425A1 TRANSMISSION CIRCUIT AND TRANSMITTER/RECEIVER USING SAME 未知
公开(公告)号：AU2003289425A1
公开(公告)日：2004-07-14
申请号：AU2003289425
申请日：2003-12-18
申请人： RENESAS TECH CORP
发明人： YAMAWAKI TAIZO , HORI KAZUAKI , WATANABE KAZUO , TANAKA SATOSHI
IPC分类号： H03C3/40 , H03D3/00 , H04B1/04 , H04B1/30 , H04B1/3822 , H04B1/40 , H03D7/12

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