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11. 发明授权

US08367490B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08367490B2
公开(公告)日：2013-02-05
申请号：US13144182
申请日：2011-03-04
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/84 , H01L29/42384 , H01L29/4908 , H01L29/6675 , H01L29/78603 , H01L29/78648 , H01L2924/0002 , H01L2924/00
摘要： The present application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure according to the present invention adjusts a threshold voltage with a common contact, which has a portion outside the source or drain region extending to the back-gate region and provides an electrical contact of the source or drain region and the back-gate region, which leads to a simple manufacturing process, an increased integration level and a lowered manufacture cost. Moreover, the asymmetric design of the back-gate structure further increases the threshold voltage and improves the performance of the device.
摘要翻译：本申请公开了一种半导体结构及其制造方法。根据本发明的半导体结构利用公共接触来调节阈值电压，该公共触点具有延伸到背栅极区域的源极或漏极区域之外的部分并且提供源极或漏极区域与背栅极的电接触区域，这导致简单的制造过程，增加的集成水平和降低的制造成本。此外，背栅结构的非对称设计进一步增加了阈值电压并提高了器件的性能。

12. 发明申请

US20120290998A1 DEVICE PERFORMANCE PREDICTION METHOD AND DEVICE STRUCTURE OPTIMIZATION METHOD 审中-公开
标题翻译：器件性能预测方法和器件结构优化方法
公开(公告)号：US20120290998A1
公开(公告)日：2012-11-15
申请号：US13320291
申请日：2011-04-26
申请人： Qingqing Liang , Huilong Zhu , Huicai Zhong , Meng Li
发明人： Qingqing Liang , Huilong Zhu , Huicai Zhong , Meng Li
IPC分类号： G06F17/50
CPC分类号： H01L22/20
摘要： The present application discloses a device performance prediction method and a device structure optimization method. According to an embodiment of the present invention, a set of structural parameters and/or process parameters for a semiconductor device constitutes a parameter point in a parameter space, and a behavioral model library is established with respect to a plurality of discrete predetermined parameter points in the parameter space, and the predetermined parameter points being associated with their respective performance indicator values in the behavioral model library. The device performance prediction method comprises: inputting a parameter point, called “predicting point”, whose performance indicator value is to be predicted; and if the predicting point has a corresponding record in the behavioral model library, outputting the corresponding performance indicator value as a predicted performance indicator value of the predicting point, or otherwise if there is no record corresponding to the predicting point in the behavioral model library, calculating a predicted performance indicator value of the predicting point by interpolation based on Delaunay triangulation.
摘要翻译：本申请公开了一种设备性能预测方法和设备结构优化方法。根据本发明的实施例，用于半导体器件的一组结构参数和/或工艺参数构成参数空间中的参数点，并且针对多个离散的预定参数点建立行为模型库参数空间以及与行为模型库中其各自的性能指标值相关联的预定参数点。设备性能预测方法包括：输入要预测其性能指标值的称为预测点的参数点; 并且如果预测点在行为模型库中具有对应的记录，则输出相应的表现指标值作为预测点的预测性能指标值，否则如果没有与行为模型库中的预测点相对应的记录，通过基于Delaunay三角测量的插值计算预测点的预测性能指标值。

13. 发明申请

US20120281468A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体器件和半导体存储器件
公开(公告)号：US20120281468A1
公开(公告)日：2012-11-08
申请号：US13320331
申请日：2011-08-10
申请人： Qingqing Liang , Xiaodong Tong , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Xiaodong Tong , Huicai Zhong , Huilong Zhu
IPC分类号： G11C11/34
CPC分类号： G11C11/39 , G11C17/06 , G11C2213/72 , G11C2213/74 , H01L27/1027
摘要： The present disclosure provides a semiconductor device and a semiconductor memory device. The semiconductor device can be used as a memory cell, and may comprise a first P-type semiconductor layer, a first N-type semiconductor layer, a second P-type semiconductor layer, and a second N-type semiconductor layer arranged in sequence. A first data state may be stored in the semiconductor device by applying a forward bias, which is larger than a punch-through voltage VBO, between the first P-type semiconductor layer and the second N-type semiconductor layer. A second data state may be stored in the semiconductor device by applying a reverse bias, which is approaching to the reverse breakdown region of the semiconductor device, between the first P-type semiconductor layer and the second N-type semiconductor layer. In this way, the semiconductor device may be effectively used for data storage. The semiconductor memory device comprises an array of memory cells consisted of the semiconductor devices.
摘要翻译：本公开提供了半导体器件和半导体存储器件。半导体器件可以用作存储单元，并且可以包括依次布置的第一P型半导体层，第一N型半导体层，第二P型半导体层和第二N型半导体层。第一数据状态可以通过在第一P型半导体层和第二N型半导体层之间施加大于穿通电压VBO的正向偏压来存储在半导体器件中。第二数据状态可以通过在第一P型半导体层和第二N型半导体层之间施加正在接近半导体器件的反向击穿区域的反向偏压来存储在半导体器件中。以这种方式，半导体器件可以有效地用于数据存储。半导体存储器件包括由半导体器件组成的存储器单元的阵列。

14. 发明申请

US20120187491A1 METHOD FOR FORMING RETROGRADED WELL FOR MOSFET 有权
标题翻译：用于形成MOSFET的退火方法
公开(公告)号：US20120187491A1
公开(公告)日：2012-07-26
申请号：US13429948
申请日：2012-03-26
申请人： Huilong Zhu , Zhijiong Luo , Qingqing Liang , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Qingqing Liang , Haizhou Yin
IPC分类号： H01L29/772
CPC分类号： H01L21/187 , H01L21/6835 , H01L21/84 , H01L27/12 , H01L29/1083 , H01L2221/6835 , H01L2221/68368
摘要： A method of forming an electrical device is provided that includes forming at least one semiconductor device on a first semiconductor layer of the SOI substrate. A handling structure is formed contacting the at least one semiconductor device and the first semiconductor layer. A second semiconductor layer and at least a portion of the dielectric layer of the SOI substrate are removed to provide a substantially exposed surface of the first semiconductor layer. A retrograded well may be formed by implanting dopant through the substantially exposed surface of the first semiconductor layer into a first thickness of the semiconductor layer that extends from the substantially exposed surface of the semiconductor layer, wherein a remaining thickness of the semiconductor layer is substantially free of the retrograded well dopant. The retrograded well may be laser annealed.
摘要翻译：提供一种形成电气装置的方法，包括在SOI衬底的第一半导体层上形成至少一个半导体器件。形成接触至少一个半导体器件和第一半导体层的处理结构。去除第二半导体层和SOI衬底的电介质层的至少一部分以提供第一半导体层的基本暴露的表面。可以通过将掺杂剂通过第一半导体层的基本上暴露的表面注入从半导体层的基本暴露的表面延伸的半导体层的第一厚度来形成退化的阱，其中半导体层的剩余厚度基本上不含的回归井掺杂剂。退火井可以进行激光退火。

15. 发明申请

US20120181509A1 GRAPHENE DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：石墨装置及其制造方法
公开(公告)号：US20120181509A1
公开(公告)日：2012-07-19
申请号：US13143932
申请日：2011-02-23
申请人： Qingqing Liang , Zhi Jin , Wenwu Wang , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Zhi Jin , Wenwu Wang , Huicai Zhong , Huilong Zhu
IPC分类号： H01L29/775 , H01L21/335
CPC分类号： H01L29/66045 , H01L29/1606 , H01L29/66742 , H01L29/78618 , H01L29/78684
摘要： A graphene device structure and a method for manufacturing the same are provided. The graphene device structure comprises: a graphene layer; a gate region formed on the graphene layer; and a doped semiconductor region formed at one side of the gate region and connected with the graphene layer, wherein the doped semiconductor region is a drain region of the graphene device structure, and the graphene layer formed at one side of the gate region is a source region of the graphene device structure. The on/off ratio of the graphene device structure may be improved by the doped semiconductor region without increasing the band gaps of the graphene material, so that the applicability of the graphene material in CMOS devices may be enhanced without decreasing the carrier mobility of graphene materials and speed of the devices.
摘要翻译：提供石墨烯器件结构及其制造方法。石墨烯器件结构包括：石墨烯层; 形成在所述石墨烯层上的栅极区域; 以及形成在所述栅极区域的一侧并与所述石墨烯层连接的掺杂半导体区域，其中所述掺杂半导体区域是所述石墨烯器件结构的漏极区域，并且形成在所述栅极区域一侧的所述石墨烯层是源极石墨烯器件结构的区域。可以通过掺杂半导体区域改善石墨烯器件结构的开/关比，而不增加石墨烯材料的带隙，从而可以增强石墨烯材料在CMOS器件中的适用性，而不降低石墨烯材料的载流子迁移率和设备的速度。

16. 发明申请

US20120168865A1 Transistor and Method for Manufacturing the Same 有权
标题翻译：晶体管及其制造方法
公开(公告)号：US20120168865A1
公开(公告)日：2012-07-05
申请号：US13144903
申请日：2011-02-25
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/78648 , H01L29/66545 , H01L29/66628
摘要： The invention relates to a transistor and a method for manufacturing the transistor. The transistor according to an embodiment of the invention may comprise: a substrate which comprises at least a back gate of the transistor, an insulating layer and a semiconductor layer stacked sequentially, wherein the back gate of the transistor is used for adjusting the threshold voltage of the transistor; a gate stack formed on the semiconductor layer, wherein the gate stack comprises a gate dielectric and a gate electrode formed on the gate dielectric; a spacer formed on sidewalls of the gate stack; and a source region and a drain region located on both sides of the gate stack, respectively, wherein the height of the gate stack is lower than the height of the spacer. The transistor enables the height of the gate stack to be reduced and therefore the performance of the transistor is improved.
摘要翻译：本发明涉及晶体管及其制造方法。根据本发明的实施例的晶体管可以包括：至少包括晶体管的背栅极，绝缘层和顺序层叠的半导体层的衬底，其中晶体管的背栅极用于调节晶体管的阈值电压晶体管; 形成在所述半导体层上的栅极堆叠，其中所述栅极堆叠包括形成在所述栅极电介质上的栅极电介质和栅电极; 形成在栅叠层的侧壁上的间隔物; 以及分别位于栅极堆叠的两侧的源极区域和漏极区域，其中栅极叠层的高度低于间隔物的高度。该晶体管能够降低栅极叠层的高度，从而提高晶体管的性能。

17. 发明申请

US20120146103A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120146103A1
公开(公告)日：2012-06-14
申请号：US13378206
申请日：2011-02-27
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L27/092 , H01L21/336
CPC分类号： H01L29/165 , H01L21/30608 , H01L29/1054 , H01L29/1083 , H01L29/517 , H01L29/6653 , H01L29/66553 , H01L29/66583 , H01L29/6659 , H01L29/66651 , H01L29/7834 , H01L29/7849
摘要： The present application discloses a semiconductor device and a method of manufacturing the same. Wherein, the semiconductor device comprises: a semiconductor substrate; a stressor embedded in the semiconductor substrate; a channel region disposed on the stressor; a gate stack disposed on the channel region; a source/drain region disposed on two sides of the channel region and embedded in the semiconductor substrate; wherein, surfaces of the stressor comprise a top wall, a bottom wall, and side walls, the side walls comprising a first side wall and a second side wall, the first side wall connecting the top wall and the second side wall, the second side wall connecting the first side wall and the bottom wall, the angle between the first side wall and the second side wall being less than 180°, and the first sidewall and the second side wall being roughly symmetrical with respect to a plane parallel to the semiconductor substrate. Embodiments of the present invention are applicable to the stress engineering technology in the semiconductor device manufacturing.
摘要翻译：本申请公开了半导体器件及其制造方法。其中，所述半导体器件包括：半导体衬底; 嵌入在半导体衬底中的应力器; 设置在所述应力器上的通道区域; 设置在通道区域上的栅极堆叠; 源极/漏极区域，设置在沟道区域的两侧并且嵌入在半导体衬底中; 其中，所述应力器的表面包括顶壁，底壁和侧壁，所述侧壁包括第一侧壁和第二侧壁，所述第一侧壁连接所述顶壁和所述第二侧壁，所述第二侧连接第一侧壁和底壁的壁，第一侧壁和第二侧壁之间的角度小于180°，第一侧壁和第二侧壁相对于平行于半导体的平面大致对称基质。本发明的实施例可应用于半导体器件制造中的应力工程技术。

18. 发明授权

US08138029B2 Structure and method having asymmetrical junction or reverse halo profile for semiconductor on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) 失效
标题翻译：具有半导体绝缘体（SOI）金属氧化物半导体场效应晶体管（MOSFET）的不对称结或反向晕轮廓的结构和方法
公开(公告)号：US08138029B2
公开(公告)日：2012-03-20
申请号：US12686402
申请日：2010-01-13
申请人： Huilong Zhu , Zhijiong Luo , Qingqing Liang , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Qingqing Liang , Haizhou Yin
IPC分类号： H01L21/00
CPC分类号： H01L27/1207 , H01L21/76251 , H01L21/8221 , H01L27/0688 , H01L29/66545
摘要： A device and method is provided that in one embodiment provides a first semiconductor device including a first gate structure on a first channel region, in which a first source region and a first drain region are present on opposing sides of the first channel region, in which a metal nitride spacer is present on only one side of the first channel region. The device further includes a second semiconductor device including a second gate structure on a second channel region, in which a second source region and a second drain region are present on opposing sides of the second channel region. Interconnects may be present providing electrical communication between the first semiconductor device and the second semiconductor device, in which at least one of the first semiconductor device and the second semiconductor device is inverted. A structure having a reverse halo dopant profile is also provided.
摘要翻译：提供了一种装置和方法，在一个实施例中提供了第一半导体器件，其包括在第一沟道区上的第一栅极结构，其中第一源区和第一漏区存在于第一沟道区的相对侧上，其中金属氮化物间隔物仅存在于第一沟道区的一侧。该器件还包括在第二沟道区上包括第二栅极结构的第二半导体器件，其中第二源区和第二漏区存在于第二沟道区的相对侧上。可以存在互连件，其提供第一半导体器件和第二半导体器件之间的电连通，其中第一半导体器件和第二半导体器件中的至少一个被反转。还提供了具有反向卤素掺杂剂分布的结构。

19. 发明授权

US08110465B2 Field effect transistor having an asymmetric gate electrode 有权
标题翻译：具有不对称栅电极的场效应晶体管
公开(公告)号：US08110465B2
公开(公告)日：2012-02-07
申请号：US11830316
申请日：2007-07-30
申请人： Huilong Zhu , Qingqing Liang
发明人： Huilong Zhu , Qingqing Liang
IPC分类号： H01L21/336
CPC分类号： H01L29/42376 , H01L21/28105 , H01L21/28114 , H01L21/28132 , H01L29/4983 , H01L29/512 , H01L29/517 , H01L29/66484 , H01L29/665 , H01L29/66613 , H01L29/7831
摘要： The gate electrode of a metal oxide semiconductor field effect transistor (MOSFET) comprises a source side gate electrode and a drain side gate electrode that abut each other near the middle of the channel. In one embodiment, the source side gate electrode comprises a silicon oxide based gate dielectric and the drain side gate electrode comprises a high-k gate dielectric. The source side gate electrode provides high carrier mobility, while the drain side gate electrode provides good short channel effect and reduced gate leakage. In another embodiment, the source gate electrode and drain gate electrode comprises different high-k gate dielectric stacks and different gate conductor materials, wherein the source side gate electrode has a first work function a quarter band gap away from a band gap edge and the drain side gate electrode has a second work function near the band gap edge.
摘要翻译：金属氧化物半导体场效应晶体管（MOSFET）的栅极包括源极侧栅极和漏极侧栅电极，在栅极中间附近彼此邻接。在一个实施例中，源极侧栅极包括基于氧化硅的栅极电介质，漏极侧栅极包括高k栅极电介质。源极栅电极提供高载流子迁移率，而漏极侧栅电极提供良好的短沟道效应和减小的栅极泄漏。在另一个实施例中，源极栅极和漏极栅电极包括不同的高k栅极电介质堆叠和不同的栅极导体材料，其中源极侧栅电极具有远离带隙边缘的四分之一带隙的第一功函数和漏极侧栅电极在带隙边缘附近具有第二功函数。

20. 发明申请

US20120025319A1 STRUCTURE AND METHOD FOR MAKING METAL SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) WITH ISOLATION LAST PROCESS 失效
标题翻译：用于制造具有隔离最近工艺的金属半导体场效应晶体管（MOSFET）的结构和方法
公开(公告)号：US20120025319A1
公开(公告)日：2012-02-02
申请号：US12844478
申请日：2010-07-27
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/84 , H01L21/76224 , H01L21/76898 , H01L21/823481 , H01L27/1203
摘要： In one embodiment, a method of providing a semiconductor device is provided, in which instead of forming isolation regions before the formation of the semiconductor devices, the isolation regions are formed after the semiconductor devices. In one embodiment, the method includes forming a semiconductor device on a semiconductor substrate. A placeholder dielectric is formed on a portion of a first surface of the substrate adjacent to the semiconductor device. A trench is etched into the substrate from a second surface of the substrate that is opposite the first surface of the substrate, wherein the trench terminates on the placeholder dielectric. The trench is filled with a dielectric material.
摘要翻译：在一个实施例中，提供了提供半导体器件的方法，其中代替在形成半导体器件之前形成隔离区域，在半导体器件之后形成隔离区域。在一个实施例中，该方法包括在半导体衬底上形成半导体器件。在与半导体器件相邻的衬底的第一表面的一部分上形成占位电介质。沟槽从衬底的与衬底的第一表面相对的第二表面蚀刻到衬底中，其中沟槽终止在占位符电介质上。沟槽填充有电介质材料。

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