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11. 发明授权

US08860179B2 Inductive loop formed by through silicon via interconnection 有权
标题翻译：通过硅通过互连形成的感应环路
公开(公告)号：US08860179B2
公开(公告)日：2014-10-14
申请号：US13392208
申请日：2011-05-19
申请人： Pengfei Wang , Qingqing Sun , Wei Zhang
发明人： Pengfei Wang , Qingqing Sun , Wei Zhang
IPC分类号： H01L27/00 , H01L23/522 , H01L23/64 , H01L25/065 , H01L23/00 , H01L23/48
CPC分类号： H01L22/14 , H01L21/76879 , H01L23/481 , H01L23/5227 , H01L23/645 , H01L24/13 , H01L24/94 , H01L25/0657 , H01L28/10 , H01L2224/32145 , H01L2225/06527 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/19042 , H01L2924/00
摘要： The present invention discloses an inductive element formed by through silicon via interconnections. The inductive element formed by means of the special through silicon via interconnection by using through silicon via technology features advantages such as high inductance and density. Moreover, the through silicon via interconnection integrated process forming the inductive element is compatible with the ordinary through silicon interconnection integrated process without any other steps, thus making the process simple and steady. The inductive element using the present invention is applicable to the through silicon via package manufacturing of various chips, especially the package manufacturing of power control chips and radio-frequency chips.
摘要翻译：本发明公开了一种通过硅经由互连形成的电感元件。通过使用硅通过技术的特殊硅通孔互连形成的电感元件具有诸如高电感和密度等优点。此外，形成电感元件的贯通硅通孔互连集成工艺与普通的通过硅互连一体化工艺兼容，无任何其他步骤，从而使工艺简单稳定。使用本发明的电感元件可应用于各种芯片的直通硅封装制造，特别是功率控制芯片和射频芯片的封装制造。

12. 发明申请

US20130078797A1 METHOD FOR MANUFACTURING A COPPER-DIFFUSION BARRIER LAYER USED IN NANO INTEGRATED CIRCUIT 审中-公开
标题翻译：在纳米集成电路中使用的铜扩散阻挡层的制造方法
公开(公告)号：US20130078797A1
公开(公告)日：2013-03-28
申请号：US13528363
申请日：2012-06-20
申请人： Qingqing Sun , Lin Chen , Wen Yang , Pengfei Wang , Wei Zhang
发明人： Qingqing Sun , Lin Chen , Wen Yang , Pengfei Wang , Wei Zhang
IPC分类号： H01L21/768
CPC分类号： H01L21/28562 , C23C16/18 , C23C16/45534 , H01L21/76846 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present invention belongs to the technical field of integrated semiconductor circuits, and relates to a method for manufacturing a copper-diffusion barrier layer. In the present invention, a proper reaction precursor has been selected and the atomic layer deposition (ALD) technology has been adopted to develop Co or Ru on a TaN layer to obtain a diffusion barrier layer used in the interconnection for process nodes no more than 32 nm, which overcomes the insufficiency of the PVD deposition Ta/TaN double-layer structure as the copper-diffusion barrier layer in step coverage and conformity, and also effectively solves various serious problems in the Cu/low-k dual damascene process, such as the generation of voids in grooves and through-holes, and electromigration stability.
摘要翻译：本发明属于集成半导体电路的技术领域，涉及铜扩散阻挡层的制造方法。在本发明中，已经选择了适当的反应前体，并且已经采用原子层沉积（ALD）技术来在TaN层上形成Co或Ru，以获得在不超过32个工艺节点的互连中使用的扩散阻挡层 nm，克服了PVD沉积Ta / TaN双层结构作为铜扩散阻挡层在步骤覆盖和一致性方面的不足，并且有效地解决了Cu / low-k双镶嵌工艺中的各种严重问题，如凹槽和通孔中的空隙的产生以及电迁移稳定性。

13. 发明申请

US20130056848A1 INDUCTIVE LOOP FORMED BY THROUGH SILICON VIA INTERCONNECTION 有权
标题翻译：通过硅互连形成的感应环路
公开(公告)号：US20130056848A1
公开(公告)日：2013-03-07
申请号：US13392208
申请日：2011-05-19
申请人： Pengfei Wang , Qingqing Sun , Wei Zhang
发明人： Pengfei Wang , Qingqing Sun , Wei Zhang
IPC分类号： H01L23/522
CPC分类号： H01L22/14 , H01L21/76879 , H01L23/481 , H01L23/5227 , H01L23/645 , H01L24/13 , H01L24/94 , H01L25/0657 , H01L28/10 , H01L2224/32145 , H01L2225/06527 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/19042 , H01L2924/00
摘要： The present invention discloses an inductive element formed by through silicon via interconnections. The inductive element formed by means of the special through silicon via interconnection by using through silicon via technology features advantages such as high inductance and density. Moreover, the through silicon via interconnection integrated process forming the inductive element is compatible with the ordinary through silicon interconnection integrated process without any other steps, thus making the process simple and steady. The inductive element using the present invention is applicable to the through silicon via package manufacturing of various chips, especially the package manufacturing of power control chips and radio-frequency chips.
摘要翻译：本发明公开了一种通过硅经由互连形成的电感元件。通过使用硅通过技术的特殊硅通孔互连形成的电感元件具有诸如高电感和密度等优点。此外，形成电感元件的贯通硅通孔互连集成工艺与普通的通过硅互连一体化工艺兼容，无任何其他步骤，从而使工艺简单稳定。使用本发明的电感元件可应用于各种芯片的直通硅封装制造，特别是功率控制芯片和射频芯片的封装制造。

14. 发明申请

US20120261744A1 MICROELECTRONIC DEVICE STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：微电子器件结构及其制造方法
公开(公告)号：US20120261744A1
公开(公告)日：2012-10-18
申请号：US13378114
申请日：2010-12-24
申请人： Pengfei Wang , Qingqing Sun , Shijin Ding , Wei Zhang
发明人： Pengfei Wang , Qingqing Sun , Shijin Ding , Wei Zhang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/165 , H01L29/267 , H01L29/4236 , H01L29/513 , H01L29/66356 , H01L29/7391
摘要： The present invention refers to a semiconductor device especially a tunneling filed effect transistor (TFET) using narrow bandgap material as the source electrode material. A Semiconductor device which is a tunneling field effect transistor type semiconductor device, in which the source material is characterized as narrow band-gap material; meanwhile, there is a u-groove channel. The narrow band-gap material results in a raise of driving current and the u-groove channel reduced drain leakage current. The TFET disclosed in to present invention has the advantages of low leakage current, high drive current, and high integration density. The static power consumption is also reduced by using the present invention. The integration density is improved as well.
摘要翻译：本发明涉及使用窄带隙材料作为源电极材料的半导体器件，特别是隧道场效应晶体管（TFET）。作为隧道场效应晶体管型半导体器件的半导体器件，其中源材料被表征为窄带隙材料; 同时，还有一个U槽通道。窄带隙材料导致驱动电流的升高和U沟道沟道减少漏极漏电流。本发明公开的TFET具有漏电流低，驱动电流高，集成度高的优点。通过使用本发明，静电消耗也降低了。整合密度也提高了。

15. 发明授权

US08586432B2 Method for manufacturing vertical-channel tunneling transistor 有权
标题翻译：垂直沟道隧道晶体管的制造方法
公开(公告)号：US08586432B2
公开(公告)日：2013-11-19
申请号：US13537854
申请日：2012-06-29
申请人： Pengfei Wang , Xi Lin , Wei Liu , Qingqing Sun , Wei Zhang
发明人： Pengfei Wang , Xi Lin , Wei Liu , Qingqing Sun , Wei Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/7391 , H01L29/0692 , H01L29/165 , H01L29/66356
摘要： The present invention belongs to the technical field of semiconductors and specifically relates to a method for manufacturing a vertical-channel tunneling transistor. In the present invention, the surrounding gate gate structure improves the control capacity of the gate and the source of narrow band gap material can enhance the device driving current. The method for manufacturing a vertical-channel tunneling transistor put forward by the present invention capable of controlling the channel length precisely features simple process, easy control and reduction of production cost.
摘要翻译：本发明属于半导体技术领域，具体涉及制造垂直沟道隧道晶体管的方法。在本发明中，围绕栅极栅极结构提高了栅极的控制能力，并且窄带隙材料的源极可以增强器件驱动电流。本发明提出的能够精确控制通道长度的垂直通道隧道晶体管的制造方法具有工艺简单，易于控制和降低生产成本。

16. 发明申请

US20130237010A1 METHOD FOR MANUFACTURING A GATE-CONTROL DIODE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：制造门控二极管半导体存储器件的方法
公开(公告)号：US20130237010A1
公开(公告)日：2013-09-12
申请号：US13554531
申请日：2012-07-20
申请人： Pengfei Wang , Xi Lin , Qingqing Sun , Wei Zhang
发明人： Pengfei Wang , Xi Lin , Qingqing Sun , Wei Zhang
IPC分类号： H01L21/336 , H01L21/36
CPC分类号： H01L21/8258 , H01L27/11521 , H01L29/40114 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： The present invention belongs to the technical field of semiconductor device manufacturing, and specifically discloses a method for manufacturing a gate-control diode semiconductor storage device. The present invention manufactures gate-control diode semiconductor memory devices through a low-temperature process featuring a simple process, low manufacturing cost and capacity of manufacturing gate-control diode memory devices with a high driving current and small sub-threshold swing. The method for manufacturing a gate-control diode semiconductor memory device proposed by the present invention is especially applicable to the manufacturing of flat panel displays and phase change memories and memory devices based on flexible substrate.
摘要翻译：本发明属于半导体器件制造技术领域，具体公开了一种栅控二极管半导体存储器件的制造方法。本发明通过低温工艺制造栅极控制二极管半导体存储器件，其特征在于制造具有高驱动电流和小次阈值摆幅的栅极控制二极管存储器件的简单工艺，低制造成本和容量。本发明提出的用于制造栅极控制二极管半导体存储器件的方法特别适用于基于柔性基板的平板显示器和相变存储器以及存储器件的制造。

17. 发明授权

US08486754B1 Method for manufacturing a gate-control diode semiconductor device 有权
标题翻译：栅极控制二极管半导体器件的制造方法
公开(公告)号：US08486754B1
公开(公告)日：2013-07-16
申请号：US13534983
申请日：2012-06-27
申请人： Pengfei Wang , Chengwei Cao , Qingqing Sun , Wei Zhang
发明人： Pengfei Wang , Chengwei Cao , Qingqing Sun , Wei Zhang
IPC分类号： H01L21/00
CPC分类号： H01L29/22 , H01L29/66356 , H01L29/7391
摘要： This invention belongs to semiconductor device manufacturing field and discloses a method for manufacturing a gate-control diode semiconductor device. When the gate voltage is relatively high, the channel under the gate has an n type and the device has a simple gate-control pn junction structure; by way of controlling the effective n-type concentration of the ZnO film through back-gate control, inverting the n-type ZnO into p-type through the gate and using NiO as a p-type semiconductor, an n-p-n-p doping structure is formed. The present invention features capacity of manufacturing gate-control diode devices able to reduce the chip power consumption through the advantages of a high driving current and small sub-threshold swing, is especially applicable to the manufacturing of reading & writing devices having flat panel displays & phase change memory, and semiconductor devices based on flexible substrates.
摘要翻译：本发明属于半导体器件制造领域，并且公开了一种用于制造栅极控制二极管半导体器件的方法。当栅极电压相对较高时，栅极下方的沟道具有n型，器件具有简单的栅极控制pn结结构; 通过背栅控制来控制ZnO膜的有效n型浓度，通过栅极将n型ZnO转换成p型并使用NiO作为p型半导体，形成n-p-n-p掺杂结构。本发明特征在于能够通过高驱动电流和小的次阈值摆幅的优点来制造能够降低芯片功耗的栅极控制二极管器件的能力，特别适用于具有平板显示器的读写装置的制造，相变存储器以及基于柔性基板的半导体器件。

18. 发明申请

US20120309118A1 SILICON WAFER ALIGNMENT METHOD USED IN THROUGH-SILICON-VIA INTERCONNECTION 审中-公开
标题翻译：通过硅 - 互连方式使用的硅波对准方法
公开(公告)号：US20120309118A1
公开(公告)日：2012-12-06
申请号：US13304149
申请日：2011-11-23
申请人： Pengfei Wang , Qingqing Sun , Shijin Ding , Wei Zhang
发明人： Pengfei Wang , Qingqing Sun , Shijin Ding , Wei Zhang
IPC分类号： H01L21/66
CPC分类号： H01L25/0657 , H01L23/481 , H01L25/50 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593
摘要： A method of silicon wafer alignment used in through-silicon-via interconnection for use in the field of high-integrity packaging technology is disclosed. In one aspect, the method includes aligning and calibrating the upper and lower silicon wafers, stacked and interconnected electrically, so as to improve alignment accuracy of silicon wafers and reduce interconnection resistances. In some embodiments, the integrated circuit chip made by the method improves speed and energy performance.
摘要翻译：公开了用于高完整性封装技术领域的硅通孔互连中使用的硅晶片对准方法。在一个方面，该方法包括对准和校准上下硅晶片，电子层叠和互连，以提高硅晶片的对准精度并降低互连电阻。在一些实施例中，通过该方法制造的集成电路芯片提高了速度和能量性能。

19. 发明申请

US20120305880A1 RESISTIVE RANDOM ACCESS MEMORY WITH ELECTRIC-FIELD STRENGTHENED LAYER AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有电场强化层的电阻随机存取存储器及其制造方法
公开(公告)号：US20120305880A1
公开(公告)日：2012-12-06
申请号：US13457035
申请日：2012-04-26
申请人： Wei Zhang , Lin Chen , Peng Zhou , Qingqing Sun , Pengfei Wang
发明人： Wei Zhang , Lin Chen , Peng Zhou , Qingqing Sun , Pengfei Wang
IPC分类号： H01L45/00
CPC分类号： G11C13/0007 , G11C2213/55 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1616
摘要： This invention belongs to the technical field of memories and specifically relates to a resistive random access memory structure with an electric-field strengthened layer and a manufacturing method thereof. The resistive random access memory in the present invention can include a top electrode, a bottom electrode and a composite layer which is placed between the top electrode and the bottom electrode and have a first resistive switching layer and a second resistive switching and electric-field strengthened layer; the second resistive switching and electric-field strengthened layer cab be adjacent to the first resistive switching layer and have a dielectric constant lower than that of the first resistive switching layer. The electric-field distribution in the RRAM unit is adjustable.
摘要翻译：本发明属于存储器的技术领域，具体涉及一种具有电场强化层的电阻随机存取存储器结构及其制造方法。本发明的电阻式随机存取存储器可以包括顶电极，底电极和复合层，它放置在顶电极和底电极之间，并具有第一电阻开关层和第二电阻开关和电场强化层; 第二电阻开关和电场强化层驾驶室与第一电阻式开关层相邻，其介电常数低于第一电阻式开关层的介电常数。 RRAM单元中的电场分布是可调的。

20. 发明授权

US08748267B2 Method for manufacturing a tunneling field effect transistor with a U-shaped channel 有权
标题翻译：用于制造具有U形通道的隧道场效应晶体管的方法
公开(公告)号：US08748267B2
公开(公告)日：2014-06-10
申请号：US13537956
申请日：2012-06-29
申请人： Pengfei Wang , Xi Lin , Wei Liu , Qingqing Sun , Wei Zhang
发明人： Pengfei Wang , Xi Lin , Wei Liu , Qingqing Sun , Wei Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/7391 , H01L29/0657 , H01L29/0895 , H01L29/517 , H01L29/66356
摘要： The present invention belongs to the technical field of semiconductor device manufacturing and specifically relates to a method for manufacturing a tunneling field effect transistor with a U-shaped channel. The U-shaped channel can effectively extend the transistor channel length, restrain the generation of leakage current in the transistor, and decrease the chip power consumption. The method for manufacturing a tunneling field effect transistor with a U-shaped channel put forward in the present invention is capable of realizing an extremely narrow U-shaped channel, overcoming the alignment deviation introduced by photoetching, and improving the chip integration degree.
摘要翻译：本发明属于半导体器件制造的技术领域，具体涉及一种具有U形沟道的隧道效应晶体管的制造方法。 U型通道可以有效地延长晶体管沟道长度，抑制晶体管中漏电流的产生，降低芯片功耗。本发明提出的具有U形通道的隧道场效应晶体管的制造方法能够实现非常窄的U形沟道，克服由光刻引入的取向偏差，提高芯片集成度。

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