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11. 发明申请

WO2014092883A1 SYSTEM AND METHOD FOR ALLOCATING MEMORY TO DISSIMILAR MEMORY DEVICES USING QUALITY OF SERVICE 审中-公开
标题翻译：使用服务质量将存储器分配到DISSIMILAR存储器件的系统和方法
公开(公告)号：WO2014092883A1
公开(公告)日：2014-06-19
申请号：PCT/US2013/068217
申请日：2013-11-04
申请人： QUALCOMM INCORPORATED
发明人： DE, Subrato K. , STEWART, Richard A. , CASCAVAL, Gheorghe Calin , CHUN, Dexter T.
IPC分类号： G06F12/06 , G06F13/16
CPC分类号： G06F12/023 , G06F12/0607 , G06F12/0638 , G06F2212/1044 , G11C7/1072 , Y02D10/13
摘要： Systems and methods are provided for allocating memory to dissimilar memory devices. An exemplary embodiment includes a method for allocating memory to dissimilar memory devices. An interleave bandwidth ratio is determined, which comprises a ratio of bandwidths for two or more dissimilar memory devices. The dissimilar memory devices are interleaved according to the interleave bandwidth ratio to define two or more memory zones having different performance levels. Memory address requests are allocated to the memory zones based on a quality of service (QoS).
摘要翻译：提供了系统和方法，用于将存储器分配给不同的存储器件。示例性实施例包括用于将不同的存储器件分配存储器的方法。确定交织带宽比，其包括两个或多个不同存储器件的带宽比。不同的存储器件根据交织带宽比进行交织以定义具有不同性能级别的两个或多个存储器区域。基于服务质量（QoS）将内存地址请求分配给内存区域。

12. 发明申请

WO2014058831A1 HEAT DISSIPATING APPARATUS FOR FOLDING ELECTRONIC DEVICES 审中-公开
标题翻译：用于折叠电子设备的散热装置
公开(公告)号：WO2014058831A1
公开(公告)日：2014-04-17
申请号：PCT/US2013/063806
申请日：2013-10-08
申请人： QUALCOMM INCORPORATED
发明人： CHIRIAC, Victor A. , CHUN, Dexter T.
IPC分类号： G06F1/20
CPC分类号： H05K7/20436 , G06F1/203 , G06F1/206 , G06F2200/203 , H05K13/04 , Y10T29/49117
摘要： Some implementations provide a folding electronic device that includes a base portion, a cover portion and a coupler. The base portion includes a region configured to generate heat. The cover portion includes a display screen, a heat dissipating component, and a thermally insulating component. The heat dissipating component is coplanar to the display screen. The thermally insulating component is coplanar to the display screen. The thermally insulating component is located between the display screen and the heat dissipating component. The coupler is for thermally coupling the base portion to the cover portion. The coupler includes a first component and a second component. The first component is coupled to the region configured to generate heat. The second component is coupled to the heat dissipating component of the cover portion. The coupler provides a path for transferring heat.
摘要翻译：一些实施方案提供一种折叠电子设备，其包括基部，盖部分和耦合器。基部包括被配置为产生热量的区域。盖部分包括显示屏，散热部件和隔热部件。散热部件与显示屏共面。隔热部件与显示屏共面。隔热部件位于显示屏和散热部件之间。联接器用于将基部热耦合到盖部分。耦合器包括第一部件和第二部件。第一部件耦合到被配置为产生热量的区域。第二部件耦合到盖部分的散热部件。耦合器提供传递热量的路径。

13. 发明申请

WO2013155470A1 HEAT DISSIPATION FEATURES, ELECTRONIC DEVICES INCORPORATING HEAT DISSIPATION FEATURES, AND METHODS OF MAKING HEAT DISSIPATION FEATURES 审中-公开
标题翻译：散热功能，加热散热功能的电子设备及制热散热功能的方法
公开(公告)号：WO2013155470A1
公开(公告)日：2013-10-17
申请号：PCT/US2013/036461
申请日：2013-04-12
申请人： QUALCOMM INCORPORATED
发明人： CHUN, Dexter T. , CHIRIAC, Victor A. , THOMPSON, James H. , MOLLOY, Stephen A.
IPC分类号： H01L23/367
CPC分类号： H01L23/3672 , H01L2924/0002 , H05K7/2039 , H05K7/20409 , Y10T29/49826 , H01L2924/00
摘要： Electronic devices incorporating a heat dissipation feature include an enclosure, and at least one heat-generating component positioned within the enclosure. The heat dissipation feature is sufficiently coupled to the at least one heat-generating component to facilitate conductive heat transfer from the heat-generating component. The heat dissipation feature includes a plurality of protrusions exposed externally to the enclosure. A thermally insulating material may be disposed on at least a tip portion of at least some of the protrusions. The thermally insulating material is selected to provide a touch temperature that is below a predetermined threshold. In some instances, the thermally insulating material can provide such a touch temperature by selecting the material to include properties for thermal conductivity (k), density (ρ), and specific heat (C p ) such that the product of k*ρ*C p results in a value less than a product of k*ρ*C p for human skin.
摘要翻译：结合散热特征的电子设备包括外壳，以及至少一个定位在外壳内的发热元件。散热特征与至少一个发热部件充分耦合，以便于来自发热部件的传导热传递。散热特征包括暴露在外壳外部的多个突起。绝热材料可以设置在至少一些突起的至少一个尖端部分上。选择绝热材料以提供低于预定阈值的触摸温度。在某些情况下，绝热材料可以通过选择材料来提供这样的触摸温度，以包括热导率（k），密度（rho）和比热（Cp）的性质，使得k * rho * Cp的结果结果其值小于人皮肤的k * rho * Cp的乘积。

14. 发明授权

EP2915019B1 SYSTEM AND METHOD FOR DYNAMIC MEMORY POWER MANAGEMENT 有权
标题翻译：系统和方法动态内存性能管理
公开(公告)号：EP2915019B1
公开(公告)日：2017-04-19
申请号：EP13745935.0
申请日：2013-07-19
申请人： Qualcomm Incorporated
发明人： LO, Haw-Jing , TAHA, Ali , CHUN, Dexter T.
IPC分类号： G06F1/32
CPC分类号： G06F1/3225 , G06F1/3275 , G06F12/023 , Y02D10/14 , Y02D50/20
摘要： Various embodiments of methods and systems for hardware (“HW”) based dynamic memory management in a portable computing device (“PCD”) are disclosed. One exemplary method includes generating a lookup table (“LUT”) to track each memory page located across multiple portions of a volatile memory. The records in the LUT are updated to keep track of data locations. When the PCD enters a sleep state to conserve energy, the LUT may be queried to determine which specific memory pages in a first portion of volatile memory (e.g., an upper bank) contain data content and which pages in a second portion of volatile memory (e.g., a lower bank) are available for receipt of content. Based on the query, the location of the data in the memory pages of the upper bank is known and can be quickly migrated to memory pages in the lower bank which are identified for receipt of the data.

15. 发明公开

EP2995051A2 SYNCHRONOUS DATA-LINK THROUGHPUT ENHANCEMENT TECHNIQUE BASED ON DATA SIGNAL DUTY-CYCLE AND PHASE MODULATION/DEMODULATION 有权
标题翻译：基于DATENSIGNALTASTVERHÄLTNIS-和相位调制/解调同步数据CONNECTION流率的增大
公开(公告)号：EP2995051A2
公开(公告)日：2016-03-16
申请号：EP14727128.2
申请日：2014-04-23
申请人： Qualcomm Incorporated
发明人： MISHRA, Lalan J. , CHUN, Dexter T. , DATTA, Animesh
IPC分类号： H04L25/49
CPC分类号： G06F13/42 , G06F13/1689 , G06F13/4234 , G06F13/4243 , G06F13/4282 , G11C7/10 , G11C7/222 , H04L7/0008 , H04L7/0037 , H04L25/4902
摘要： A synchronous data-link throughput enhancement technique based on data signal duty-cycle and phase modulation demodulation is disclosed. A method includes receiving multiple bits to be transmitted, encoding the multiple bits to generate a multi-bit signal that represents the multiple bits, and transmitting, via a synchronous interface, the multi-bit signal during a time period that corresponds to one-half of a cycle of a synchronization signal.

16. 发明授权

EP2965217B1 METHOD AND APPARATUS FOR SELECTIVELY TERMINATING SIGNALS ON A BIDIRECTIONAL BUS BASED ON BUS SPEED 有权
标题翻译： VEFAHREN和设备在双向总线基于CAN总线高速信号选择性终止
公开(公告)号：EP2965217B1
公开(公告)日：2017-04-19
申请号：EP14716075.8
申请日：2014-03-06
申请人： Qualcomm Incorporated
发明人： CHUN, Dexter T. , SETHI, Sumeet S. , EATON, John D. , CUPPU, Vinodh R. , ARORA, Vikram , SRINIVAS, Vaishnav , MUNEER, Muhammad A. , BERK, Isaac D.
IPC分类号： H03K19/0175 , H04L25/02
CPC分类号： H04L25/0278 , G06F13/4086 , H03K19/0005 , H03K19/017545 , Y02D10/14 , Y02D10/151
摘要： A method of controlling signal termination includes providing first logic for selectively terminating signals received at a first device on a bidirectional data bus, providing second logic for selectively terminating signals received at a second device on the bidirectional data bus, sending first signals from the first device to the second device on the bidirectional data bus at a first speed, stopping the sending of the first signals, after stopping the sending of the first signals, enabling the second logic and shifting a reference voltage of the second device from a first level to a second level, after enabling the second logic at the second device, sending second signals from the first device to the second device on the bidirectional data bus at a higher speed, and controlling the first logic based on a speed of signals received at the first device on the bidirectional data bus.
摘要翻译：控制信号终端的方法，包括：提供第一逻辑，用于选择性地终止于一个双向数据总线上的第一设备接收到的信号，用于选择性地终止于所述双向数据总线上的第二设备接收到的信号而提供第二逻辑，从所述第一设备发送第一信号以第一速度的双向数据总线上的第二装置，停止所述第一信号的发送，停止所述第一信号的发送之后，使所述第二逻辑和从第一电平移位所述第二装置的参考电压施加到第二电平，使所述第二逻辑在第二设备处，以更高的速度在双向数据总线上从所述第一设备发送第二信号到所述第二装置，并基于信号的速度控制第一逻辑之后在第一设备处接收到的在双向数据总线。

17. 发明公开

EP3108367A1 KERNEL MASKING OF DRAM DEFECTS 审中-公开
标题翻译：内核MASK DRAM缺损
公开(公告)号：EP3108367A1
公开(公告)日：2016-12-28
申请号：EP15708993.9
申请日：2015-02-20
申请人： Qualcomm Incorporated
发明人： CHUN, Dexter T. , LI, Yanru , DONG, Xiangyu , SUH, Jungwon , KIM, Jung Pill , SRIRAMAGIRI, Deepti Vijayalakshmi
IPC分类号： G06F11/10 , G06F12/00
CPC分类号： G11C29/44 , G06F11/1048 , G06F11/1076 , G06F11/2053 , G06F12/0246 , G06F2212/7209 , G11C2029/4402
摘要： Systems, methods, and computer programs are disclosed for kernel masking dynamic random access memory (DRAM) defects. One such method comprises: detecting and correcting a single-bit error associated with a physical address in a dynamic random access memory (DRAM); receiving error data associated with the physical address from the DRAM; storing the received error data in a failed address table located in a non-volatile memory; and retiring a kernel page corresponding to the physical address if a number of errors associated with the physical address exceeds an error count threshold.

18. 发明授权

EP2856466B1 INTER-CHIP MEMORY INTERFACE STRUCTURE 有权
公开(公告)号：EP2856466B1
公开(公告)日：2018-10-24
申请号：EP13729562.2
申请日：2013-05-31
申请人： Qualcomm Incorporated
发明人： SUH, Jungwon , CHUN, Dexter T.
IPC分类号： G11C7/02 , G11C7/22 , H01L25/065 , G11C5/04 , G11C5/06 , H01L25/10
CPC分类号： G11C5/06 , G11C5/04 , G11C5/063 , G11C7/02 , G11C7/222 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/48227 , H01L2225/0651 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311
摘要： In an embodiment, a stacked package-on-package system has a memory die and a logic die. The memory die comprises a first memory and a second memory, each operated independently of the other, and each having an inter-chip interface electrically connected to the logic die. The logic die has two independent clock sources, one to provide a first clock signal to the first memory, and the other clock source to provide a second clock signal to the second memory.

19. 发明公开

EP2965217A1 METHOD AND APPARATUS FOR SELECTIVELY TERMINATING SIGNALS ON A BIDIRECTIONAL BUS BASED ON BUS SPEED 有权
标题翻译： VEFAHREN和设备在双向总线基于CAN总线高速信号选择性终止
公开(公告)号：EP2965217A1
公开(公告)日：2016-01-13
申请号：EP14716075.8
申请日：2014-03-06
申请人： Qualcomm Incorporated
发明人： CHUN, Dexter T. , SETHI, Sumeet S. , EATON, John D. , CUPPU, Vinodh R. , ARORA, Vikram , SRINIVAS, Vaishnav , MUNEER, Muhammad A. , BERK, Isaac D.
IPC分类号： G06F13/40
CPC分类号： H04L25/0278 , G06F13/4086 , H03K19/0005 , H03K19/017545 , Y02D10/14 , Y02D10/151
摘要： A method of controlling signal termination includes providing first logic for selectively terminating signals received at a first device on a bidirectional data bus, providing second logic for selectively terminating signals received at a second device on the bidirectional data bus, sending first signals from the first device to the second device on the bidirectional data bus at a first speed, stopping the sending of the first signals, after stopping the sending of the first signals, enabling the second logic and shifting a reference voltage of the second device from a first level to a second level, after enabling the second logic at the second device, sending second signals from the first device to the second device on the bidirectional data bus at a higher speed, and controlling the first logic based on a speed of signals received at the first device on the bidirectional data bus.

20. 发明公开

EP2929447A1 SYSTEM AND METHOD FOR DYNAMICALLY ALLOCATING MEMORY IN A MEMORY SUBSYSTEM HAVING ASYMMETRIC MEMORY COMPONENTS 有权
标题翻译：系统和方法在一家商店的动态内存分配，法制与非对称存储器组件
公开(公告)号：EP2929447A1
公开(公告)日：2015-10-14
申请号：EP13803313.9
申请日：2013-11-04
申请人： Qualcomm Incorporated
发明人： STEWART, Richard A. , CHUN, Dexter T.
IPC分类号： G06F13/16 , G06F12/06
CPC分类号： G06F12/0607 , G06F13/1647
摘要： Systems and methods are provided for dynamically allocating a memory subsystem. An exemplary embodiment comprises a method for dynamically allocating a memory subsystem in a portable computing device. The method involves fully interleaving a first portion of a memory subsystem having memory components with asymmetric memory capacities. A second remaining portion of the memory subsystem is partial interleaved according to an interleave bandwidth ratio. The first portion of the memory subsystem is allocated to one or more high-performance memory clients. The second remaining portion is allocated to one or more relatively lower-performance memory clients.

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