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11. 发明授权

US06496740B1 Transfer controller with hub and ports architecture 有权
标题翻译：具有集线器和端口架构的传输控制器
公开(公告)号：US06496740B1
公开(公告)日：2002-12-17
申请号：US09543870
申请日：2000-04-06
申请人： Iain Robertson , David Hoyle
发明人： Iain Robertson , David Hoyle
IPC分类号： G05B1101
CPC分类号： G06F15/17
摘要： The transfer controller with hub and ports (TCHP) performs the task of communication throughout an entire system in a centralized function. A single hub (435) tied to multiple ports (440, 447, 450, 452) by a central pipeline is the medium for all data communications among DSP clusters (455), external devices, and external memory. A transfer request queue manager (420) receives, prioritizes and queues data transfer requests. Each data port includes an identically configured interior interface (901) connected to the hub (435) and an exterior interface (902) configured for a target external memory/device connected to the port. The interior interfaces of all ports are clocked at a common internal frequency, while the exterior interfaces are clocked at the frequency of the external memory/device connected to the port.
摘要翻译：具有集线器和端口（TCHP）的传输控制器以集中的功能在整个系统中执行通信任务。通过中央管线连接到多个端口（440,447,450,452）的单个集线器（435）是用于DSP集群（455），外部设备和外部存储器之间的所有数据通信的介质。传送请求队列管理器（420）接收数据传输请求的优先次序和队列。每个数据端口包括连接到集线器（435）的相同配置的内部接口（901）和被配置用于连接到端口的目标外部存储器/设备的外部接口（902）。所有端口的内部接口以公共内部频率计时，而外部接口按照连接到端口的外部存储器/设备的频率进行计时。

12. 发明申请

US20050188182A1 Microprocessor having a set of byte intermingling instructions 审中-公开
标题翻译：微处理器具有一组字节混合指令
公开(公告)号：US20050188182A1
公开(公告)日：2005-08-25
申请号：US11114549
申请日：2005-04-26
申请人： David Hoyle , Vishal Markandey , Lewis Nardini
发明人： David Hoyle , Vishal Markandey , Lewis Nardini
IPC分类号： G06F15/00
CPC分类号： G06F9/30032 , G06F9/30036 , G06F9/3828 , G06F9/3853 , G06F9/3891
摘要： A data processing system is provided with a digital signal processor that has a set of instructions for intermingling byte fields selected from a selected pair of source operands and storing the ordered result in a selected destination register. A first 32-bit operand is treated as four 8-bit fields while a second 32-bit operand is treated as four 8-bit fields. Intermingling circuitry is operable to form an ordered result in accordance with each one of the set of byte intermingling instructions. An instruction is provided that performs a shift right and byte merge operation. Another instruction is provided that performs a shift left and byte merge operation. Another instruction is provided that perform a byte swap operation. A set of instructions are provided that perform various byte packing and unpacking operations.
摘要翻译：数据处理系统具有数字信号处理器，该数字信号处理器具有一组指令，用于混合从所选择的一对源操作数中选择的字节字段，并将所选择的结果存储在所选择的目标寄存器中。第一个32位操作数被视为四个8位字段，而第二个32位操作数被视为四个8位字段。混合电路可操作以根据该组字节混合指令中的每一个形成有序结果。提供执行右移和字节合并操作的指令。另外提供了执行左移和字节合并操作的指令。提供另一个执行字节交换操作的指令。提供了一组执行各种字节打包和解包操作的指令。

13. 发明授权

US06766440B1 Microprocessor with conditional cross path stall to minimize CPU cycle time length 有权
标题翻译：具有条件交叉路径失速的微处理器，以最小化CPU周期时间长度
公开(公告)号：US06766440B1
公开(公告)日：2004-07-20
申请号：US09702453
申请日：2000-10-31
申请人： Donald E. Steiss , David Hoyle
发明人： Donald E. Steiss , David Hoyle
IPC分类号： G06F930
CPC分类号： G06F9/3885 , G06F9/3824 , G06F9/3828 , G06F9/3891
摘要： A digital system is provided that includes a central processing unit (CPU) that has an instruction execution pipeline with a plurality of functional units for executing instructions in a sequence of CPU cycles. The execution units are clustered into two or more groups. Cross-path circuitry is provided such that results from any execution unit in one execution unit cluster can be supplied to execution units in another cluster. A cross-path stall is conditionally inserted to stall all of the functional groups when one execution unit cluster requires an operand from another cluster on a given CPU cycle and the execution unit that is producing that operand completes the computation of that operand on an immediately preceding CPU cycle.
摘要翻译：提供了一种数字系统，其包括具有指令执行流水线的中央处理单元（CPU），所述指令执行流水线具有用于以CPU周期的顺序执行指令的多个功能单元。执行单元被分组成两个或更多个组。提供交叉路径电路，使得可以将一个执行单元集群中的任何执行单元的结果提供给另一个集群中的执行单元。当一个执行单元集群在给定的CPU周期中需要来自另一个集群的操作数时，有条件地插入一个跨路径停顿来停止所有的功能组，并且正在产生该操作数的执行单元完成该操作数的计算。 CPU周期。

14. 发明授权

US06760742B1 Multi-dimensional galois field multiplier 有权
标题翻译：多维伽罗瓦域倍增器
公开(公告)号：US06760742B1
公开(公告)日：2004-07-06
申请号：US09507187
申请日：2000-02-18
申请人： David Hoyle
发明人： David Hoyle
IPC分类号： G06F1500
CPC分类号： G06F7/724 , H03M13/158
摘要： An implementation of a multi-dimensional Galois field multiplier and a method of Galois field multi-dimensional multiplication which are able to support many communication standards having various symbol sizes, different GFs, and different primitive polynomials, in a cost-efficient manner is disclosed. The key to allow a single implementation to perform for all different GF sizes is to align the input data such that the Galois field symbols of the operands are aligned to the left most significant bit (MSB) position of the input data field. Similarly, the primitive polynomial used to create a selected Galois field is aligned to the left MSB position. A polynomial multiply is performed. The product polynomial is then conditionally divided by the primitive polynomial starting with the most significant bit, the condition being if the left most bit of the product is a 1. In other words, if the product polynomial has an MSB of 1, then divide the product with the primitive polynomial. Perform this step until the MSB is 0. In addition, for fields smaller than a maximum size Galois field, the sequence of conditional divisions is further conditioned with a predetermined mask in dependence upon the size of the GF. The resultant product is aligned to the left MSB.
摘要翻译：公开了能够以成本有效的方式支持具有各种符号大小，不同GF和不同原始多项式的许多通信标准的多维Galois域乘法器的实现和Galois域多维乘法的方法。允许单个实现对于所有不同GF大小执行的关键是对齐输入数据，使得操作数的Galois字段符号与输入数据字段的最高有效位（MSB）位置对齐。类似地，用于创建所选伽罗瓦域的原始多项式与左MSB位置对齐。执行多项式乘法。然后，乘积多项式由最高有效位开始的原始多项式有条件地划分，条件是产品的最左位为1。换句话说，如果乘积多项式的MSB为1，则将产品与原始多项式。执行该步骤直到MSB为0.另外，对于小于最大尺寸伽罗瓦域的场，根据GF的大小，利用预定掩码进一步调节条件划分序列。所得产物与左MSB对齐。

15. 发明授权

US06745319B1 Microprocessor with instructions for shuffling and dealing data 有权
标题翻译：具有混洗和交易数据指令的微处理器
公开(公告)号：US06745319B1
公开(公告)日：2004-06-01
申请号：US09702452
申请日：2000-10-31
申请人： Keith Balmer , David Hoyle , Lewis Nardini
发明人： Keith Balmer , David Hoyle , Lewis Nardini
IPC分类号： G06F9305
CPC分类号： G06F9/3891 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30072 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/3828 , G06F9/3885
摘要： A data processing system is provided with a digital signal processor (DSP) which has a shuffle instruction for shuffling a source operand (600) and storing the shuffled result in a selected destination register (610). A shuffled result is formed by interleaving bits from a first source operand portion with bits from a second operand portion. A de-interleave and pack (DEAL) instruction is provided for de-interleaving a source operand. The shuffle instruction and the DEAL instruction have an exactly inverse effect. The DSP includes swizzle circuitry that performs interleaving or de-interleaving in a single execution phase.
摘要翻译：数据处理系统具有数字信号处理器（DSP），数字信号处理器（DSP）具有用于混洗源操作数（600）并将洗牌结果存储在所选目的地寄存器（610）中的混洗指令。通过从来自第二操作数部分的位与第一源操作数部分交织比特来形成混洗结果。提供去交错和包（DEAL）指令用于解交织源操作数。随机播放指令和DEAL指令具有完全相反的效果。 DSP包括在单个执行阶段执行交织或解交织的交换电路。

16. 发明授权

US06711602B1 Data processor with flexible multiply unit 有权
标题翻译：数据处理器具有灵活的乘法单元
公开(公告)号：US06711602B1
公开(公告)日：2004-03-23
申请号：US09703093
申请日：2000-10-31
申请人： Amarjit Singh Bhandal , Keith Balmer , David Hoyle , Karl M. Guttag , Zahid Hussain
发明人： Amarjit Singh Bhandal , Keith Balmer , David Hoyle , Karl M. Guttag , Zahid Hussain
IPC分类号： G06F752
CPC分类号： G06F9/30014 , G06F9/3853
摘要： An embodiment of the invention includes a pair of parallel 16×16 multipliers each with two 32-bit inputs and one 32-bit output. There are options to allow input halfword and byte selection for four independent 8×8 or two independent 16×16 multiplications, real and imaginary parts of comple×multiplication, pairs of partial sums for 32×32 multiplication, and partial sums for 16×32 multiplication. There are options to allow internal hardwired routing of each multiplier unit results to achieve partial-sum shifting as required to support above options. There is a redundant digit arithmetic adder before final outputs to support additions for partial sum accumulation, complex multiplication vector accumulation and general accumulation for FIRs/IIRs—giving MAC unit functionality. There are options controlled using bit fields in a control register passed to the multiplier unit as an operand. There are also options to generate all of the products needed for complex multiplication.
摘要翻译：本发明的实施例包括一对并行的16×16乘法器，每个乘法器具有两个32位输入和一个32位输出。有四种独立的8x8或两个独立的16x16乘法输入半字和字节选择的选项，复乘的实部和虚部，32x32乘法的部分和对，以及16x32乘法的部分和。有一些选项允许每个乘法器单元的内部连线布线结果实现部分和位移动，以支持上述选项。在最终输出之前有一个冗余数字运算加法器，以支持部分和累加的加法，复数乘法向量累加和FIR / IIR的一般累加 - 提供MAC单元功能。使用控制寄存器中的位域作为操作数传递给乘法器单元进行控制的选项。还可以选择生成复杂乘法所需的所有产品。

17. 发明授权

US06453405B1 Microprocessor with non-aligned circular addressing 有权
标题翻译：具有非对齐循环寻址的微处理器
公开(公告)号：US06453405B1
公开(公告)日：2002-09-17
申请号：US09703179
申请日：2000-10-31
申请人： David Hoyle , Joseph R. Zbiciak
发明人： David Hoyle , Joseph R. Zbiciak
IPC分类号： G06F1200
CPC分类号： G06F9/3891 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/30145 , G06F9/30167 , G06F9/3552 , G06F9/3555 , G06F9/3824 , G06F9/3828 , G06F9/3853 , G06F9/3885
摘要： A data processing system having a central processing unit (CPU) with address generation circuitry for accessing a circular buffer region in a non-aligned manner is provided. The CPU has an instruction set architecture that is optimized for intensive numeric algorithm processing. The CPU has dual load/store units connected to dual memory ports of a memory controller. The CPU can execute two aligned data transfers each having a length of one byte, two bytes, four bytes, or eight bytes in parallel by executing two load/store instructions. The CPU can also execute a single non-aligned data transfer having a length of four bytes or eight bytes by executing a non-aligned load/store instruction that utilizes both memory ports. A data transfer address for each load/store instruction is formed by fetching the instruction (600), decoding the instruction (610) to determine instruction type, transfer data size, addressing mode and scaling selection. For a non-aligned instruction, after selectively scaling (620) an offset provided by the instruction and combining the selectively scaled offset with a base address value the resultant address is then augmented (640) by a line size associated with the instruction. For circular addressing mode, both the resultant address and the augmented address are bounded (650, 651) to stay within the circular buffer region and two aligned data items are accessed in parallel (652, 653) and a non-aligned data item is extracted (654) from the two aligned data items, such that the non-aligned data item wraps around the boundary of the circular buffer region.
摘要翻译：提供一种具有中央处理单元（CPU）的数据处理系统，其具有用于以非对准方式访问循环缓冲区域的地址产生电路。 CPU具有针对密集数值算法处理进行了优化的指令集体系结构。 CPU具有连接到存储器控制器的双存储器端口的双重加载/存储单元。 CPU可以通过执行两个加载/存储指令来并行执行两个对齐的数据传输，每个数据传输具有一个字节，两个字节，四个字节或八个字节的长度。 CPU还可以通过执行利用两个存储器端口的不对齐的加载/存储指令来执行具有四字节或八字节长度的单个非对齐数据传输。通过取指令（600），解码指令（610）来确定指令类型，传输数据大小，寻址模式和缩放选择，形成每个加载/存储指令的数据传输地址。对于非对准指令，在选择性地缩放（620）由指令提供的偏移量并且将选择性缩放的偏移量与基址值组合之后，然后将所得到的地址通过与该指令相关联的行大小增大（640）。对于循环寻址模式，结果地址和扩充地址都被界定（650,651）以保持在循环缓冲区内，并且并行访问两个对齐的数据项（652,653），并且提取不对齐的数据项（654），使得不对齐的数据项围绕循环缓冲区的边界卷绕。

18. 发明申请

US20080016327A1 Register File Bypass With Optional Results Storage and Separate Predication Register File in a VLIW Processor 有权
标题翻译：在VLIW处理器中使用可选结果注册文件旁路存储和分离预测寄存器文件
公开(公告)号：US20080016327A1
公开(公告)日：2008-01-17
申请号：US11769191
申请日：2007-06-27
申请人： Amitabh Menon , David Hoyle
发明人： Amitabh Menon , David Hoyle
IPC分类号： G06F9/30
CPC分类号： G06F9/3885 , G06F9/30032 , G06F9/30072 , G06F9/30109 , G06F9/3012 , G06F9/3013 , G06F9/3016 , G06F9/30167 , G06F9/3828 , G06F9/3891
摘要： This invention makes each register bypass forwarding register explicitly addressable in software. Software chooses whether to access the forwarding register immediately eliminating the need for complex automatic detection. Each instruction executes and always writes its result into the forwarding register. Writing this data into the register file in the next cycle is optional as selected by the destination register file number. This invention separates registers storing predication data from the register file. This separation removes the speed problem by enabling scheduling of the predication computation out of the critical path.
摘要翻译：本发明使每个寄存器旁路转发寄存器能够在软件中明确地寻址。软件选择是否立即访问转发寄存器，无需复杂的自动检测。每个指令执行并且始终将其结果写入转发寄存器。在下一个周期中将该数据写入寄存器文件是可选的，由目标寄存器文件编号选择。本发明分离从寄存器文件存储预测数据的寄存器。这种分离通过使关键路径中的预测计算能够调度来消除速度问题。

19. 发明申请

US20070283231A1 Multi-Standard Scramble Code Generation Using Galois Field Arithmetic 审中-公开
标题翻译：使用伽罗瓦域算法的多标准扰码生成
公开(公告)号：US20070283231A1
公开(公告)日：2007-12-06
申请号：US11745690
申请日：2007-05-08
申请人： David Hoyle
发明人： David Hoyle
IPC分类号： H03M13/00
CPC分类号： G06F7/584
摘要： This invention is a method of using a Fibonacci form linear feedback shift register. The Fibonacci form linear feedback shift register having an initial state and a set of taps is converter into an equivalent Galois form linear feedback shift register. The Galois form linear feedback shift register state is altered employing Galois field arithmetic. The altered Galois form linear feedback shift register is converted into an equivalent altered Fibonacci form linear feedback shift register. A pseudo-random number produced by the altered Fibonacci form linear feedback shift register is used, for example in a scramble code.
摘要翻译：本发明是一种使用斐波纳契形式线性反馈移位寄存器的方法。具有初始状态和一组抽头的斐波纳契形式的线性反馈移位寄存器被转换成为等效的伽罗瓦形式的线性反馈移位寄存器。伽罗瓦形式线性反馈移位寄存器状态被改变采用伽罗瓦域算术。改变的Galois形式的线性反馈移位寄存器被转换成等效的改变的斐波纳契形式的线性反馈移位寄存器。使用由改变的斐波纳契形式线性反馈移位寄存器产生的伪随机数，例如在扰码中。

20. 发明授权

US07047284B1 Transfer request bus node for transfer controller with hub and ports 有权
标题翻译：用于具有集线器和端口的传输控制器的传输请求总线节点
公开(公告)号：US07047284B1
公开(公告)日：2006-05-16
申请号：US09713440
申请日：2000-11-15
申请人： Sanjive Agarwala , David A. Comisky , Charles L. Fuoco , Iain Robertson , David Hoyle , John Keay , Keith Balmer , Amarjit S. Bhandal , Christopher L. Mobley
发明人： Sanjive Agarwala , David A. Comisky , Charles L. Fuoco , Iain Robertson , David Hoyle , John Keay , Keith Balmer , Amarjit S. Bhandal , Christopher L. Mobley
IPC分类号： G06F15/177
CPC分类号： G06F13/37
摘要： A transfer request bus and transfer request bus node is described which is suitable for use in a data transfer controller processing multiple concurrent transfer requests despite the attendant collisions which result when conflicting transfer requests occur. Transfer requests are passed from an upstream transfer request node to downstream transfer request node and then to a transfer request controller with queue. At each node a local transfer request can also be inserted to be passed on to the transfer controller queue. Collisions at each transfer request node are resolved using a token passing scheme wherein a transfer request node possessing the token allows a local request to be inserted in preference to the upstream request.
摘要翻译：描述了转移请求总线和传送请求总线节点，其适用于处理多个并发转移请求的数据传输控制器，尽管在发生冲突的转移请求时产生了伴随的冲突。传输请求从上游传输请求节点传递到下游传输请求节点，然后传送到具有队列的传输请求控制器。在每个节点处，也可以插入本地传输请求以传递到传输控制器队列。使用令牌传递方案来解决每个传送请求节点处的冲突，其中拥有令牌的传送请求节点允许优先于上游请求插入本地请求。

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