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11. 发明授权

US07573761B2 Integrated electrical module with regular and redundant elements 失效
标题翻译：具有常规和冗余元件的集成电气模块
公开(公告)号：US07573761B2
公开(公告)日：2009-08-11
申请号：US11756468
申请日：2007-05-31
申请人： Peter Beer
发明人： Peter Beer
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/808 , G11C29/806 , G11C29/812
摘要： An integrated electrical module has a set of regular elements and a set of redundant elements, the elements being split over at least two blocks which are individually selectable by an input address and respectively containing regular elements and redundant elements. The integrated electrical module further has two repair circuits, each repair circuit being associated to a block, the two repair circuits being conditioned as a pair for a partner mode of operation, in which the addressing of an element from a first half-group of regular elements in the first block is diverted to a first half-group of elements in the second block and the addressing of an element from a second half-group of regular elements in the first block is diverted to a second half-group of elements in the second block.
摘要翻译：集成电气模块具有一组常规元件和一组冗余元件，这些元件在至少两个块上分开，这些块可由输入地址单独选择并分别包含常规元件和冗余元件。集成电气模块还具有两个修复电路，每个修复电路与块相关联，所述两个修复电路被调节成对，用于伙伴操作模式，其中，来自第一半组正常第一块中的元素被转移到第二块中的元素的第一半组，并且来自第一块中的第二半组的正则元素的元素的寻址被转移到第一块中的元素的第二半组第二块。

12. 发明授权

US07231562B2 Memory module, test system and method for testing one or a plurality of memory modules 有权
标题翻译：用于测试一个或多个存储器模块的存储器模块，测试系统和方法
公开(公告)号：US07231562B2
公开(公告)日：2007-06-12
申请号：US10754455
申请日：2004-01-09
申请人： Carsten Ohlhoff , Peter Beer
发明人： Carsten Ohlhoff , Peter Beer
IPC分类号： G01R31/28
CPC分类号： G11C29/40 , G11C2029/0405 , G11C2029/1208 , G11C2029/2602
摘要： The invention relates to an integrated memory module having a memory unit and a self-test circuit, the self-test circuit being embodied in such a way as to make available test data and test addresses for testing memory areas in the memory unit and to generate defect data depending on the detection of a defect, a test circuit being provided in order to receive defect data from one or a plurality of connectable memory modules to be detected, the test circuit being configured in such a way as to store the received defect data depending on addresses assigned thereto in the memory unit.
摘要翻译：本发明涉及一种具有存储器单元和自检电路的集成存储器模块，该自检电路以这样一种方式实现：提供用于测试存储器单元中的存储器区域的测试数据和测试地址，并产生缺陷数据取决于缺陷的检测，提供测试电路以便从要被检测的一个或多个可连接存储器模块接收缺陷数据，该测试电路被配置成存储接收的缺陷数据取决于在存储器单元中分配给其的地址。

13. 发明授权

US07159156B2 Memory chip with test logic taking into consideration the address of a redundant word line and method for testing a memory chip 有权
标题翻译：具有测试逻辑的存储器芯片考虑了冗余字线的地址以及用于测试存储器芯片的方法
公开(公告)号：US07159156B2
公开(公告)日：2007-01-02
申请号：US10610186
申请日：2003-06-30
申请人： Peter Beer
发明人： Peter Beer
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/24 , G11C11/401 , G11C29/36 , G11C2029/0405 , G11C2029/1806
摘要： A memory chip includes an on-chip data generator, a scrambler unit for checking the correct operability of the memory cells, a repair unit, and redundant word lines that, in the case of a memory cell recognized as defective, are used instead of the word line regularly activated. The scrambler unit is connected to the repair unit and, thus, receives from the repair unit information on whether the redundant word line replacing a defective word line drives transistors of memory cells that can be connected to true bit lines or to complementary bit lines. As such, the scrambler unit can take the information as to whether a true bit line or a complementary bit line is driven through the spare word line into consideration when performing the test procedure. This provides for a more efficient performance of the test procedure. Also provided is a method for testing memory cells.
摘要翻译：存储器芯片包括片上数据生成器，用于检查存储单元的正确可操作性的加扰单元，修复单元和冗余字线，在使用被识别为有缺陷的存储单元的情况下，代替字线定期激活。加扰器单元连接到修复单元，从而从修复单元接收关于替换缺陷字线的冗余字线是否驱动可连接到真位线或互补位线的存储器单元的晶体管的信息。因此，加扰器单元可以在执行测试过程时考虑到通过备用字线驱动真实位线或互补位线的信息。这提供了更有效的测试过程的性能。还提供了一种用于测试存储器单元的方法。

14. 发明授权

US07137049B2 Method and apparatus for masking known fails during memory tests readouts 有权
公开(公告)号：US07137049B2
公开(公告)日：2006-11-14
申请号：US10425224
申请日：2003-04-29
申请人： Jochen Hoffmann , Carsten Ohlhoff , Peter Beer
发明人： Jochen Hoffmann , Carsten Ohlhoff , Peter Beer
IPC分类号： G11C29/00
CPC分类号： G11C29/24
摘要： Embodiments of the present invention generally provide methods and apparatus for testing memory devices having normal memory elements and redundant memory elements. During a front-end testing procedure, normal memory elements that are found to be defective are replaced by redundant memory elements. During the front-end test, redundant memory elements that are found to be defective may be marked as defective by blowing associated mask fuses. During a back-end testing procedure, the results of testing a normal memory element may be masked (e.g., forced to a passing result) if the normal memory element has been replaced by a redundant memory element. Similarly, the results of testing a redundant memory element may be masked if the redundant memory element was previously found to be defective, as indicated by an associated mark fuse. By masking the test results for memory elements (normal and redundant) that have been previously found defective, the memory elements may be tested in the same manner during front-end and back-end testing.

15. 发明申请

US20060129879A1 System and method for monitoring the status and progress of a technical process or of a technical project 审中-公开
标题翻译：用于监测技术过程或技术项目状态和进度的系统和方法
公开(公告)号：US20060129879A1
公开(公告)日：2006-06-15
申请号：US11271927
申请日：2005-11-14
申请人： Richard Alznauer , Andreas Liefeldt , Georg Gutermuth , Stefan Basenach , Peter Beer
发明人： Richard Alznauer , Andreas Liefeldt , Georg Gutermuth , Stefan Basenach , Peter Beer
IPC分类号： G06F11/00
CPC分类号： G06Q10/10
摘要： The invention relates to a system and method for automatically and systematically analysing and monitoring operations of a technical process (10) for the status and progress monitoring of the technical process (10), based on data (D) which characterizes the current state of the process (10), in which check routines (C) for describing and implementing check criteria for evaluating the data (D) are defined and stored in a first module (20). The first module (20) interacts with a second module (30) which compiles the check routines (C) stored in the first module (D) to form hierarchically structured check points (CP). The check routines (C) which are stored in the hierarchically structured check points (CP) check, by assigning the data (D). made available by the process (10) and by taking into account the results of the check routines (C) carried out by the subordinate check points (CP), whether the check criteria stored in the check routines (C) apply, carry out automatic evaluation of the check routines (C) and generate information about the status and/or progress of the respective process.
摘要翻译：本发明涉及一种用于对技术过程（10）的状态和进度监视的技术过程（10）的操作进行自动和系统地分析和监视的系统和方法，所述技术过程（10）基于表征当前状态的数据（D）过程（10），其中用于描述和实现用于评估数据（D）的检查标准的检查例程（C）被定义并存储在第一模块（20）中。第一模块（20）与存储在第一模块（D）中的校验例程（C）的第二模块（30）相互作用以形成分层结构化的检查点（CP）。存储在分层结构化检查点（CP）中的检查例程（C）通过分配数据（D）来进行检查。通过过程（10）提供，并且考虑由下级检查点（CP）执行的检查例程（C）的结果，存储在检查例程（C）中的检查条件是否适用，执行自动检查例程（C）的评估并且生成关于相应过程的状态和/或进度的信息。

16. 发明授权

US06985390B2 Integrated memory circuit having a redundancy circuit and a method for replacing a memory area 失效
标题翻译：具有冗余电路的集成存储器电路和用于替换存储区域的方法
公开(公告)号：US06985390B2
公开(公告)日：2006-01-10
申请号：US10831466
申请日：2004-04-23
申请人： Peter Beer
发明人： Peter Beer
IPC分类号： G11C29/00
CPC分类号： G11C29/838 , G11C29/787 , G11C29/812
摘要： An integrated memory circuit having a redundancy circuit for replacing a memory area having an address by a redundant memory area assigned to the redundancy circuit and method for replacing a memory area. In one embodiment, the redundancy circuit comprises one or more fuse storage elements in which the address of the memory area which is to be replaced by the redundant memory area can be set, wherein, for the purpose of setting the address, each of the fuse storage elements may be set to a first state by the respective fuse storage element being left unchanged and set to a second state by the respective fuse storage element being permanently changed, an activation fuse storage element for activating the address stored in the fuse storage elements for replacing the memory area with the redundant memory area, and a deactivation storage element for permitting or preventing replacement of the memory area having the address by the redundant memory area, wherein the deactivation storage element is connected to the fuse storage elements in such a way as to prevent replacement of the memory area if each of the fuse storage elements has been permanently changed and set to the second state.
摘要翻译：一种具有冗余电路的集成存储器电路，用于通过分配给冗余电路的冗余存储区域来替换具有地址的存储区域以及用于替换存储区域的方法。在一个实施例中，冗余电路包括一个或多个保险丝存储元件，其中可以设置要由冗余存储器区域替换的存储器区域的地址，其中为了设置地址，每个保险丝存储元件可以通过相应的保险丝存储元件保持不变而被设置为第一状态，并且通过相应的熔丝存储元件被永久地改变而设置为第二状态;激活熔丝存储元件，用于激活存储在熔丝存储元件中的地址用冗余存储器区域代替存储器区域，以及去激活存储元件，用于允许或防止由冗余存储器区域替换具有地址的存储区域，其中去激活存储元件以这样的方式连接到熔丝存储元件：如果每个保险丝存储元件已经被永久地改变并被设置到第二状态，则防止更换存储器区域。

17. 发明授权

US06922365B2 Read-out circuit for a dynamic memory circuit, memory cell array, and method for amplifying and reading data stored in a memory cell array 失效
标题翻译：用于动态存储器电路的读出电路，存储单元阵列和用于放大和读取存储在存储单元阵列中的数据的方法
公开(公告)号：US06922365B2
公开(公告)日：2005-07-26
申请号：US10653652
申请日：2003-09-02
申请人： Peter Beer
发明人： Peter Beer
IPC分类号： G11C7/06 , G11C11/4091 , G11C7/00
CPC分类号： G11C7/1012 , G11C7/065 , G11C11/4091 , G11C2207/005
摘要： A read-out circuit for a dynamic memory circuit has an interchanging circuit. The interchanging circuit can apply the bit lines that are connected to the storage capacitors to the second and third data output lines and to apply the bit lines that are not connected to the memory cells to the first and fourth data output lines. Sense amplifiers, in each case, are provided for amplifying a potential difference on a first line and a second line. A first sense amplifier is connected to the first and the second data output line. A second sense amplifier is connected to the third and the fourth data output line. A third sense amplifier is connected to the second and the third data output line.
摘要翻译：用于动态存储器电路的读出电路具有互换电路。交换电路可以将连接到存储电容器的位线应用于第二和第三数据输出线，并且将未连接到存储器单元的位线应用于第一和第四数据输出线。在每种情况下，提供感测放大器，用于放大第一行和第二行上的电位差。第一读出放大器连接到第一和第二数据输出线。第二读出放大器连接到第三和第四数据输出线。第三读出放大器连接到第二和第三数据输出线。

18. 发明授权

US06891431B2 Integrated semiconductor circuit configuration 失效
标题翻译：集成半导体电路配置
公开(公告)号：US06891431B2
公开(公告)日：2005-05-10
申请号：US10675761
申请日：2003-09-30
申请人： Peter Beer , Carsten Ohlhoff
发明人： Peter Beer , Carsten Ohlhoff
IPC分类号： G01R15/20 , G01R19/00 , H03F15/00 , G01R31/26
CPC分类号： G01R15/202 , G01R19/0092
摘要： To measure the current consumption of a circuit device with a current measuring device, the circuit device being supplied by a current/voltage supply line device, as simply as possible without the need for additional measuring devices, an integrated circuit configuration includes integrating the circuit configuration, the current measuring device, and, also, the current/voltage supply line device in a common chip and forming the current measuring device with a Hall sensor device.
摘要翻译：为了测量具有电流测量装置的电路装置的电流消耗，电路装置由电流/电压供应线装置提供，尽可能简单地不需要额外的测量装置，集成电路配置包括集成电路配置电流测量装置，以及公共芯片中的电流/电压供应线装置，并用霍尔传感器装置形成电流测量装置。

19. 发明授权

US06813200B2 Circuit configuration for reading out a programmable link 有权
标题翻译：用于读出可编程链路的电路配置
公开(公告)号：US06813200B2
公开(公告)日：2004-11-02
申请号：US10627841
申请日：2003-07-25
申请人： Peter Beer
发明人： Peter Beer
IPC分类号： G11C700
CPC分类号： G11C29/781 , G11C17/18
摘要： A circuit configuration for reading out a programmable link enables programming the programmable link in addition to reading out the programmed value into a volatile memory cell. For this purpose, address lines that are present are coupled to the input of the volatile memory cell by additional switches. Given the presence of a hit signal at the output of a combination unit, the switches are driven by a control circuit in a manner dependent on a set signal. The present circuit is particularly suitable for dynamic semiconductor memories and for mass production.
摘要翻译：用于读出可编程链路的电路配置除了将编程值读出到易失性存储器单元外，还可编程可编程链路。为此，存在的地址线通过附加开关耦合到易失性存储器单元的输入。给定在组合单元的输出处存在命中信号，开关由取决于设置信号的方式由控制电路驱动。本电路特别适用于动态半导体存储器并用于批量生产。

20. 发明授权

US06754110B2 Evaluation circuit for a DRAM 失效
标题翻译： DRAM的评估电路
公开(公告)号：US06754110B2
公开(公告)日：2004-06-22
申请号：US10190814
申请日：2002-07-08
申请人： Peter Beer , Thilo Schaffroth
发明人： Peter Beer , Thilo Schaffroth
IPC分类号： G11C700
CPC分类号： G11C7/18 , G11C7/062 , G11C11/4091 , G11C11/4097
摘要： A circuit configuration for evaluating electrical charges of memory cells in a DRAM is provided. Signal lines within the evaluation circuit cross one another in order to reduce parasitic coupling capacitances between adjacent signal lines of a memory cell array.
摘要翻译：提供了用于评估DRAM中的存储单元的电荷的电路配置。评估电路内的信号线彼此交叉，以减少存储单元阵列的相邻信号线之间的寄生耦合电容。

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