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11. 发明授权

US5488583A Memory integrated circuits having on-chip topology logic driver, and methods for testing and producing such memory integrated circuits 失效
标题翻译：具有片上拓扑逻辑驱动器的存储器集成电路，以及用于测试和产生这种存储器集成电路的方法
公开(公告)号：US5488583A
公开(公告)日：1996-01-30
申请号：US311582
申请日：1994-09-22
申请人： Adrian E. Ong , William K. Waller , Paul S. Zagar
发明人： Adrian E. Ong , William K. Waller , Paul S. Zagar
IPC分类号： G11C7/10 , G11C7/18 , G11C29/36 , G11C7/00 , G11C29/00
CPC分类号： G11C29/36 , G11C7/1006 , G11C7/18
摘要： A memory integrated circuit chip of a predefined circuit topology has an on-chip topology logic driver. The topology logic driver selectively inverts data being written to and read from addressed memory cells in the memory IC based upon location of the addressed memory cells in the circuit topology of the memory array. The topology logic driver is preferably a logic circuit that embodies a boolean function defining the circuit topology. A method for testing and producing such memory ICs is also described.
摘要翻译：预定义电路拓扑的存储器集成电路芯片具有片上拓扑逻辑驱动器。拓扑逻辑驱动器基于存储器阵列的电路拓扑中寻址的存储器单元的位置选择性地反转正在写入存储器IC中的寻址存储器单元的数据和从其读出的数据。拓扑逻辑驱动器优选地是实现定义电路拓扑的布尔函数的逻辑电路。还描述了用于测试和产生这种存储器IC的方法。

12. 发明授权

US5465232A Sense circuit for tracking charge transfer through access transistors in a dynamic random access memory 失效
标题翻译：用于跟踪通过动态随机存取存储器中的存取晶体管的电荷转移的感测电路
公开(公告)号：US5465232A
公开(公告)日：1995-11-07
申请号：US275890
申请日：1994-07-15
申请人： Adrian E. Ong , Paul S. Zagar
发明人： Adrian E. Ong , Paul S. Zagar
IPC分类号： G11C11/409 , G11C11/407 , G11C11/4091 , G11C11/4094 , G11C11/40
CPC分类号： G11C11/4094 , G11C11/4091
摘要： A simple, low-power sense circuit is disclosed that accurately tracks charge transfer between the capacitor of a dynamic random access memory cell and its associated digit line. The circuit, which is preferably located in the peripheral circuitry, employs a model access transistor to charge a pull-up node that is coupled to ground through a capacitor which simulates digit line capacitance. The pull-up node is coupled to the gate of a N-channel field-effect output transistor. When voltage on the node reaches the threshold voltage of the output transistor, the output transistor begins to turn on. The output from the output transistor (in this case, ground potential) is fed back to the gate of a P-channel device which couples the node to V.sub.CC. The P-channel device is used to pull up the node to V.sub.CC rapidly once the trip point (i.e., the threshold voltage) of the N-channel output transistor is reached. The sense circuit is reset for the next read cycle by sending a high signal to the gate of an N-channel reset transistor, which couples the capacitive node to ground.
摘要翻译：公开了一种简单的低功率检测电路，其精确地跟踪动态随机存取存储器单元的电容器与其相关的数字线之间的电荷转移。优选地位于外围电路中的电路采用模型存取晶体管，以通过模拟数字线电容的电容器耦合到地的上拉节点。上拉节点耦合到N沟道场效应输出晶体管的栅极。当节点上的电压达到输出晶体管的阈值电压时，输出晶体管开始导通。输出晶体管（在这种情况下为接地电位）的输出反馈到将节点耦合到VCC的P沟道器件的栅极。一旦达到N沟道输出晶体管的跳变点（即阈值电压），P沟道器件用于将节点快速上拉至VCC。通过向N沟道复位晶体管的栅极发送高信号，将感测电路复位为下一个读取周期，N沟道复位晶体管将电容节点耦合到地。

13. 再颁专利

USRE36952E One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture 失效
标题翻译：一次性可编程完全可测试的可编程逻辑器件，具有零功率和抗熔丝单元架构
公开(公告)号：USRE36952E
公开(公告)日：2000-11-14
申请号：US653516
申请日：1996-05-24
申请人： Paul S. Zagar , Kurt P. Douglas
发明人： Paul S. Zagar , Kurt P. Douglas
IPC分类号： G01R31/3185 , G11C17/16 , H03K19/173
CPC分类号： H03K19/1735 , G01R31/318516 , G11C17/16
摘要： There is a zero power programmable logic device with a one time programmable and fully-testable anti-fuse cell architecture. Specifically, a half-latch and fuse cell circuit allows the PLD to use "zero power" during the standby period since the sense amps are not used to maintain the programmed logic. Additionally, the PLD is capable of being tested for logic gate and logic path integrity, and anti-fuse electrical parameters without permanently programming the anti-fuse.
摘要翻译：有一个零功率可编程逻辑器件，具有一次性可编程和完全可测试的反熔丝单元架构。具体来说，半锁存和熔丝单元电路允许PLD在待机期间使用“零功率”，因为感测放大器不用于维持编程逻辑。此外，PLD能够对逻辑门和逻辑路径完整性进行测试，并且可以对反熔丝电气参数进行测试，而无需永久编程防熔丝。

14. 发明授权

US5953739A Synchronous DRAM cache using write signal to determine single or burst write 有权
标题翻译：同步DRAM缓存使用写入信号来确定单个或突发写入
公开(公告)号：US5953739A
公开(公告)日：1999-09-14
申请号：US247994
申请日：1999-02-10
申请人： Paul S. Zagar , Mirmajid Seyyedy
发明人： Paul S. Zagar , Mirmajid Seyyedy
IPC分类号： G06F12/08 , G11C7/10 , G11C7/18 , G11C11/4097 , G06F13/00
CPC分类号： G11C11/4097 , G06F12/0893 , G11C7/1006 , G11C7/103 , G11C7/18
摘要： A dynamic memory is described which uses a multiplexed latch architecture and global bit lines. The multiplexed architecture allows the memory to operate as a synchronous pipelined cache memory in a computer processing system. The global bit lines are fabricated parallel to memory array bit lines and input/output connections are distributed around the memory to increase speed. Page access operations are controlled to allow either single or burst writes.
摘要翻译：描述了使用多路复用的锁存结构和全局位线的动态存储器。多路复用架构允许存储器在计算机处理系统中作为同步流水线缓存存储器操作。全局位线与存储器阵列位线并行制造，并且输入/输出连接分布在存储器周围以增加速度。控制页面访问操作以允许单次或突发写入。

15. 发明授权

US5747869A Reduced pitch laser redundancy fuse bank structure 失效
公开(公告)号：US5747869A
公开(公告)日：1998-05-05
申请号：US831389
申请日：1997-04-01
申请人： Kirk Prall , Tod S. Stone , Paul S. Zagar
发明人： Kirk Prall , Tod S. Stone , Paul S. Zagar
IPC分类号： H01L21/82 , G11C29/00 , H01L23/525 , H01L27/10 , H01L29/00
CPC分类号： G11C29/785 , G11C29/80 , H01L23/5258 , H01L2924/0002
摘要： A configuration for a laser fuse bank is disclosed wherein the available space is more efficiently used. Fuses of graduated width and variable configuration are placed so as to minimize the average distance between fuses and maximize fuse density. Alternatively, a common source is added to a standard laser fuse structure such that it intersects the fuses and the number of available fuses is doubled.

16. 发明授权

US5552739A Integrated circuit power supply having piecewise linearity 失效
标题翻译：具有分段线性的集成电路电源
公开(公告)号：US5552739A
公开(公告)日：1996-09-03
申请号：US559414
申请日：1995-11-15
申请人： Brent Keeth , Paul S. Zagar , Brian M. Shirley , Stephen L. Casper
发明人： Brent Keeth , Paul S. Zagar , Brian M. Shirley , Stephen L. Casper
IPC分类号： G05F1/46 , G05F1/10
CPC分类号： G05F1/465
摘要： A power supply for an integrated circuit has a piecewise linear operating characteristic for improved integrated circuit testing and screening. In an integrated circuit that receives an externally applied power signal, designated V.sub.CCX, and includes a power supply for generating an internal operating voltage, designated V.sub.CCR, an on-chip power supply circuit provides V.sub.CCR as a piecewise linear function of V.sub.CCX. In a first segment of such a function, V.sub.CCR approximates V.sub.CCX for efficient low voltage operations. In a second segment, used for normal operations of the integrated circuit, V.sub.CCR rises gradually with V.sub.CCX so that test results at the edges of the segment can be guaranteed with a margin for measurement tolerance, process variation, and derating. In a third segment, V.sub.CCR follows below V.sub.CCX at a predetermined constant offset. Transitions between segments are smooth due to nonlinear devices used in the power supply circuitry. When used in a dynamic random access memory integrated circuit, operation in the first segment provides data retention at low power consumption. Operation in the second segment supports speed grading individual devices with a margin for properly stating memory performance specifications. Operation in the third segment supports screening at elevated temperatures for identifying weak and defective memory devices.
摘要翻译：集成电路的电源具有分段线性工作特性，用于改进的集成电路测试和屏蔽。接收外部施加的电源信号（指定为VCCX）的集成电路中，包括用于产生内部工作电压的电源（指定为VCCR），片上电源电路提供VCCR作为VCCX的分段线性功能。在这种功能的第一段中，VCCR逼近VCCX以实现有效的低电压操作。在用于集成电路的正常操作的第二段中，VCCR随着VCCX逐渐上升，从而可以保证测量公差，工艺变化和降额的边缘上的测试结果。在第三部分中，VCCR在预定的常数偏移下遵循VCCX以下。由于电源电路中使用的非线性器件，片段之间的转换是平滑的。当在动态随机存取存储器集成电路中使用时，第一段中的操作以低功耗提供数据保持。第二部分中的操作支持对具有裕量的各个设备进行速度分级，以正确说明内存性能规格。第三部分的操作支持在升高的温度下进行筛选以识别弱和有缺陷的存储器件。

17. 发明授权

US5293342A Wordline driver circuit having an automatic precharge circuit 失效
标题翻译：字线驱动电路具有自动预充电电路
公开(公告)号：US5293342A
公开(公告)日：1994-03-08
申请号：US993929
申请日：1992-12-17
申请人： Stephen L. Casper , Adrian Ong , Paul S. Zagar
发明人： Stephen L. Casper , Adrian Ong , Paul S. Zagar
IPC分类号： G11C8/08 , G11C11/408 , G11C7/00
CPC分类号： G11C8/08 , G11C11/4085
摘要： The invention is an automatic precharge circuit featuring precharge devices each of which is interposed between a high voltage node, connectable to a supply potential, and a serial node. The precharge devices are gated automatically by a primary predecode signal of a decode portion of the row decoder. Power is conserved since the serial nodes are passively pulled to the supply potential through the precharge devices. The invention increases speed and provides error free wordline selection.
摘要翻译：本发明是一种自动预充电电路，其特征在于预充电装置各自插入在可连接到电源电位的高压节点和串联节点之间。预充电装置由行解码器的解码部分的主要预解码信号自动选通。功率节省，因为串行节点被动地通过预充电器件拉到电源电位。本发明提高了速度并提供了无错误的字线选择。

18. 发明授权

US5287017A Programmable logic device macrocell with two OR array inputs 失效
标题翻译：具有两个OR阵列输入的可编程逻辑器件宏单元
公开(公告)号：US5287017A
公开(公告)日：1994-02-15
申请号：US884489
申请日：1992-05-15
申请人： Varadarajan L. Narasimhan , Kurt P. Douglas , Paul S. Zagar
发明人： Varadarajan L. Narasimhan , Kurt P. Douglas , Paul S. Zagar
IPC分类号： H03K19/177 , H03K19/173
CPC分类号： H03K19/17728 , H03K19/17704
摘要： A programmable logic device (PLD) is disclosed, which can efficiently, in a realestate sense, emulate a Mealy state machine. Specifically, there is a PLD which has macrocells which accept signals from two separate logical OR arrays. Where the first array and macrocell produces a latched output signal and the second array and macrocell circuit produces a non-latched output signal.
摘要翻译：公开了一种可编程逻辑器件（PLD），其可以有效地以实质的方式模拟Mealy状态机。具体来说，存在具有接收来自两个单独的逻辑或数组的信号的宏单元的PLD。其中第一阵列和宏单元产生锁存的输出信号，并且第二阵列和宏单元电路产生未锁存的输出信号。

19. 发明授权

US5285408A Method and apparatus for providing a faster ones voltage level restore operation in a dram 失效
标题翻译：提供一种更快速的电压恢复操作的方法和装置
公开(公告)号：US5285408A
公开(公告)日：1994-02-08
申请号：US945206
申请日：1992-09-15
申请人： Michael W. Starkweather , Paul S. Zagar
发明人： Michael W. Starkweather , Paul S. Zagar
IPC分类号： G11C11/4091 , G11C11/4094 , G11C7/00
CPC分类号： G11C11/4094 , G11C11/4091
摘要： There is a DRAM which provides for a faster non-accessed memory cell ones voltage level refresh or restore process. Specifically, the DRAM does not shut down a digit line's voltage pull-up circuitry (PSA) during a write operation. By leaving on the PSA, the digit lines being pulled to a ones voltage level will continue to be pulled up during the write operation. Thus, a non-accessed digit line will reach the ones voltage level in a shorter time than if the PSA were turned off during the write operation.
摘要翻译：存在DRAM，其提供更快的非存取存储单元电压电平刷新或恢复过程。具体来说，DRAM在写入操作期间不会关闭数字线的电压上拉电路（PSA）。通过离开PSA，在写入操作期间，被拉到一个电压电平的数字线将继续被上拉。因此，在写入操作期间，如果PSA被关闭，则不被访问的数字线将在更短的时间内达到一个电压电平。

20. 发明授权

US5802010A Burst EDO memory device 失效
公开(公告)号：US5802010A
公开(公告)日：1998-09-01
申请号：US661478
申请日：1996-06-10
申请人： Paul S. Zagar , Brett L. Williams , Troy A. Manning
发明人： Paul S. Zagar , Brett L. Williams , Troy A. Manning
IPC分类号： G06F12/06 , G11C7/10 , G11C11/407 , G11C8/00
CPC分类号： G11C7/109 , G06F12/0638 , G11C11/407 , G11C7/1018 , G11C7/1021 , G11C7/1024 , G11C7/1039 , G11C7/1045 , G11C7/1078 , G11C7/1096 , G06F2212/2022
摘要： An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.

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