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11. 发明申请

US20050194668A1 Wafer scale die handling 有权
标题翻译：晶片刻度处理
公开(公告)号：US20050194668A1
公开(公告)日：2005-09-08
申请号：US10792757
申请日：2004-03-05
申请人： Paul Enquist , Gaius Fountain , Carl Petteway
发明人： Paul Enquist , Gaius Fountain , Carl Petteway
IPC分类号： H01L23/495
CPC分类号： H01L21/67333 , H01L2924/0002 , Y10S414/135 , Y10S414/14 , Y10S414/141 , H01L2924/00
摘要： A waffle pack device including a member having recesses in a surface of the member to accommodate die from at least one semiconductor wafer. The member is compatible with semiconductor wafer handling equipment and/or semiconductor wafer processing. Preferably, the member accommodates at least a majority of die from a semiconductor wafer. Further, one semiconductor device assembly method is provided which removes die from a singular waffle pack device, places die from the single waffle pack device on a semiconductor package to assemble from the placed die all die components required for an integrated circuit, and electrically interconnects the placed die in the semiconductor package to form the integrated circuit. Another semiconductor device assembly method is provided which removes die from at least one waffle pack device, places die from the at least one waffle pack device on a semiconductor package to assemble from the placed die device components required for an integrated circuit, and electrically interconnects the placed die in the semiconductor package to form the integrated circuit.
摘要翻译：一种华夫饼包装置，包括在所述构件的表面中具有凹部以容纳来自至少一个半导体晶片的模具的构件。该元件与半导体晶片处理设备和/或半导体晶片处理兼容。优选地，构件容纳来自半导体晶片的至少大部分管芯。此外，提供了一种半导体器件组装方法，其从单个华夫饼包装置中去除裸片，将来自单个华夫饼包装置的管芯放置在半导体封装上，以从放置的管芯组装集成电路所需的所有管芯部件，并将放置在半导体封装中以形成集成电路。提供了另一种半导体器件组装方法，其从至少一个华夫饼包装置去除管芯，将来自至少一个华夫饼包装置的管芯放置在半导体封装上，以从集成电路所需的放置的管芯器件组件中组装，并将放置在半导体封装中以形成集成电路。

12. 发明授权

US07126212B2 Three dimensional device integration method and integrated device 有权
公开(公告)号：US07126212B2
公开(公告)日：2006-10-24
申请号：US10011432
申请日：2001-12-11
申请人： Paul M. Enquist , Gaius Fountain
发明人： Paul M. Enquist , Gaius Fountain
IPC分类号： H01L29/08
CPC分类号： H01L24/08 , H01L21/187 , H01L21/2007 , H01L21/6835 , H01L21/76251 , H01L21/76898 , H01L21/8221 , H01L23/13 , H01L23/36 , H01L23/481 , H01L23/5384 , H01L23/5385 , H01L23/5389 , H01L23/552 , H01L24/24 , H01L24/26 , H01L24/27 , H01L24/30 , H01L24/48 , H01L24/80 , H01L24/82 , H01L24/83 , H01L24/94 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/16 , H01L25/167 , H01L25/18 , H01L25/50 , H01L27/0688 , H01L27/14634 , H01L2221/6835 , H01L2221/68359 , H01L2221/68363 , H01L2223/6677 , H01L2224/0807 , H01L2224/08123 , H01L2224/1134 , H01L2224/16 , H01L2224/24011 , H01L2224/24225 , H01L2224/24226 , H01L2224/24227 , H01L2224/3005 , H01L2224/30104 , H01L2224/305 , H01L2224/48091 , H01L2224/48101 , H01L2224/48227 , H01L2224/48247 , H01L2224/80896 , H01L2224/81894 , H01L2224/8303 , H01L2224/83092 , H01L2224/83099 , H01L2224/8319 , H01L2224/83193 , H01L2224/83345 , H01L2224/83359 , H01L2224/8385 , H01L2224/83894 , H01L2224/83896 , H01L2224/83912 , H01L2224/83948 , H01L2224/9202 , H01L2224/9212 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06555 , H01L2225/06589 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01074 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/05442 , H01L2924/07802 , H01L2924/10253 , H01L2924/10329 , H01L2924/1305 , H01L2924/13062 , H01L2924/13063 , H01L2924/13064 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/351 , Y10S148/012 , Y10S438/977 , H01L2224/13099 , H01L2924/01049 , H01L2924/01031 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
摘要： A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. A conductor array having a plurality of contact structures may be formed on an exposed surface of the semiconductor device, vias may be formed through the semiconductor device to device regions, and interconnection may be formed between said device regions and said contact structures.

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