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    • 13. 发明授权
    • Electronic playset
    • 电子戏剧
    • US08292689B2
    • 2012-10-23
    • US11865620
    • 2007-10-01
    • Mark HardinAndy ChanEric SkifstromJack Millerick
    • Mark HardinAndy ChanEric SkifstromJack Millerick
    • A63F3/52
    • A63H3/52A63H33/26
    • The present disclosure provides for electronic playsets and components thereof. An electronic playset of the present disclosure may include a see-through monitor having a transparent screen configured to display an animated image superimposed over one or more regions. The see-through monitor may be moveable by rotation or translation between one or more positions, the one or more positions being adjacent to the one or more regions. Some embodiments including a see-through monitor with a light source configured to illuminate the one or more regions. Another aspect of the present disclosure provides for a removable toy having an identifiable accessory that may be provided to an electronic playset. The playset may be configured to identify the toy and display an animated character based on the identity.
    • 本公开提供电子乐曲及其组件。 本公开的电子乐曲集可以包括透视监视器,其具有被配置为显示叠加在一个或多个区域上的动画图像的透明屏幕。 透视监视器可以通过一个或多个位置之间的旋转或平移来移动,该一个或多个位置与一个或多个区域相邻。 一些实施例包括具有被配置为照亮一个或多个区域的光源的透视监视器。 本公开的另一方面提供了一种可移除的玩具,其具有可被提供给电子游戏装置的可识别的附件。 玩具可以被配置为识别玩具并基于身份显示动画角色。
    • 15. 发明申请
    • Single-ended transmission for direct access test mode within a differential input and output circuit
    • 单端传输,用于差分输入和输出电路中的直接访问测试模式
    • US20050251720A1
    • 2005-11-10
    • US10839635
    • 2004-05-05
    • Wayne FangAndy ChanKuek-Hock Lee
    • Wayne FangAndy ChanKuek-Hock Lee
    • G01R31/28G01R31/317G06F11/00G11C29/48
    • G11C29/1201G01R31/3172G11C29/48
    • An integrated circuit, such as an integrated circuit memory device, includes an output circuit capable to provide a differential signal on first and second contacts during a first mode of operation, such as in a read or write mode of operation, and a single-ended signal on the first contact during a second mode of operation, such as a test mode of operation. A first variable resistor, responsive to a first control signal, is coupled to a first voltage source and the first contact. A second variable resistor, responsive to a second control signal, is coupled to a second voltage source and the second contact. A first transistor has a first electrode coupled to the first contact, a second electrode coupled to the current source and a gate to receive a first input signal. A second transistor has a first electrode coupled to the second contact, a second electrode coupled to the current source and a gate to receive a second input signal. A differential signal is provided on the first and second contacts responsive to the first and second input signals and first and second control signals. A test circuit included in external test equipment with a predetermined resistor is coupled to the integrated circuit and receives a single-ended signal from the output circuit in a test mode of operation.
    • 诸如集成电路存储器件的集成电路包括输出电路,其能够在第一操作模式(例如在读取或写入操作模式下)在第一和第二触点上提供差分信号,并且单端 在第二操作模式下的第一接触信号,例如测试操作模式。 响应于第一控制信号的第一可变电阻器耦合到第一电压源和第一触点。 响应于第二控制信号的第二可变电阻器耦合到第二电压源和第二触点。 第一晶体管具有耦合到第一触点的第一电极,耦合到电流源的第二电极和用于接收第一输入信号的栅极。 第二晶体管具有耦合到第二触点的第一电极,耦合到电流源的第二电极和用于接收第二输入信号的栅极。 响应于第一和第二输入信号以及第一和第二控制信号,在第一和第二接点上提供差分信号。 包含在具有预定电阻器的外部测试设备中的测试电路耦合到集成电路,并且在测试操作模式下从输出电路接收单端信号。
    • 18. 发明授权
    • Fast and gate with programmable output polarity
    • 快速和门极可编程输出
    • US4638189A
    • 1987-01-20
    • US626377
    • 1984-06-29
    • George GeannopoulosCyrus TsuiMark FitzpatrickAndy Chan
    • George GeannopoulosCyrus TsuiMark FitzpatrickAndy Chan
    • H03K19/177H03K17/66H03K19/173H03K19/20G06F11/28H03K19/003H03K19/082
    • H03K19/1736H03K17/666
    • The present invention combines in either a logical AND function of N logical input signals, where N is a selected positive integer greater than or equal to 1, and provides programmably, either a direct AND output signal or a NAND output signal. The invention accomplishes this using a minimum number of components in the data path, between the logical input leads and logical output leads. A minimum of components in the data path reduces the propagation delay introduced by the circuit. The invention accomplishes this by providing two AND gates connected to the same set of N logical input signals. The output signal of one AND gate is inverted by an inverter with an enable/disable input lead. The output signal of the other AND gate is inverted twice by two inverters. The second inverter has an enable/disable input lead. Means are provided for exclusively enabling one or the other of the two inverters with an enable/disable input lead. Thus, either the once inverted signal is provided to the output lead or the twice inverted signal is provided to the output lead.
    • 本发明以N逻辑输入信号的逻辑和功能组合,其中N是大于或等于1的选择的正整数,并且可编程地提供直接AND输出信号或NAND输出信号。 本发明使用数据路径中的最小数量的组件,逻辑输入引线和逻辑输出引线之间来实现。 数据路径中的最小组件减少了由电路引入的传播延迟。 本发明通过提供连接到同一组N个逻辑输入信号的两个与门来实现这一点。 一个与门的输出信号由具有使能/禁止输入引线的反相器反相。 另一个与门的输出信号由两个反相器反相两次。 第二个反相器具有使能/禁止输入引线。 提供了用于通过使能/禁止输入引线独占地使能两个逆变器中的一个或另一个的装置。 因此,将一次反相信号提供给输出引线,或将两次反相信号提供给输出引线。