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11. 发明授权

US06472262B2 Method for fabricating a bipolar transistor of the self-aligned double-polysilicon type with a heterojunction base and corresponding transistor 有权
标题翻译：用于制造具有异质结基极和相应晶体管的自对准双多晶硅型双极晶体管的方法
公开(公告)号：US06472262B2
公开(公告)日：2002-10-29
申请号：US09817898
申请日：2001-03-26
申请人： Alain Chantre , Didier Dutartre , Hélène Baudry
发明人： Alain Chantre , Didier Dutartre , Hélène Baudry
IPC分类号： H01L218249
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A self-aligned double-polysilicon type bi-polar transistor with a heterojunction base comprises a semiconducting heterojunction region lying over an active region of a semiconductor substrate and over an isolating region delimiting the active region, and incorporating the intrinsic base region of the transistor. An emitter region situated above the active region and coming into contact with the upper surface of the semiconducting heterojunction region. A polysilicon layer forming the extrinsic base region of the transistor, situated on each side of the emitter region and separated from the semiconducting heterojunction region by a separation layer comprising an electrically conducting connection part situated just outside the emitter region. This connection part ensures an electrical contact between the extrinsic base and the intrinsic base.
摘要翻译：具有异质结基底的自对准双多晶硅型双极晶体管包括位于半导体衬底的有源区上方的半导体异质结区域和界定有源区域的隔离区域，以及掺入晶体管的本征基极区域。位于有源区上方并与半导体异质结区的上表面接触的发射极区。形成晶体管的非本征基极区域的多晶硅层，位于发射极区域的每一侧，并且通过分离层与半导体异质结区域分离，所述分离层包括位于发射极区域正前方的导电连接部分。该连接部件确保外部基座和内部基座之间的电接触。

12. 发明授权

US06403437B1 Method for making hyperfrequency transistor 失效
标题翻译：制造超频晶体管的方法
公开(公告)号：US06403437B1
公开(公告)日：2002-06-11
申请号：US09445425
申请日：1999-12-29
申请人： Alain Chantre , Jean Du Port De Poncharra
发明人： Alain Chantre , Jean Du Port De Poncharra
IPC分类号： H01L218222
CPC分类号： H01L29/66272 , H01L29/732
摘要： A bipolar transistor including an extrinsic base on the surface of a silicon substrate covered by a first layer of doped polycrystalline silicon, an intrinsic base that is separated from the extrinsic base and covered by a second layer of polycrystalline silicon that constitutes the emitter and that is insulated from the first layer of polycrystalline silicon, and a link base that links the extrinsic base to the intrinsic base. The link base is located under the first layer of doped polycrystalline silicon.
摘要翻译：一种双极晶体管，包括在由第一掺杂多晶硅层覆盖的硅衬底的表面上的非本征基极，本征基极与外部基极分离并由构成发射极的第二多晶硅层覆盖，与第一层多晶硅绝缘，以及将外部基极连接到本征基底的连接基底。链路基座位于第一层掺杂多晶硅下面。

13. 发明授权

US5367184A Vertical JFET transistor with optimized bipolar operating mode and corresponding method of fabrication 失效
标题翻译：具有优化双极性工作模式和相应制造方法的垂直JFET晶体管
公开(公告)号：US5367184A
公开(公告)日：1994-11-22
申请号：US87427
申请日：1993-07-02
申请人： Alain Chantre
发明人： Alain Chantre
IPC分类号： H01L21/331 , H01L21/337 , H01L29/737 , H01L29/808 , H01L29/161 , H01L29/205 , H01L29/225
CPC分类号： H01L29/66916 , H01L29/66242 , H01L29/7371 , H01L29/8083
摘要： The vertical junction field-effect transistor comprises a semiconductor structure including an internal semiconductor layer (23, 26) extending within the channel region (7) between the gate region (4, 31), this internal layer being produced in a semiconductor material, having an energy gap (Eg.sup.2) smaller than that of the material forming the channel and gate regions, and the same type of conductivity (N) as that of the channel region, and the heterojunction formed between this internal layer and the channel region exhibits a band discontinuity situated in the valence band in the case of a N-type channel, or in the conduction band in the case of a P-type channel.
摘要翻译：垂直结场效应晶体管包括半导体结构，其包括在栅极区域（4,31）之间的沟道区域（7）内延伸的内部半导体层（23,26），该内部层由半导体材料制成，具有比形成沟道和栅极区域的材料小的能隙（Eg2）和与沟道区域相同类型的导电率（N），并且在该内部层和沟道区域之间形成的异质结带呈现带状在N型通道的情况下位于价带中的不连续性，或者在P型通道的情况下在导带中。

14. 发明授权

US06744080B2 Method of manufacturing a bipolar transistor of double-polysilicon, heterojunction-base type and corresponding transistor 有权
标题翻译：制造双晶硅，异质结基极型和相应晶体管的双极晶体管的方法
公开(公告)号：US06744080B2
公开(公告)日：2004-06-01
申请号：US10097651
申请日：2002-03-13
申请人： Alain Chantre , Helene Baudry , Didier Dutartre
发明人： Alain Chantre , Helene Baudry , Didier Dutartre
IPC分类号： H01L2973
CPC分类号： H01L29/66242 , H01L29/7378
摘要： Transistor and method of manufacturing a bipolar transistor of the double-polysilicon, heterojunction-base type, in which a semiconducting layer with SiGe heterojunction is formed by non-selective epitaxy on an active region of a substrate and an insulating region surrounding the active region. At least one stop layer is formed on the semiconducting layer above a part of the active region. A layer of polysilicon and an upper insulating layer are formed on the semiconducting layer and on a part of the stop layer, leaving an emitter window free. An emitter region is formed by epitaxy in the emitter window, resting partially on the upper insulating layer and in contact with the semiconducting layer.
摘要翻译：晶体管和双晶硅异质结基极型双极晶体管的制造方法，其中具有SiGe异质结的半导体层通过非选择性外延在衬底的有源区和围绕有源区的绝缘区形成。在有源区域的一部分上方的半导体层上形成至少一个阻挡层。在半导体层和停止层的一部分上形成多晶硅层和上绝缘层，留下发射器窗口。发射极区域通过在发射极窗中外延形成，部分地搁置在上绝缘层上并与半导体层接触。

15. 发明授权

US06436782B2 Process for fabricating a self-aligned double-polysilicon bipolar transistor 有权
标题翻译：用于制造自对准双重多晶硅双极晶体管的工艺
公开(公告)号：US06436782B2
公开(公告)日：2002-08-20
申请号：US09796116
申请日：2001-02-28
申请人： Alain Chantre , Michel Marty , Hélène Baudry
发明人： Alain Chantre , Michel Marty , Hélène Baudry
IPC分类号： H01L21331
CPC分类号： H01L29/66242
摘要： The process includes successively forming, over a base region of a semiconductor substrate, a poly-Ge or poly-SiGe layer, an etch-stop layer over a selected zone of the Ge or SiGe layer, a layer of poly-Si of the same conductivity type as the base region, then an outer layer of dielectric material. Etching the layers includes stopping at the stop layer to form an emitter window preform, removing the stop film and selectively removing the Ge or SiGe layer in the emitter window preform to form an emitter window and to form an emitter made of poly-Si of conductivity type the opposite of the base region in the window.
摘要翻译：该方法包括在半导体衬底的基极区域上依次形成多晶Ge或多晶硅层，在Ge或SiGe层的选定区域上的蚀刻停止层，相同的多晶硅层导电类型作为基极区，然后是外层介电材料。蚀刻层包括在停止层处停止以形成发射器窗预制件，去除停止膜并选择性地去除发射器窗预制件中的Ge或SiGe层以形成发射极窗并形成由导电性的多晶硅制成的发射极键入窗口中的基础区域的相反。

16. 发明授权

US06265275B1 Method of selectively doping the intrinsic collector of a vertical bipolar transistor with epitaxial base 有权
标题翻译：用外延基极选择性掺杂垂直双极晶体管的本征集电极的方法
公开(公告)号：US06265275B1
公开(公告)日：2001-07-24
申请号：US09323525
申请日：1999-06-01
申请人： Michel Marty , Alain Chantre , Thierry Schwartzmann
发明人： Michel Marty , Alain Chantre , Thierry Schwartzmann
IPC分类号： H01L21331
CPC分类号： H01L29/66242 , H01L29/0826 , H01L29/7378
摘要： The collector of a vertical bipolar transistor is selectively doped by a first implantation of dopants before the epitaxy of the base, and is selectivly doped by a second implantation of dopants through the epitaxial base. Two implanted zones with different widths are obtained. The base of the vertical bipolar transistor is thinned and the collector resistance is optimized.
摘要翻译：垂直双极晶体管的集电极通过在基极的外延之前的第一注入掺杂剂选择性地掺杂，并且通过外延基底的第二注入掺杂剂被选择地掺杂。获得具有不同宽度的两个植入区。垂直双极晶体管的基极变薄，集电极电阻被优化。

17. 发明授权

US06902970B2 Integrated circuit including, and fabrication method for producing, bipolar and MOSFET transistors 有权
标题翻译：集成电路包括双极晶体管和MOSFET晶体管的制造方法
公开(公告)号：US06902970B2
公开(公告)日：2005-06-07
申请号：US10352376
申请日：2003-01-27
申请人： Michel Marty , Alain Chantre
发明人： Michel Marty , Alain Chantre
IPC分类号： H01L21/8249 , H01L21/8238
CPC分类号： H01L21/8249
摘要： Production of an insulated-gate field-effect transistor is begun and interrupted at an uncompleted point. Then, a bipolar transistor is almost completely produced. At that point, a return is made to the production of the insulated-gate field-effect transistor. Lastly, a finishing step common to both transistors and including common thermal annealing and common siliciding is performed.
摘要翻译：绝缘栅场效应晶体管的制造在未完成的点开始和中断。然后，双极晶体管几乎完全产生。此时，对绝缘栅场效应晶体管的制造进行了回归。最后，执行两个晶体管共同的包括普通热退火和普通硅化的完成步骤。

18. 发明授权

US06551891B1 Process for fabricating a self-aligned vertical bipolar transistor 有权
标题翻译：制造自对准垂直双极晶体管的工艺
公开(公告)号：US06551891B1
公开(公告)日：2003-04-22
申请号：US09668428
申请日：2000-09-22
申请人： Alain Chantre , Michel Marty , Helene Baudry
发明人： Alain Chantre , Michel Marty , Helene Baudry
IPC分类号： H01L21331
CPC分类号： H01L29/66242 , H01L29/66272
摘要： The fabrication process comprises a phase of producing a base region having an extrinsic base and an intrinsic base, and a phase of producing an emitter region comprising an emitter block having a narrower lower part located in an emitter window provided above the intrinsic base. Production of the extrinsic base comprises implantation of dopants, carried out after the emitter window has been defined, on either side of and at a predetermined distance dp from the lateral boundaries of the emitter window, so as to be self-aligned with respect to this emitter window, and before the emitter block is formed.
摘要翻译：该制造工艺包括产生具有非本征基极和本征基极的基极区域的相位，以及产生发射极区域的相位，该发射极区域包括位于位于本征基底之上的发射极窗口中的较窄的下部的发射极阵列。外部基极的制造包括在发射极窗口被限定之后进行的掺杂剂的注入，并且在距离发射器窗口的横向边界的预定距离dp处，以便相对于该自对准发射极窗口，并且在发射极块形成之前。

19. 发明授权

US06384469B1 Vertical bipolar transistor, in particular with an SiGe heterojunction base, and fabrication process 失效
标题翻译：垂直双极晶体管，特别是SiGe异质结基底和制造工艺
公开(公告)号：US06384469B1
公开(公告)日：2002-05-07
申请号：US09674021
申请日：2000-10-23
申请人： Alain Chantre
发明人： Alain Chantre
IPC分类号： H01L27082
CPC分类号： H01L29/66287 , H01L29/66242 , H01L29/7378
摘要： The semiconductor region of an intrinsic collector is surrounded with a lateral insulating region. A semi-conducting layer comprising a SiGe heterojunction is partially located between the transmitter and the intrinsic collector and extends on either side of the transmitter above the lateral insulating region. The base intrinsic region is formed in said semi-conducting layer with heterojunction between the transmitter and the intrinsic collector. The base extrinsic region and the collector extrinsic region respectively comprise first zones formed in said semi-conducting layer with heterojunction, located respectively on either side of the transmitter and above the lateral insulating region first part and mutually electrically insulated by the lateral insulating region second part.
摘要翻译：本征收集器的半导体区域被侧面绝缘区域包围。包括SiGe异质结的半导电层部分地位于发射器和本征收集器之间，并且在发射机的两侧在横向绝缘区域上方延伸。基本本征区域在发射器和本征收集器之间的异质结形成在所述半导电层中。基极外部区域和集电极外部区域分别包括形成在具有异质结的所述半导体层中的第一区域，分别位于发射器的两侧并且位于横向绝缘区域第一部分之上，并且由横向绝缘区域第二部分。

20. 发明授权

US06177717B1 Low-noise vertical bipolar transistor and corresponding fabrication process 有权
标题翻译：低噪声垂直双极晶体管及相应的制造工艺
公开(公告)号：US06177717B1
公开(公告)日：2001-01-23
申请号：US09323418
申请日：1999-06-01
申请人： Alain Chantre , Michel Marty , Didier Dutartre , Augustin Monroy , Michel Laurens , Francois Guette
发明人： Alain Chantre , Michel Marty , Didier Dutartre , Augustin Monroy , Michel Laurens , Francois Guette
IPC分类号： H01L27082
CPC分类号： H01L29/66242 , H01L29/0826 , H01L29/7378
摘要： The intrinsic collector of a vertical bipolar transitor is grown epitaxially on an extrinsic collector layer buried in a semiconductor substrate. A lateral isolation region surrounds the upper part of the intrinsic collector and an offset extrinsic collector well is produced. An SiGe heterojunction base lying above the intrinsic collector and above the lateral isolation region is produced by non-selective epitaxy. An in-situ doped emitter is produced by epitaxy on a predetermined window in the surface of the base which lies above the intrinsic collector so as to obtain, at least above the window, an emitter region formed from single-crystal silicon and directly in contact with the silicon of the base.
摘要翻译：垂直双极性偏转器的本征集电极外延生长在埋在半导体衬底中的非本征集电极层上。横向隔离区域围绕本征收集器的上部，并产生偏移的外部收集阱。通过非选择性外延生产位于本征收集器之上和横向隔离区上方的SiGe异质结基底。原位掺杂的发射体通过在位于本征集电极上方的基底表面上的预定窗口上外延生长，以便至少在窗口上方获得由单晶硅形成并直接接触的发射极区域与基底的硅。

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