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    • 11. 发明授权
    • Test system emulator
    • 测试系统仿真器
    • US5951704A
    • 1999-09-14
    • US802857
    • 1997-02-19
    • Robert F. SauerKiyoshi FukushimaHiroaki Yamoto
    • Robert F. SauerKiyoshi FukushimaHiroaki Yamoto
    • G06F11/22G01R31/319G06F11/26G06F9/455
    • G06F11/261G01R31/31917
    • An emulator software in a semiconductor test system for emulating hardware in the semiconductor test system as well as a semiconductor device to be tested without need to use an actual test system hardware. The emulator software includes an emulator unit which emulates a function of each hardware unit of the test system, a device emulator which emulates a function of a semiconductor device to be tested, a data collecting part for acquiring data from the emulator unit necessary for carrying out a test program, and a device test emulator which generates a test signal to be applied to the device emulator based on the acquired data and compares the resultant signal from the device emulator with the expected data and stores the comparison result therein. In the other aspect, the emulator is combined with the operating system of the semiconductor test system which is capable of easily modifying the software when there is a change or replacement of the hardware of the test system so that the transmission of the control data for the hardware and its operation or the development of the test program can be carried out without using the hardware of the test system.
    • 用于模拟半导体测试系统中的硬件的半导体测试系统中的仿真器软件以及要测试的半导体器件,而不需要使用实际的测试系统硬件。 仿真器软件包括仿真测试系统的每个硬件单元的功能的仿真器单元,模拟要测试的半导体器件的功能的器件仿真器,用于从执行所需的仿真器单元获取数据的数据收集部件 测试程序和设备测试仿真器,其基于所获取的数据生成要应用于设备仿真器的测试信号,并将来自设备仿真器的结果信号与预期数据进行比较并将比较结果存储在其中。 另一方面,仿真器与半导体测试系统的操作系统组合,当测试系统的硬件发生变化或更换时,能够容易地修改软件,以便传输控制数据 可以在不使用测试系统的硬件的情况下执行硬件及其操作或开发测试程序。
    • 12. 发明授权
    • Memory protection circuit for EPROM
    • EPROM存储保护电路
    • US5506806A
    • 1996-04-09
    • US309028
    • 1994-09-20
    • Kiyoshi Fukushima
    • Kiyoshi Fukushima
    • G06F12/14G06F21/24G11C7/24G11C16/02G11C16/04G11C16/22G11C17/00G11C7/00
    • G11C16/22G11C7/24
    • An erasable programmable read-only memory (EPROM) includes a plurality of EPROM cells arranged in a matrix having a plurality of rows and a plurality of columns, and a plurality of digit lines each connected in common to drains of the EPROM cells included in a corresponding one column of EPROM cells. A Y-selector receives a Y-address of a given address for selecting one digit line of the digit lines so as to connect the selected digit line to a sense amplifier. Each of the digit lines is connected to one of reading-inhibition circuits having a reading-inhibition information storing EPROM cell, so that when the reading-inhibition information storing EPROM cell of the reading-inhibition circuits are in a written condition, the digit line is forcibly maintained at a predetermined logic level. The EPROM can inhibit the reading of any bit or bits and any area of an EPROM.
    • 可擦除可编程只读存储器(EPROM)包括以矩阵形式排列的多个EPROM单元,该多个EPROM单元具有多行和多列,以及多个数字线,每个数字线共同连接到包含在其中的EPROM单元的漏极 相应的一列EPROM单元。 Y选择器接收用于选择数字线的一位数字线的给定地址的Y地址,以将所选择的数字线连接到读出放大器。 每个数字线连接到具有存储EPROM单元的读取禁止信息的读取禁止电路之一,使得当读取禁止电路的EPROM单元的读取禁止信息处于写入状态时,数字线 被强制维持在预定的逻辑电平。 EPROM可以禁止对EPROM的任何位或位和任何区域的读取。
    • 17. 发明授权
    • Input circuit for mode setting
    • 模式设定输入电路
    • US5764075A
    • 1998-06-09
    • US736498
    • 1996-10-24
    • Kiyoshi Fukushima
    • Kiyoshi Fukushima
    • G06F1/32G06F15/78H03K19/00H03K19/003H03K17/173
    • H03K19/003H03K19/0016
    • In order to provide an input circuit for mode setting with a simple configuration sufficiently stable and without unnecessary current consumption, the input circuit of the invention, for outputting a control signal (MODE OUT) according to a status of a mode setting terminal (I1), comprises latch means (100) being reset with a rising edge of a reset signal (RES) to output the control signal (MODE OUT) of logic LOW and latching logic of the mode setting terminal (I1) with a falling edge of a delayed signal (RESD) of said reset signal (RES) for maintaining to output inverse or the same logic of said logic of the mode setting terminal (I1) latched, and pull-up or pull-down means (P1) becoming ON for pulling up or down the mode setting terminal (I1) to logic HIGH or LOW when the mode setting terminal (I1) is left open gated by logic LOW of the control signal (MODE OUT) and becoming OFF for cutting a current flowing through the mode setting terminal (I1) gated by logic HIGH of the control signal (MODE OUT).
    • 为了提供具有足够稳定且没有不必要的电流消耗的简单配置的模式设置的输入电路,本发明的输入电路用于根据模式设置端子(I1)的状态输出控制信号(MODE OUT) 包括以复位信号(RES)的上升沿复位的锁存装置(100),以输出逻辑低电平的控制信号(MODE OUT)和模式设置端子(I1)的锁存逻辑,其延迟的下降沿 所述复位信号(RES)的信号(RESD)用于保持输出与锁存的模式设定端子(I1)的所述逻辑相反或相同的逻辑,并且上拉或下拉装置(P1)变为导通以拉起 或者当模式设定端子(I1)由控制信号(MODE OUT)的逻辑低电位门开启时,模式设定端子(I1)变为逻辑高电平或低电平,并且变为OFF以切断流过模式设定端子的电流 (I1)由逻辑高电平控制 gnal(MODE OUT)。
    • 19. 发明授权
    • Automatic control system for offset printing machine
    • 胶印机自动控制系统
    • US4353299A
    • 1982-10-12
    • US225606
    • 1981-01-16
    • Kazuo MuraiKenji HashimotoKiyoshi FukushimaSumio Suzuki
    • Kazuo MuraiKenji HashimotoKiyoshi FukushimaSumio Suzuki
    • B41F33/02B41F33/16G05B19/07B41F7/06B41F7/36B41F7/40B41F31/30
    • B41F33/16B41F33/025G05B19/07
    • An automatic control system for an offset printing machine includes a process execution instructions generating circuit having latched therein instructions for executing various operation processes and adapted to shift from one operation phase to another for successively generating process execution instructions, so that an ink forming and master plate feeding process, an inking process, a transfer-printing process, a printing process, and a master plate ejecting and cleaning process can be automatically executed in correct order. The number of times for executing each of the etching, inking, transfer-printing and cleaning processes can be adjusted in a process setting structure. When a master plate feeding error detecting signal is generated, the process execution instructions generating circuit is reset to an initial condition of stop instructions which prevailed prior to actuation of a start switch. When a master plate ejection error signal or other misoperation indicating signal is generated, the process execution instructions generating circuit remains latched to the current operation process, and a lamp is lighted to indicate the process in which misoperation has occurred. The period of time for moistening an etching roller can be determined depending on the number of copies to be produced. The control system allows the offset printing machine to manually execute any operation process or processes as desired.
    • 一种胶版印刷机的自动控制系统包括:一个处理执行指令产生电路,其中锁存有用于执行各种操作处理的指令,并适于从一个操作阶段转移到另一个操作阶段,以连续生成处理执行指令,使得油墨成型和主板 可以以正确的顺序自动执行进纸处理,上墨处理,转印打印处理,打印处理和主印版喷射和清洁处理。 可以在处理设置结构中调整执行每个蚀刻,着墨,转印和清洁处理的次数。 当产生主板进给错误检测信号时,处理执行指令产生电路被复位到在启动开关之前占用的停止指令的初始状态。 当产生主板排出错误信号或其他误操作指示信号时,处理执行指令产生电路保持锁定到当前操作过程,并且点亮指示发生误操作的处理的灯。 用于润湿蚀刻辊的时间可以根据要生产的拷贝数来确定。 控制系统允许胶印机根据需要手动执行任何操作过程或过程。