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    • 13. 发明申请
    • Scalable Virtual Appliance Cloud (SVAC) and Methods Usable in an SVAC
    • 可扩展虚拟设备云(SVAC)和SVAC中可用的方法
    • US20130242999A1
    • 2013-09-19
    • US13484216
    • 2012-05-30
    • Keshav G. KambleDar-Ren LeuNilanjan MukherjeeVijoy A. Pandey
    • Keshav G. KambleDar-Ren LeuNilanjan MukherjeeVijoy A. Pandey
    • H04L12/56
    • H04L63/101G06F9/45558H04L45/64H04L47/125
    • According to one embodiment, a method for providing scalable virtual appliance cloud (SVAC) services includes receiving incoming data traffic having multiple packets directed toward a SVAC using at least one switching distributed line card (DLC), determining that a packet satisfies a condition of an access control list (ACL), designating a destination port to send the packet based on the condition of the ACL being satisfied, fragmenting the packet into cells, wherein the designated destination port is stored in a cell header of the cells, sending the cells to the destination port via at least one switch fabric controller (SFC), receiving the cells at a fabric interface of an appliance DLC, reassembling the cells into a second packet, performing one or more services on the second packet using the appliance DLC, and sending the second packet to its intended port.
    • 根据一个实施例,一种用于提供可伸缩虚拟设备云(SVAC)服务的方法包括使用至少一个交换分布式线卡(DLC)接收具有指向SVAC的多个分组的输入数据业务,确定分组满足条件 访问控制列表(ACL),根据满足ACL的条件指定发送分组的目的地端口,将分组分段成小区,其中指定的目的地端口存储在小区的小区头部中,将小区发送到 经由至少一个交换结构控制器(SFC)的目的地端口,在设备DLC的结构接口处接收小区,将小区重新组合成第二分组,使用设备DLC在第二分组上执行一个或多个服务,以及发送 第二个数据包到其预定端口。
    • 16. 发明申请
    • Thread Execution in a Computing Environment
    • 线程在计算环境中执行
    • US20120324460A1
    • 2012-12-20
    • US13602365
    • 2012-09-04
    • Dayavanti G. KamathNirapada GhoshDar-ren LeuNilanjan MukherjeeVijoy Pandey
    • Dayavanti G. KamathNirapada GhoshDar-ren LeuNilanjan MukherjeeVijoy Pandey
    • G06F9/46
    • G06F9/52G06F9/4881G06F2209/486
    • A technique for executing normally interruptible threads of a process in a non-preemptive manner includes in response to a first entry associated with a first message for a first thread reaching a head of a run queue, receiving, by the first thread, a first wake-up signal. In response to receiving the wake-up signal, the first thread waits for a global lock. In response to the first thread receiving the global lock, the first thread retrieves the first message from an associated message queue and processes the retrieved first message. In response to completing the processing of the first message, the first thread transmits a second wake-up signal to a second thread whose associated entry is next in the run queue. Finally, following the transmitting of the second wake-up signal, the first thread releases the global lock.
    • 用于以非预先方式执行进程的正常可中断线程的技术包括响应于与第一消息相关联的第一条目,用于第一线程到达运行队列的头部,由第一线程接收第一唤醒 -up信号。 响应于接收到唤醒信号,第一个线程等待一个全局锁定。 响应于接收全局锁的第一线程,第一线程从相关联的消息队列中检索第一消息并处理检索到的第一消息。 响应于完成第一消息的处理,第一线程向第二线程发送第二唤醒信号,该第二线程的相关条目在下一个运行队列中。 最后,在发送第二个唤醒信号之后,第一个线程释放全局锁定。
    • 19. 发明授权
    • Method for synthesizing linear finite state machines
    • 线性有限状态机的合成方法
    • US08024387B2
    • 2011-09-20
    • US11894393
    • 2007-08-20
    • Janusz RajskiJerzy TyszerMark KassabNilanjan Mukherjee
    • Janusz RajskiJerzy TyszerMark KassabNilanjan Mukherjee
    • G06F7/58
    • G06F7/584G06F2207/583H03K3/84
    • Method and apparatus for synthesizing high-performance linear finite state machines (LFSMs) such as linear feedback shift registers (LFSRs) or cellular automata (CA). Given a characteristic polynomial for the circuit, the method obtains an original LFSM circuit such as a type I or type II LFSR. Feedback connections within the original circuit are then determined. Subsequently, a number of transformations that shift the feedback connections can be applied in such a way that properties of the original circuit are preserved in a modified LFSM circuit. In particular, if the original circuit is represented by a primitive characteristic polynomial, the method preserves the maximum-length property of the original circuit in the modified circuit and enables the modified circuit to produce the same m-sequence as the original circuit. Through the various transformations, a modified LFSM circuit can be created that provides higher performance through shorter feedback connection lines, fewer levels of logic, and lower internal fan-out.
    • 用于合成诸如线性反馈移位寄存器(LFSR)或细胞自动机(CA)的高性能线性有限状态机(LFSM)的方法和装置。 给定电路的特征多项式,该方法获得原始的LFSM电路,如I型或II型LFSR。 然后确定原始电路内的反馈连接。 随后,可以以使原始电路的特性保留在修改的LFSM电路中的方式来应用移动反馈连接的多个变换。 特别地,如果原始电路由原始特征多项式表示,则该方法保留修改电路中原始电路的最大长度特性,并使修改电路能够产生与原始电路相同的m序列。 通过各种转换,可以创建一个修改后的LFSM电路,通过较短的反馈连接线路提供更高的性能,更低的逻辑电平和更低的内部扇出。
    • 20. 发明申请
    • CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELECTIVE COMPACTION OF TEST RESPONSES
    • 测试模式的连续应用和分解以及测试响应的选择性压缩
    • US20110214026A1
    • 2011-09-01
    • US13013712
    • 2011-01-25
    • Janusz RajskiJerzy TyszerMark KassabNilanjan Mukherjee
    • Janusz RajskiJerzy TyszerMark KassabNilanjan Mukherjee
    • G06F11/25
    • G01R31/318547
    • A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.
    • 在测试电路中将测试图案应用于扫描链的方法。 该方法包括提供比特的压缩测试模式; 将压缩的测试图案解压缩为被提供的压缩测试图案的解压缩测试图案; 以及将解压缩的测试图案应用于扫描电路被测电路。 取决于要生成解压缩位的方式,以相同或不同的时钟速率同步地执行提供压缩测试模式,解压缩压缩测试模式和应用解压缩模式的动作。 执行解压缩的电路包括解压缩器,例如适于接收压缩的位测试模式的线性有限状态机。 解压缩器将压缩的测试模式正在接收时,将测试模式解压缩为解压缩的位测试模式。